JP3645979B2 - Data recording / transmission method and data recording / transmission apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to recording / transmission of digital data, and more particularly to a technique for recording / transmitting data at a variable bit rate of a digital compressed image.
[0002]
[Prior art and problems to be solved by the invention]
Conventionally, there is a technique called variable bit rate (VBR) coding in an image compression system represented by MPEG (Moving Picture Image Coding Experts Group). In the variable bit rate encoding, for example, when the difference from one image to the next image is large, the image data to be reproduced is encoded at a high rate, and when the difference is small, the image data is encoded at a low rate. As a result, the average bit rate can be lowered without degrading the image quality, and as a result, the image quality becomes higher than that of a technique called constant bit rate (CBR) coding.
[0003]
Incidentally, an image compression method represented by MPEG is generally applied to two storage systems and communication systems. Of course, the above-described variable bit rate encoding method is also mainly applied to the storage system and the communication system. As an application to the storage system, it is conceivable to record image data on a medium such as a hard disk or a CD-ROM. On the other hand, as an application to a communication system, for example, it is conceivable that image data is transmitted via a wireless or wired transmission path, and the image data is reproduced in real time at a transmission destination.
[0004]
However, when the image data recorded on the hard disk or the like is applied again to the communication system as an application to the storage system, the following problems occur. In order to explain this problem, first, a signal output from an encoder capable of variable bit rate encoding will be described.
[0005]
An encoder that compresses image data and can perform variable bit rate encoding performs encoding while changing the bit rate according to the time code of the original image. Since the stream data output from such an encoder is not at a constant rate, this stream data is output together with output timing information. The output timing information generally includes a “strobe signal” indicating the valid period of stream data, but it is also conceivable to use a “clock signal”. The clock signal here, that is, the clock signal indicating the output timing, is not a clock signal (master clock signal) having a constant period. Hereinafter, the clock signal indicating the output timing is referred to as a “variable clock signal” in distinction from a normal clock signal (master clock signal).
[0006]
The variable clock signal indicates that the stream data is valid at the output of the pulse. Since the bit rate is proportional to the amount of effective stream data, it is proportional to the number of pulses of the variable clock signal. That is, the bit rate can be changed by changing the number of pulses of the variable clock signal. Note that the number of pulses is counted as one square wave of one period.
[0007]
The variable clock signal can be created, for example, as follows. In the encoder, a master clock signal having a fixed period that is a reference for the operation of the encoder is generated, and encoding is performed based on the master clock signal. Here, when realizing a bit rate for a certain period, the bit rate is proportional to the amount of effective stream data. Therefore, effective stream data for achieving a target bit rate is, for example, of the above-mentioned fixed period. The number of pulses corresponding to the master clock signal is calculated. Then, a signal that outputs the calculated number of pulses during the period may be generated as a variable clock signal. Of course, the stream data corresponds to the variable clock signal.
[0008]
For example, in the period A shown in FIG. 15, it is assumed that stream data that should be valid corresponds to two pulses of the master clock signal in order to achieve the target bit rate. At this time, as shown in FIGS. 15A and 15B, a variable clock signal that outputs two pulses in the period A is created. FIG. 15A shows an example in which pulses are thinned out from a master clock signal. FIG. 15B shows an example in which the cycle of the variable clock signal is changed so that two pulses are output in the period A. As described above, the pulse of the variable clock signal may be output at any timing during the period A.
[0009]
The present invention is premised on the above-described encoder that uses a variable clock signal as output timing information, that is, an encoder that outputs a variable clock signal and stream data.
FIG. 12 shows an output example from the encoder assumed in the present invention, and shows a variable clock signal created by thinning out a clock signal having a constant period and stream data corresponding to the variable clock signal. Pulses of the variable clock signal are output in the period T1 and the period T2, and the stream data is valid corresponding to the pulses. That is, stream data corresponding to the number of pulses of the variable clock signal is output corresponding to the pulses of the variable clock signal.
[0010]
In order to explain the problems described later, a method for recording a signal from the encoder when variable bit rate coding is applied to the storage system will be described. For example, consider recording the output from an encoder on a medium such as a hard disk or a CD-ROM. At this time, only the stream data output from the encoder is recorded, and the variable clock signal is not recorded. This is because a change in bit rate can be recognized by analyzing the stream data. Therefore, it is not necessary to record a variable clock signal indicating a change in the variable bit rate. That is, at the time of reproduction, the decoder analyzes the stream data, recognizes the change in the bit rate of the stream data, and reads the stream data from a medium such as a CD-ROM at an appropriate timing. Thus, conventionally, when recording the output from the encoder on a medium such as a hard disk or a CD-ROM, for example, only the stream data is recorded, and the variable clock signal is not recorded.
[0011]
Hereinafter, problems when image data recorded on a hard disk or the like is applied again to a communication system will be described. For example, a case where stream data once stored in a medium is transmitted and an image is reproduced in real time at the transmission destination is taken as an example. In this case, since the reproduction is performed using a decoder at the transmission destination, a change in the bit rate of the transmitted stream data can be recognized. However, the transmission source does not know the transmission timing of the stream data because the variable clock signal that is the information of the output timing of the stream data is not recorded. For this reason, when the decoder reads the stream data at the transmission destination, there is a possibility that the corresponding stream data is not transmitted to the transmission destination buffer. Conversely, stream data may be transmitted at a speed higher than the timing required by the decoder at the transmission destination, and the transmission destination buffer may be saturated.
[0012]
The following two methods are conceivable as methods for solving such problems.
The first method is to provide a decoder at the transmission source, analyze the inside of the stream data, recognize the change in the bit rate, and transmit the stream data. However, according to this method, there is a problem that the configuration of the transmission device as the transmission source becomes complicated.
[0013]
As a second method, a variable clock signal output from the encoder is recorded. However, if the variable clock signal is recorded as it is, a huge storage capacity is required, which is not practical.
For example, a case where a variable clock signal obtained by thinning out the master clock signal as shown in FIG. 12 is recorded will be described. At this time, as shown in FIG. 13, it is assumed that recording is performed by setting the pulse output period of the variable clock signal as 1, and recording the period when the pulse of the variable clock signal is not output (pulses are thinned) as 0. In this case, in order to record the change in the bit rate, it is necessary to record the period when the pulse of the variable clock signal is not output. As a result, a storage capacity corresponding to the number of bits corresponding to the number of pulses of the clock signal having a constant period before thinning out the pulses is required.
[0014]
Thus, consider recording with run-length encoding as shown in FIG. In this method, a continuous length of 0 or 1 is recorded. That is, 0 continues for length 2 in the period T5, 1 continues for length 9 in the period T1, 0 continues for length 11 in the period T6, 1 continues in length 5 in the period T2, and 0 continues in length 5 in the period T7. It will continue. According to this method, for example, if the output period of the variable clock signal continues for 200 bits, if it is recorded as it is, a storage capacity of 200 bits is required, but in order to record a length of 200, an 8-bit binary number (0 to 0) is recorded. It is sufficient to use 255). However, even with this method, if the pulse output period of the variable clock signal and the period in which no pulse is output are alternately repeated, the required storage capacity increases.
[0015]
An object of the present invention is to devise the above-described second method, and to reuse the recorded stream data as an application to the storage system again to the communication system.
[0016]
[Means for Solving the Problems and Effects of the Invention]
The data recording and transmitting method according to claim 1, which has been made to achieve the above-described object, includes a master clock signal corresponding to stream data to be output within a predetermined period in order to achieve a target bit rate for each predetermined period. Based on a variable clock signal set to output pulses corresponding to the number of pulses in the predetermined period and a variable clock signal and stream data input from an encoder capable of outputting stream data output in synchronization with the variable clock signal The quotient calculated by dividing the total number of pulses of the variable clock signal output from the encoder during a predetermined processing period by the number of unit pulses is specified as variable clock signal related information. Recorded at each processing period, and recorded the variable clock signal related information while timing the predetermined processing period A variable clock signal having the number of pulses calculated by multiplying the number of unit pulses is generated and transmitted every predetermined processing period, stream data output together with the variable clock signal from the encoder is recorded, and the recorded stream data is recorded. It is characterized by transmitting in correspondence with the pulse of the variable clock signal to be transmitted.
[0017]
As shown in the prior art described above, in order to output stream data at a variable bit rate, a variable clock signal indicating the validity of the stream data is output from the encoder together with the stream data. However, since recording a variable clock signal as described above requires an enormous storage capacity, conventionally only stream data is recorded. Therefore, once stream data recorded on a recording medium such as a hard disk is not analyzed by a decoder, the transmission timing cannot be determined.
[0018]
Therefore, in the data recording / transmission method of the present invention, in order to achieve the target bit rate, a variable clock signal that outputs pulses corresponding to the number of pulses corresponding to the bit rate in a predetermined period, and the variable clock signal are output in synchronization with the variable clock signal. On the premise of an encoder that outputs stream data, the variable clock signal output from the encoder is converted into variable clock signal related information and recorded to record with a small storage capacity. Based on the clock signal related information, a new variable clock signal is created and transmitted. At the same time, stream data is recorded and transmitted in correspondence with pulses of the variable clock signal. The “master clock signal” is a clock signal having a fixed period that is the basis of the operation of the encoder, and a predetermined period is also measured based on the master clock signal. In that sense, the bit rate in each predetermined period can be expressed as the number of pulses of the master clock signal.
[0019]
Here, the operation related to the variable clock signal will be described in detail.
In the data recording and transmitting method of the present invention, the number of pulses of the variable clock signal is summed up every predetermined processing period. Then, a quotient obtained by dividing the total by the number of unit pulses is recorded as variable clock signal related information for each predetermined processing period.
[0020]
At the time of transmission, a variable clock signal having the number of pulses obtained by multiplying the variable clock signal related information by the number of unit pulses is generated, and transmitted every predetermined processing period while counting the predetermined processing period. However, it cannot be determined from the variable clock signal related information at which timing the pulse of the variable clock signal output from the encoder is output during a predetermined processing period. For this reason, at the time of transmission, a pulse is output at an appropriate timing during a predetermined processing period. For example, considering a fixed clock signal, a variable clock signal that outputs a pulse of the number of pulses calculated from the beginning of the processing period can be created and transmitted by thinning out the pulse of the portion after the processing period. Alternatively, a variable clock signal that outputs the number of pulses calculated in the entire processing period may be generated and transmitted by changing the cycle for each processing period.
[0021]
That is, no matter what timing a pulse is output from the encoder as a variable clock signal, the number of pulses per predetermined period does not change between recording and transmission. For example, FIG. 10A shows a variable clock signal that is thinned out from an encoder, and FIG. 10B shows a variable clock signal to be transmitted. In FIG. 10, the output period of the pulse of the variable clock signal is shown at a high level. As shown in FIG. 10, in each processing period E, F, G, the number of pulses output from the encoder is equal to the number of pulses to be transmitted. That is, the bit rate for each predetermined period can be held.
[0022]
As described above, the pulse transmission timing for each predetermined period is different from the output timing from the encoder. Also in the example of FIG. 10, the pulse transmission timing is from the beginning of each processing period, and is different from the pulse output timing of the variable clock signal from the encoder. However, there is no problem in reproducing with the transmission destination decoder. The reason is that it is only necessary that the corresponding stream data is transmitted to the transmission destination buffer in units of frames at the timing read by the transmission destination decoder. That is, by setting the predetermined processing period to be sufficiently shorter than the frame unit, the transmission timing shift within the predetermined processing period can be ignored during reproduction.
[0023]
As for the storage capacity, the storage capacity does not change even if the variable clock signal has been interrupted during the predetermined processing period by summing up the pulses of the variable clock signal. It becomes. For example, in the processing period G shown in FIG. 10, the pulses of the variable clock signal are output in another period of 50 pulses each, but the total is processed as 100 pulses. Further, it can be recorded as a numerical value to divide the total number of pulses by the number of unit pulses, and the numerical value is equal to or less than a value obtained by dividing the maximum number of pulses of the variable clock signal output in a predetermined period by the number of unit pulses. In FIG. 10, in order to divide the number of unit pulses as 100 pulses, “3” is recorded in the processing period E, “2” is recorded in the processing period F, and “1” is recorded in the processing period G. Further, if the clock signal having a fixed period for generating the variable clock signal and the master clock signal for measuring each processing period have the same period, the maximum number of pulses of the variable clock signal in each processing period E, F, G is Since it is 600 pulses, the recorded numerical value is at most “6” or less.
[0024]
As described above, the variable clock signal related information for holding the transmission timing can be recorded with an extremely small storage capacity as compared with the conventional case, and the data to be transmitted can be reproduced at the transmission destination in real time. That is, the stream data once recorded on the hard disk or the like can be used again for the communication system as an application to the storage system.
[0025]
In the present invention, the quotient obtained by dividing the total number of pulses of the variable clock signal output during a predetermined processing period by the number of unit pulses may be an integer, or may be a decimal depending on conditions. The condition is processing such as rounding down or rounding up to a certain number of digits. This is because the storage capacity necessary for recording increases as the number of digits after the decimal point increases. However, since an error occurs when processing such as rounding down or rounding up is performed, it is desirable to handle the quotient as an integer.
[0026]
Considering handling with integers, it is possible that there will be a remainder. Therefore, as described in claim 2, when the remainder is calculated by dividing the total number of pulses of the variable clock signal in a predetermined processing period by the number of unit pulses, the remaining number of pulses can be changed in the next processing period. You may add to the pulse number of a clock signal. For example, if the number of pulses of the variable clock signal is 350 in the processing period E in FIG. 10, 50 pulses as the remainder divided by the predetermined unit pulse number 100 are the number of pulses of the variable clock signal output in the processing period F. In addition to 200, the number of pulses of the variable clock signal output in the processing period F may be 250.
[0027]
In addition, there may be a case where the total output period from the encoder is not an integral multiple of the predetermined processing period. At this time, there is a last processing period that cannot be divided by a predetermined processing period. Even when the total output period from the encoder is an integral multiple of the predetermined processing period, the number of pulses of the variable clock signal remaining in the last predetermined processing period was output in the next processing period. It can also be added as a thing. Therefore, as described in claim 3, for the variable clock signal output after the last processing period that can be divided when the entire output period from the encoder is divided into predetermined processing periods, the variable clock signal The number of pulses may be recorded directly.
[0028]
For example, in the example shown in FIG. 10, when the entire output period from the encoder is a period of 1900 pulses by the master clock, a period of 100 pulses is generated after the processing period G. At this time, if the number of pulses of the variable clock signal is 70 pulses during the 100 pulse period, a numerical value “70” may be recorded. Further, when the number of pulses of the variable clock signal is 150 in the predetermined period G in FIG. 10, it can be considered that the fractional 50 pulses are output after the last predetermined period G. At this time, the 50 pulses may be recorded as “50”.
[0029]
By the way, as shown in claim 4, the predetermined processing period may be a period in which pulses of an integral multiple of the number of unit pulses are counted based on a clock signal having a fixed period. The reason is that, for example, fractional pulses are not generated in the control, and when this control is configured by a circuit, for example, the circuit configuration is simplified.
[0030]
When the data recording and transmitting method described above is configured as a data recording and transmitting apparatus, a configuration as shown in claim 5 is conceivable. That is, a variable clock signal set to output pulses corresponding to the number of pulses of the master clock signal corresponding to stream data to be output within the predetermined period in order to achieve the target bit rate for each predetermined period, And a data recording / transmitting apparatus for recording and transmitting data based on the variable clock signal and stream data input from an encoder capable of outputting stream data output in synchronization with the variable clock signal, and output from the encoder Stream data recording means for recording stream data, master clock signal creating means for creating a master clock signal, timing means for timing a predetermined processing period based on the master clock signal creating means, and a variable clock output from the encoder Count the pulses of the signal and Is counted every time the number of unit pulses becomes equal, and the counting means for counting the number of judgments, and the number of judgments counted by the counting means at the end of the timing of the predetermined processing period by the timing means. A recording initialization means for recording and initializing; a pulse number calculating means for reading the number of judgments recorded by the recording initialization means; and multiplying the read judgment number by a unit pulse number; A variable clock signal transmitting means for generating and transmitting a variable clock signal having the number of pulses calculated by the pulse number calculating means during a predetermined processing period timed by, and a variable clock signal pulse transmitted by the variable clock signal transmitting means. Correspondingly, stream data transmission means for transmitting the stream data recorded by the stream data recording means, A data recording transmitting apparatus characterized by was e.
[0031]
According to the data recording and transmitting apparatus of the present invention, data encoded at a variable bit rate is recorded, and the recorded data is transmitted. Hereinafter, the operation in data recording will be described in (1), and the operation in data transmission will be described in (2).
(1) First, the operation in data recording will be described. First, the stream data recording means determines the validity based on the pulse of the variable clock signal from the encoder and records the stream data. The master clock signal creating means creates a master clock signal having a constant period. At this time, two clock generators as one of the master clock signal generating means may be prepared for data recording and transmission, or may be shared for data recording and transmission. . However, in the case where another data is transmitted while recording certain data, it is desirable to prepare two clock generators for recording and transmission. In addition, when the variable clock signal output from the encoder is a signal obtained by thinning a pulse from a clock signal having a fixed period, it may be considered to create a master clock signal based on the pulse output of the variable clock signal. In this case, data can be recorded in synchronization with the output of the encoder.
[0032]
The time measuring means measures a predetermined processing period based on the created master clock signal. The counting means counts the pulses of the variable clock signal output from the encoder, determines that the sum is equal to the number of unit pulses, and counts the number of determinations. Then, the recording initialization unit records and initializes the number of determinations when the timing of the predetermined processing period ends. Here, “initialization” means that when it is determined that the number of pulses of the variable clock signal becomes equal to the number of unit pulses, the number of determinations is “1”.
[0033]
Here, the operation in the above-described data recording will be described in detail based on the time chart shown in FIG. 11A, and as a result, the capacity required for storing the variable clock signal will be reduced. In FIG. 11A, the number of unit pulses is 400, and the predetermined processing period is a period of 6400 pulses of the master clock signal. In this case, it is assumed that the variable clock signal output from the encoder is obtained by thinning out a clock signal having a constant period.
[0034]
FIG. 11A shows a variable clock signal and stream data output from the encoder. In order to simplify the drawing, the pulse output period of the variable clock signal is shown as a high level. In FIG. 11A, the period [t0 to t4], the period [t5 to t7], and the period [t9 to t11] are pulse output periods of the variable clock signal. Stream data is validated corresponding to the pulses output during these periods. That is, as many stream data as the number of pulses of the variable clock signal are output. The stream data recording means records this stream data.
[0035]
In FIG. 11A, the period [t0 to t8] and the period [t8 to t12] are predetermined processing periods (periods of the master clock signal 6400 pulses) measured by the timing unit. The counting means counts the number of pulses of the variable clock signal, determines every time it becomes equal to 400 pulses, determines that it is equal, and counts the number of determinations. In FIG. 11A, the periods [t0 to t1], [t1 to t2], [t2 to t3], and [t10 to t11] are 400 pulses of the master clock signal, and the periods [t3 to t4], [ Each of t5 to t6], [t6 to t7], and [t9 to t10] is 200 pulses. Therefore, the time when it is determined that 400 pulses have been output is time t1, t2, t3, t6, t10, t11.
[0036]
At this time, the recording initialization means records and initializes the number of times of determination at the end of the timing of the predetermined processing period by the timing means. That is, in FIG. 11A, the number of determinations is recorded and initialized at times t8 and t12. Since the number of determinations at time t8 is four at times t1, t2, t3, and t6, “4” is recorded. Here, since it is once initialized, the number of determinations is newly “1” at time t10, and the number of determinations recorded at t12 is “2”. That is, a group of 400 pulses is recorded and the number of the master clock signals is recorded for every 6400 pulses of the master clock signal.
[0037]
According to this method, for example, when the maximum number of pulses of the variable clock signal is 6400 pulses, the maximum value “16” (6400 ÷ 400) is recorded, and when the number of pulses of the variable clock signal is 0, The minimum value “0” is recorded. That is, it is only necessary to have a storage capacity capable of recording a binary number that can represent “0” to “16”, for example, a 5-bit binary number, every 6400 pulses output by the master clock signal. That is, if the pulse output is recorded as 1, a storage capacity of 6400 bits is required, but 5 bits is sufficient in this example. Further, even if the pulse output of the variable clock signal is not continuous during the period when 6400 pulses are output as the master clock signal, the necessary storage capacity does not change. That is, the storage capacity is not increased by the pulse output period of the variable clock signal as in the above-described run length encoding method.
[0038]
(2) Next, the operation in data transmission will be described.
The pulse number calculation means reads the recorded number of determinations, and calculates the number of pulses by multiplying the read number of determinations by the number of unit pulses. Then, the variable clock signal transmission means creates and transmits a variable clock signal for transmitting the calculated number of pulses in a predetermined processing period. The stream data transmitting means transmits the stream data recorded in synchronization with the transmitted variable clock signal.
[0039]
Here, based on the time chart shown in FIG. 11B, the operation in the above-mentioned data transmission will be described in detail, and the recorded data can be transmitted to the transmission destination and reproduced as an application to the communication system. Will be explained. FIG. 11B shows a variable clock signal to be transmitted and stream data transmitted in synchronization with the variable clock signal.
[0040]
The time measuring means measures a predetermined processing period based on the master clock signal having a fixed period output by the master clock signal creating means. Assuming that the number of unit pulses is 400 pulses and the predetermined processing period is a period of 6400 pulses by the master clock signal in correspondence with the example of FIG. 11A, the period [t13 to t15] in FIG. The period [t15 to t17] is a predetermined processing period.
[0041]
The pulse number calculation means multiplies the recorded number of determinations by the unit pulse number 400 to calculate the pulse number. That is, in FIG. 11A, the determination number “4” is recorded in the first predetermined processing period, and the determination number “2” is recorded in the next predetermined processing period. Therefore, 400 × 4 = 1600 and 400 × 2 = 800 are calculated as the number of pulses.
[0042]
Then, as shown in FIG. 11 (b), the variable clock signal transmission means creates a variable clock signal to be transmitted in a predetermined processing period with the number of pulses of 1600 pulses and 800 pulses in this case. Then, the first variable clock signal is transmitted from time t13, and the next variable clock signal is transmitted from time t15.
[0043]
The stream data transmission means transmits the recorded stream data in correspondence with the pulse of the variable clock signal. In FIG. 11B, the stream data recorded in the periods [t13 to t14] and [t15 to t16] are transmitted in correspondence with the pulses.
[0044]
According to this, the transmission timing of the stream data is deviated from the output timing from the encoder. For example, the stream data B output in the period [t5 to t6] in FIG. 11A is transmitted continuously to the transmission of the stream data A in FIG. Further, the stream data C output in the period [t6 to t7] in FIG. 11A is transmitted from time t15 in FIG. 11B. Furthermore, the stream data D transmitted in the period [t9 to t11] in FIG. 11A is transmitted continuously with the transmission of the stream data C in FIG.
[0045]
However, there is no problem in reproducing the data. The reason will be explained.
Conventionally, since the variable clock signal has never been recorded, the transmission timing is not known, and the reproduction of the fact that the corresponding stream data cannot be transmitted to the transmission destination buffer at the timing when the transmission destination decoder tries to read is possible. It was a reason that could not be done. That is, it is not necessary to transmit at exactly the same timing as the output of the encoder, as long as the corresponding stream data can be transmitted to the transmission destination buffer at the timing at which the transmission destination decoder attempts to read. Further, it is sufficient that this timing can be transmitted in units of frames. For this reason, the period of 6400 pulses counted by the master clock signal is a sufficiently small period when viewed from the stream data of one frame, and such a shift is not a problem.
[0046]
As described above in (1) and (2), according to the data recording / transmitting apparatus of the present invention, the variable clock signal can be stored with a small storage capacity, and the stream data is transmitted based on the variable clock signal to be temporarily stored. Even the stream data can be transmitted and reproduced in real time at the transmission destination. Data once recorded as an application to the storage system can be applied again to the communication system.
[0047]
The data recording / transmission apparatus of the present invention is not limited to the variable clock signal as shown in the example shown in FIG. 11, that is, the variable clock signal created by thinning out the clock signal having a constant period. For example, the variable clock signal output from the encoder may have a form in which the cycle changes every period. For example, it is a variable clock signal that outputs a pulse in all periods [t0 to t12] in FIG. 11, and for example, in each period [t0 to t7], [t7 to t8], and [t8 to t12]. A variable clock signal that changes the cycle may be used. On the other hand, regarding transmission, a variable clock signal having a cycle changed so as to transmit a pulse calculated in a predetermined processing period may be generated and transmitted. For example, you may transmit the variable clock signal which changed the period in each period so that the pulse of 1600 pulses and 800 pulses may be output in period [t13-t15] and [t15-t17].
[0048]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of a data recording / transmitting apparatus 1 of the present embodiment.
[0049]
The data recording / transmitting device 1 includes a data holding circuit 10, a data transmitting circuit 20, a control unit 50 that controls the entire data recording / transmitting device 1, and a hard disk drive (hereinafter referred to as "HDD") in the data recording / transmitting device 1. 70 is provided with a disk interface 61 for connecting 70, and an input / output interface 62 for connecting a CD-ROM writer or the like to the data recording / transmitting apparatus 1.
[0050]
The control unit 50 includes a CPU 51 as control means, a ROM 52 as program storage means, and a RAM 53 as temporary storage means. The CPU 51 performs data recording and reading processing, which will be described later, based on a program stored in advance in the ROM 52. When this data recording and reading process is executed, the RAM 53 functions as a work area.
[0051]
The data holding circuit 10 is connected to an encoder 80 that can encode data at a variable bit rate. A terminal 82 and a video device 85 are connected to the encoder 80. The encoder 80 encodes video data output from the video device 85 and outputs a variable clock signal and stream data. The bit rate at this time is instructed by the terminal 82. For example, a time table 83 indicating the correspondence between the time code and the bit rate as shown in FIG. 17 is prepared in the terminal 82, and the bit rate corresponding to the time code of the video data of the video device 85 is indicated. Become.
[0052]
The encoder 80 creates a variable clock signal as follows, for example, in order to output stream data at a target bit rate instructed corresponding to the time code of the video data from the video device 85. In the encoder 80, a master clock signal having a fixed period that is a reference for the operation of the encoder 80 is created, and encoding is performed based on the master clock signal. Here, when the target bit rate is realized in the period corresponding to the time code, since the bit rate is proportional to the amount of effective stream data, effective stream data for achieving the target bit rate is For example, the number of pulses corresponding to the master clock signal having the fixed period is calculated. Then, a signal that outputs the calculated number of pulses in a period corresponding to the time code is created as a variable clock signal. Of course, the stream data corresponds to the variable clock signal.
[0053]
For example, in the period A shown in FIG. 15, it is assumed that stream data that should be valid corresponds to two pulses of the master clock signal in order to achieve the target bit rate. At this time, as shown in FIGS. 15A and 15B, a variable clock signal that outputs two pulses in the period A is created. FIG. 15A shows an example in which pulses are thinned out from a master clock signal. FIG. 15B shows an example in which the cycle of the variable clock signal is changed so that two pulses are output in the period A. As described above, the pulse of the variable clock signal may be output at any timing during the period A. As shown in FIG. 15A, the encoder 80 according to the present embodiment outputs a variable clock signal in a form in which the master clock signal of the encoder 80 is thinned out.
[0054]
The data holding circuit 10 extracts and holds variable clock signal related information and stream data based on the two data of the variable clock signal and stream data from the encoder 80. As described above, the validity of the stream data is indicated by the pulse output of the variable clock signal.
[0055]
In parallel with the extraction of the variable clock signal related information and the valid stream data by the data holding circuit 10, the control unit 50 reads the held variable clock signal related information and the valid stream data from the data holding circuit 10 and stores them in the HDD 70. Record. Also, the variable clock signal related information and valid stream data recorded in the HDD 70 are read, the number of pulses of the variable clock signal is calculated from the variable clock signal related information, and the calculated number of pulses of the variable clock signal and the stream data are stored in the data. The data is sequentially transferred to the transmission circuit 20.
[0056]
The data transmission circuit 20 newly creates a variable clock signal based on the number of pulses of the variable clock signal transferred by the control unit 50, transmits the variable clock signal to the reproduction device 90 via the transmission path 94, and transfers it by the control unit 50. The received stream data is made to correspond to the pulse of the variable clock signal and transmitted to the reproducing apparatus 90 via the transmission path 94.
The playback device 90 includes a buffer 91 that temporarily records data transmitted from the data transmission circuit 20, a decoder 92 that analyzes and plays back the stream data transmitted to the buffer 91, and a monitor 93 that displays playback video. It has.
[0057]
As described above, the data recording / transmitting apparatus 1 according to the present embodiment records the data output from the encoder 80 at the variable bit rate once in the HDD 70, and then reproduces it again in real time on the reproducing apparatus 90 as the transmission destination. The recorded data is transmitted. Further, the data recording / transmitting apparatus 1 according to the present embodiment can record only stream data on a storage medium such as a CD-ROM as usual through the input / output interface 62.
[0058]
Next, the data holding circuit 10, the data transmission circuit 20, and the control unit 50, which are features of the data recording / transmission apparatus 1 of this embodiment, will be described in detail. (A) The configuration and function of the data holding circuit 10, (b) The data recording processing from the data holding circuit 10 by the control unit 50 and the operation of the data holding circuit 10 associated therewith, (c) The data transmission circuit 20, the data transfer process to the data transmission circuit 20 by the control unit 50 and the operation of the data transmission circuit 20 associated therewith will be described. Further, in the following description, the “predetermined processing period” is a period of 6400 pulses, “unit pulse”, which is the number of pulses of a master clock signal having a fixed period created by a clock generator (described later) of the data recording and transmitting apparatus 1 of the present embodiment. A specific numerical value of 400 pulses is used as the “number”.
[0059]
(A) The configuration and function of the data holding circuit 10 will be described based on the circuit diagram shown in FIG.
The data holding circuit 10 includes a master clock generator 111 as a “master clock signal generating unit” that generates a master clock signal from the variable clock signal from the encoder 80, and 6400 based on the master clock signal generated by the master clock generator 111. T-counter 101 as a “timer” for measuring the pulse processing period, r-counter 103 for counting the pulses of the variable clock signal, and counting up by an active signal output every 400 pulses from the r-counter 103 h The counter 104, the latch 102 that holds an active signal output every 6400 pulses from the T counter 101, and the latch that holds the value of the h counter 104 when an active signal is output from the T counter 101 And a 05.
[0060]
As shown in FIG. 4, the master clock generator 111 creates a master clock signal before thinning out from the thinned variable clock signal. The master clock generator 111 includes a master clock oscillator 112 that creates a master clock with a fixed period, and a PLL 113 that corrects the period of the master clock signal created by the master clock oscillator 112 based on the pulse output of the variable clock signal. .
[0061]
That is, consider the case where the variable clock signal that has been thinned is output from the encoder 80 as shown in FIG. The master clock oscillator 112 creates a master clock signal having a period close to that of the master clock signal of the encoder 80 before thinning. Then, the PLL 113 corrects the time lag of the pulses generated by the master clock oscillator 112 at the rising edge of the pulse of the variable clock signal at t19, t20, t21, t22, and t23 in FIG. Synchronize with the signal. As a result, data can be recorded in synchronization with the operation of the encoder 80.
[0062]
The r counter 103 counts the pulses of the variable clock signal and outputs an active signal to the h counter 104 every 400 pulses. The count value of the h counter 104 is held in the latch 105 by an active signal output from the T counter 101 every 6400 pulses. As a result, the integer quotient obtained by dividing the sum of the pulses of the variable clock signal in the predetermined processing period of 6400 pulses by the unit period of 400 pulses is held in the latch 105. That is, the value of the h counter 104 held in the latch 105 becomes “variable clock signal related information”. When the count value of the h counter 104 is held in the latch 105, immediately after that, the h counter 104 is cleared to zero. The r counter 103 and the h counter 104 correspond to “counting means”. Note that when the active signal is held in the latch 102, the variable clock signal related information held in the latch 105 can be read out, and the variable clock signal related information held in the latch 105 is read out by the control unit 50. The latch 102 is cleared.
[0063]
Further, the data holding circuit 10 includes an address decoder 106 that manages access from the control unit 50, a shift register 109 that converts stream data into 8-bit units, and an active signal every 8 bits based on the created master clock signal. An output 8-bit counter 107, a latch 108 for holding an active signal output from the 8-bit counter 107 every 8 bits, and an active signal output from the 8-bit counter are input to the shift register 109. And a latch 110 that holds the streamed 8-bit stream data.
[0064]
The address decoder 106 is connected to an address bus, and is configured to output corresponding data on the data bus when accessed from the control unit 50. The latch 108 is cleared when the stream data held in the latch 110 is read by the control unit 50.
[0065]
The 8-bit counter 107 and the shift register 109 are input with a variable clock signal and are configured to operate in response to the pulse of the variable clock signal. As a result, the stream data input to the shift register 109 corresponds to the pulse of the variable clock signal.
[0066]
(B) Next, the data recording processing from the data holding circuit 10 by the control unit 50 and the operation of the data holding circuit 10 associated therewith will be described. The data recording process by the controller 50 will be described based on the flowchart of FIG. 3, and the operation of the data holding circuit 10 will be described based on the circuit diagram of FIG.
[0067]
In the first step S1000 in FIG. 3, a file for recording stream data is opened. In subsequent S1010, a file for recording variable clock signal related information is opened. A file for recording stream data and a file for recording variable clock signal related information are prepared in the HDD 70.
[0068]
Next, in S1020, it is determined whether or not an active signal is held in the latch 108 in FIG. This process is a process for determining whether or not the stream data is held in the latch 110 in FIG. The 8-bit stream data corresponding to the pulse of the variable clock signal is input to the shift register 109, and the 8-bit stream data is held in the latch 110 by the active signal from the 8-bit counter 107. An active signal from 107 is held in the latch 108.
[0069]
If an affirmative determination is made in S1020, that is, if an active signal is held in the latch 108, the 8-bit stream data held in the latch 110 is read in S1030, and the contents of the HDD 70 are read in S1040. Record the stream data in a file for recording. Then, the process proceeds to S1050. On the other hand, if a negative determination is made in S1020, that is, if an active signal is not held in the latch 108, the processing proceeds to S1050 without performing the processing of S1030 and S1040. Note that the latch 108 is cleared simultaneously with the reading process in S1030.
[0070]
In S1050, it is determined whether or not an active signal from the T counter 101 is held in the latch 102. This processing is processing for determining whether or not the variable clock signal related information corresponding to the processing period of 6400 pulses is held in the latch 105. When the T counter 101 measures the processing period of 6400 pulses and outputs an active signal, the count value of the h counter 104 is held in the latch 105 as variable clock signal related information, and the active signal from the T counter 101 is It is held by the latch 102. Immediately thereafter, the h counter 104 is cleared to zero.
[0071]
If an affirmative determination is made in S1050, that is, if an active signal is held in the latch 102, the variable clock signal related information held in the latch 105 is read in S1060, and the variable clock signal related information is read in S1070. Is recorded in a file in the HDD 70 for recording. Then, the process proceeds to S1080. On the other hand, if a negative determination is made in S1050, that is, if an active signal is not held in the latch 102, the processing proceeds to S1080 without executing the processing of S1060 and S1070.
[0072]
Note that the latch 102 is cleared simultaneously with the reading process in S1060. In S1070, the variable clock signal related information is recorded in the file in the HDD 70 in the format shown in FIG. That is, a storage capacity of 8 bits is allocated as a storage capacity of one variable clock signal related information, 0 is recorded in the most significant bit, and variable clock signal related information is recorded in the lower 7 bits. In FIG. 16, the variable clock signal related information in the first processing period is 4, and the variable clock signal related information in the next processing period is 2. In this way, the variable clock signal related information is stored in order with the most significant pulse as 0, and the number of pulses of the variable clock signal less than 400 pulses remaining in the r counter 103 is recorded in the last row. At this time, the most significant pulse is recorded as 1 in order to distinguish it from the variable clock signal related information recorded in units of 400 pulses.
[0073]
In S1080, it is determined whether or not the data output from the encoder 80 is completed. If a negative determination is made in S1080, that is, if data output from the encoder 80 has not been completed, the process proceeds to S1020, and the subsequent processing is repeated. On the other hand, if an affirmative determination is made in S1080, that is, if the data output from the encoder 80 is completed, the flow proceeds to S1090.
[0074]
In S1090, the number of pulses of the variable clock signal of less than 400 pulses remaining in the r counter 103 at the end of the output from the encoder 80 is read, and the number of pulses of the variable clock signal is directly recorded. Although omitted in FIG. 2 because it becomes complicated, a circuit for reading the count value of the r counter 103 is prepared in order to extract the number of pulses described above. The number of variable clock signal pulses less than 400 pulses remaining in the r counter 103 is recorded in the last row of the format shown in FIG. 16 as described above. In this case, the most significant pulse is set to 1 and the lower 7 pulses The count value of the r counter is recorded in.
[0075]
In subsequent S1100, the file for recording the stream data is closed. In step S1110, the file for recording the variable clock signal related information is closed, and the data recording process ends.
For example, when recording on a CD-ROM or the like, the stream data recorded in the file in which the stream data is recorded may be read out and recorded via the input / output interface 62. The control unit 50 corresponds to “recording initialization unit” and “stream data recording unit”, and among the processing executed by the control unit 50, S1060 and S1070 correspond to processing as recording initialization unit. S1040 corresponds to processing as a stream data recording unit.
[0076]
(C) FIG. 6 is a circuit diagram showing a circuit configuration of the data transmission circuit 20. Next, the configuration and function of the data transmission circuit 20 will be described based on the circuit diagram shown in FIG.
The data transmission circuit 20 measures a processing period of 6400 pulses based on a master clock generator 135 serving as a “master clock signal creation unit” that outputs a master clock signal having a fixed period, and a master clock signal from the master clock generator 135. A T-counter 137 as a “timer”, an address decoder 134 which is connected to the address bus and manages access to the data transmission circuit 20 from the control unit 50 shown in FIG. 1, and the HDD 50 shown in FIG. The variable clock signal related information is read, a clock latch 140 that holds the number of pulses of the variable clock signal calculated from the variable clock signal related information, and the master clock generator based on the number of pulses transferred from the clock latch 140. And a clock counter 139 as a "variable clock signal transmitter" generating and transmitting a variable clock signal based on the master clock signal 135. Signals H to M are output from the address decoder 134 in response to the access of the control unit 50.
[0077]
The data transmission circuit 20 also has a latch 131 that holds stream data read from the HDD 70 by the control unit 50 in 8-bit units, and 8-bit stream data transferred from the latch 131 in 1-bit units (serial). And a shift register 132 that transmits to the buffer 91 based on the master clock signal from the master clock generator 135, and an 8-bit counter 133 that measures an 8-bit period based on the master clock signal from the master clock generator 135. ing.
[0078]
The variable clock signal output from the clock counter 139 is input to the enable terminals of the shift register 132 and the 8-bit counter 133, and is configured to operate in response to the pulse of the variable clock signal. As a result, the stream data is transmitted corresponding to the pulse of the variable clock signal. The shift register 132 corresponds to “stream data transmission means”.
[0079]
Furthermore, the data transmission circuit 20 includes a latch 136 for holding an active signal output every time the 8-bit counter 133 counts an 8-bit period, and an active signal output by the T counter 137 every 6400 pulses. And a latch 138 for holding. The latch 136 is for determining the timing at which the control unit 50 writes stream data to the latch 131, and the latch 138 is for determining the timing at which the control unit 50 writes the number of pulses of the variable clock signal to the clock latch 140. Is. The latch 136 and the latch 138 are cleared by signals I and K output from the address decoder 134 at the same time as the writing by the control unit 50 is performed.
[0080]
Further, the data transmission circuit 20 receives a two-input OR 142 to which an output from the 8-bit counter 133 and a signal H from the address decoder 134 are input, and an output from the T counter 137 and a signal J from the address decoder 134. 2 inputs OR141. The output of the 2-input OR 142 is input to the LD terminal of the shift register 132, and the output of the 2-input OR 141 is input to the LD terminal of the clock counter 139.
[0081]
As a result, when the signal H from the address decoder 134 becomes active or when the output from the 8-bit counter 133 becomes active, the stream data held in the latch 131 is transferred to the shift register 132. Similarly, when the signal J from the address decoder becomes active or when the output from the T counter becomes active, the number of pulses of the variable clock signal held in the clock latch 140 is transferred to the clock counter 139.
[0082]
A signal L of the address decoder 134 is input to the enable terminal of the T counter 137. When this signal L becomes active, data transmission is started. (D) Next, the data transfer process to the data transmission circuit 20 by the control unit 50 and the operation of the data transmission circuit 20 associated therewith will be described. The data transfer processing by the control unit 50 will be described based on the flowcharts of FIGS. 7, 8, and 9, and the operation of the data transmission circuit 20 will be described based on the circuit diagram of FIG.
[0083]
In the first step S1200 in FIG. 7, the control unit 50 opens a file in which variable clock signal related information is recorded and a file in which stream data is recorded. In subsequent S1210, the stream data is read in units of 8 bits from the file in the HDD 70 in which the stream data is recorded. In step S1220, the read stream data is written to the latch 131 in FIG. With this process, the latch 136 is cleared.
[0084]
In S 1230, the 8-bit stream data held in the latch 131 in FIG. 6 is transferred to the shift register 132. This is performed by activating the signal H from the address decoder 134, which is an input signal to the LD terminal of the shift register 132.
[0085]
In S1240 and S1250, the same processing as S1210 and S1220 described above is performed. That is, the stream data is read out in units of 8 bits from the file in which the stream data is recorded (S1240), and the read stream data is written to the latch 131 (S1250).
[0086]
By the processing of S1210 to S1250, the 8-bit stream data is held in the shift register 132, and the subsequent 8-bit stream data is held in the latch 131.
In S1260, the variable clock signal related information is read from the file in the HDD 70 in which the variable clock signal related information is recorded. In subsequent S1261, the number of pulses of the variable clock signal for the processing period of 6400 pulses is calculated based on the read variable clock signal related information. This pulse number calculation process will be described later. In S1262, the calculated number of pulses of the variable clock signal is written to the clock latch 140 in FIG.
[0087]
In S 1263, the number of pulses of the variable clock signal held in the clock latch 140 is transferred to the clock counter 139. This is performed by activating the signal K from the address decoder 134, which is an input signal to the LD terminal of the clock counter 139.
[0088]
In S1264 to S1266, the same processing as S1260 to S1262 is performed. That is, the variable clock signal related information is read from the file in the HDD 70 in which the variable clock signal related information is recorded (S1264), the number of pulses of the variable clock signal is calculated (S1265), and written to the clock latch 140 (S1266).
[0089]
By the processing of S1260 to S1266, the number of pulses of the variable clock signal corresponding to the first 6400 pulse processing period is set in the clock counter 139 in FIG. 6, and the clock latch 140 corresponds to the next 6400 pulse processing period. The number of pulses of the variable clock signal to be held is held.
[0090]
Then, the start of transmission is instructed in S1267 in FIG. This process is to activate the signal L from the address decoder 134, which is an input signal to the enable terminal of the T counter 137. As a result, the T counter 137 in FIG. 6 starts to operate in synchronization with the master clock signal from the master clock generator 135.
[0091]
The clock counter 139 in FIG. 6 outputs pulses to the buffer 91 while counting the set number of pulses, and stops outputting pulses when the counting of the number of pulses is completed. The T counter 137 outputs an active signal when the processing period of 6400 pulses is counted. This signal is held in the latch 138 and simultaneously input to the LD terminal of the clock counter 139. By inputting an active signal to the LD terminal, the number of pulses of the variable clock signal in the next processing period is transferred from the clock latch 140 to the clock counter 139.
[0092]
While the clock counter 139 outputs a pulse as a variable clock signal, the pulse is also input to the enable terminal of the 8-bit counter 133 and the shift register 132. The 8-bit counter 133 and the shift register 132 operate.
[0093]
The shift register 132 transmits the set 8-bit stream data in 1-bit units (bit serial). The 8-bit counter outputs an active signal every 8 bits. This signal is held in the latch 136 and is input to the LD terminal of the shift register 132 via the two-input OR 142. When an active signal is input to the LD terminal, the shift register 132 transfers the next 8-bit stream data from the latch 131.
[0094]
In this way, the clock counter 139 transfers the number of pulses of the variable clock signal every 6400 pulses based on the T counter 137 from the clock latch 140, and the shift register 132 outputs 8 bits while the clock counter 139 outputs pulses. The stream data is transferred from the latch 131 every time.
[0095]
Corresponding to these data transmission operations, the control unit 50 writes data to the clock latch 140 and the latch 131 as described below.
In S 1270, it is determined whether or not an active signal is held in the latch 136. This process is a process for determining whether or not 8-bit stream data held in the latch 131 has already been transferred to the shift register 132. When the 8-bit period is clocked by the 8-bit counter 133 and the stream data held in the latch 131 is transferred to the shift register 132, the latch 136 receives the active signal output from the counter 133 that clocks the 8-bit period. The signal is retained.
[0096]
If an affirmative determination is made in S1270, that is, if an active signal is held in the latch 136, the stream data is read in 8-bit units from the file in the HDD 70 in which the stream data is recorded in S1280, and in S1290, Write to the read stream data latch 131. At this time, the address decoder 134 outputs the signal I for the latch 136 in an active state, and the latch 136 is cleared. On the other hand, if a negative determination is made in S1270, that is, if an active signal is not held in the latch 136, the processing proceeds to S1300 without executing the processing in S1280 and S1290.
[0097]
In S1300, it is determined whether or not an active signal is held in the latch 138. This process is a process for determining whether or not the number of pulses of the variable clock signal held in the clock latch 140 has already been transferred to the clock counter 139. When the processing period of 6400 pulses is timed and the number of pulses of the variable clock signal held in the clock latch 140 is transferred to the clock counter 139, the latch 138 receives from the T counter 137 that measures the processing period of 6400 pulses. Active signal is held.
[0098]
If an affirmative determination is made in S1300, that is, if an active signal is held in the latch 138, the variable clock signal related information is read from the file in the HDD 70 in which the variable clock signal related information is recorded in S1310, and S1315 In step S1320, the number of pulses of the variable clock signal is calculated from the variable clock signal related information, and the calculated number of pulses is written to the clock latch 140 in step S1320. In the writing process in S1320, the signal K from the address decoder 134 becomes active, and the latch 138 is cleared. On the other hand, if a negative determination is made in S1300, that is, if an active signal is not held in the latch 138, the processing of S1310 to S1320 is not executed and the processing proceeds to S1330.
[0099]
In S1330, it is determined whether all stream data has been read. If all the stream data has been read (S1330: YES), the file in which the stream data is recorded and the file in which the variable clock signal related information is recorded are closed in S1340, and this data reading process ends. On the other hand, when all the stream data has not been read (S1330: NO), the process proceeds to S1270 and the subsequent processing is repeated.
[0100]
The control unit 50 corresponds to “pulse number calculation means”, and among the processing executed by the control unit 50, steps S1260, S1261, S1264, S1265, S1310, and S1315 correspond to processing as pulse number calculation means.
Next, the pulse number calculation processing shown in S1261, S1265, and S1315 will be described based on the flowchart of FIG.
[0101]
First, in first step S1400, it is determined whether or not the most significant bit of the read variable clock signal related information is zero. When the most significant bit is 0 (S1400: YES), the variable clock signal related information is multiplied by 400. On the other hand, if the most significant pulse is not 0 (S1400: NO), the processing of S1410 is not executed and the present pulse number calculation processing is terminated. In other words, the variable clock signal related information that is normally recorded with the most significant pulse being 0 is the quotient obtained by dividing the total number of pulses by the unit period of 400 pulses, so the number of pulses is calculated by multiplying by 400. The number of pulses of the variable clock signal remaining in the r counter 103 in FIG. 2 at the end of the data recording process is recorded with the most significant pulse as 1, as described above. In this case, since the pulse number is directly recorded, the read variable clock signal related information becomes the pulse number of the variable clock signal as it is.
[0102]
The operation of the data recording and transmitting apparatus 1 of the present embodiment described above will be specifically described based on the timing chart of FIG. Note that the variable clock signal shown in FIG. 11 represents a pulse output period at a high level. In other words, it indicates that pulses are output at a constant cycle when in a high level state.
[0103]
First, the data recording operation will be described with reference to FIG.
FIG. 11A shows a variable clock signal and stream data output from the encoder 80. In FIG. 11A, the period [t0 to t4], the period [t5 to t7], and the period [t9 to t11] are pulse output periods of the variable clock signal. Stream data is validated corresponding to the pulses of the variable clock signal output during these periods.
[0104]
Here, as shown in FIG. 2, the variable clock signal is input to the shift register 109 for extracting the stream data and the 8-bit counter 107 for extracting the stream data in units of 8 bits, corresponding to the pulses of the variable clock signal. Therefore, valid stream data is held in the latch 110. That is, the stream data corresponding to the pulse of the variable clock signal is recorded by the control unit 50 in the period [t0 to t4], [t5 to t7], and [t9 to t11].
[0105]
At this time, the master clock generator 111 in FIG. 2 creates a master clock signal from the variable clock signal from the encoder 80. The T counter 101 measures a processing period of 6400 pulses based on the master clock signal and outputs an active signal every 6400 pulses. In FIG. 11A, since the period [t0 to t8] and the period [t8 to t12] are 6400 pulses, an active signal is output from the T counter 101 at times t8 and t12.
[0106]
Then, the r counter 103 in FIG. 2 counts the pulses of the variable clock signal, and outputs an active signal to the h counter 104 every time the number of pulses reaches 400 pulses. The h counter 104 counts up when an active signal is output from the r counter 103. In FIG. 11A, the periods [t0 to t1], [t1 to t2], [t2 to t3], and [t10 to t11] are 400 pulses, and the periods [t3 to t4] and [t5 to t6]. , [T6 to t7] and [t9 to t10] are 200 pulses, respectively. Therefore, the time when the active signal is output from the r counter 103 is time t1, t2, t3, t6, t10, t11.
[0107]
When the active signal from the T counter 101 is held in the latch 102 in FIG. 2, the control unit 50 records the count value of the h counter 104 that is information related to the variable clock signal held in the latch 105 to the HDD 70. To do. Then, the value of the latch 105 is read, and at the same time, the latch 102 is cleared. That is, in FIG. 11A, since the active signal is held in the latch 102 at times t8 and t12, the variable clock signal related information held in the latch 105 is recorded immediately thereafter. The value of the latch 105 at time t8 is “4” because the h counter 104 is counted up at times t1, t2, t3, and t6. Here, since the h counter 104 is cleared to 0, the value of the h counter 104 is newly “1” at time t10, the value of the h counter 104 is “2” at t12, and therefore the latch 105 at t12. The value of is “2”.
[0108]
As can be seen from the above description, when a variable clock signal pulse is output throughout the 6400 pulse processing period, the maximum value “16” is held in the latch 105 and the variable clock signal pulse is transmitted throughout the 6400 pulse processing period. Is not output, the latch 105 holds the minimum value “0”. Therefore, in this embodiment, a storage capacity for recording the variable clock signal related information for the processing period of 6400 pulses may be prepared for 8 bits for each processing period of 6400 pulses. Further, since the r counter 103 in FIG. 2 counts the pulses of the variable clock signal, the pulses of the variable clock signal may be output at any timing during the 6400 pulses. That is, unlike the run-length encoding method shown in the above prior art, the storage capacity is not affected by the variable clock signal.
[0109]
Next, the data transmission operation will be described with reference to FIG.
FIG. 11B shows a variable clock signal to be transmitted and stream data to be transmitted corresponding to the variable clock signal.
A T counter 137 in FIG. 6 measures a processing period of 6400 pulses based on the master clock signal output from the master clock generator 135. The periods [t13 to t15] and [t15 to t17] in FIG. 11B are 6400 pulse processing periods, and the T counter 137 outputs an active signal at times t15 and t17.
[0110]
The control unit 50 reads the variable clock signal related information from the HDD 70 and calculates the number of pulses of the variable clock signal. That is, in FIG. 11A, the value “4” of the latch 105 is recorded as variable clock signal related information in the first processing period, and the value “2” of the latch 105 is recorded in the next processing period. Therefore, the control unit 50 calculates 400 pulses × 4 = 1600 pulses and 400 pulses × 2 = 800 pulses as the number of pulses in each processing period of the variable clock signal.
[0111]
Then, the clock counter 139 transmits a pulse having a cycle of the master clock generator 135 as a variable clock signal while counting the number of pulses transferred and set from the clock latch 140 until time t14 in FIG. 11B. When the set number of pulses becomes zero, no pulse is output until time t15 when the T counter 137 outputs an active signal.
[0112]
The variable clock signal transmitted from the clock counter 139 is input to the enable terminals of the shift register 132 and the 8-bit counter 133 in FIG. 6, and stream data is transmitted in response to the transmission of the variable clock signal. In FIG. 11B, the stream data is transmitted in correspondence with the pulse of the variable clock signal in the period [t13 to t14] and [t15 to t16].
[0113]
According to this, the transmission timing of the stream data is deviated from the output timing from the encoder 80. For example, the stream data B output in the period [t5 to t6] in FIG. 11A is transmitted continuously to the transmission of the stream data A in FIG. Further, the stream data C output in the period [t6 to t7] in FIG. 11A is transmitted from time t15 in FIG. 11B. Furthermore, the stream data D transmitted in the period [t9 to t11] in FIG. 11A is transmitted continuously with the transmission of the stream data C in FIG.
[0114]
The effects exhibited by the data recording / transmitting apparatus 1 of the present embodiment described above will be described in detail.
In the data recording and transmitting apparatus 1 of the present embodiment, the T counter 101 of the data holding circuit 10 shown in FIG. 2 measures a processing period of 6400 pulses, and the variable clock signal related to the latch 105 held every processing period. By recording the information, it is not necessary to record a period during which the pulse of the variable clock signal is not output. This is because the information corresponding to the pulse output period in the 6400 pulse processing period is the variable clock signal related information, and by recording the variable clock signal related information, the period in which the pulse of the variable clock signal is not output can be known naturally. It is.
[0115]
As a result, the storage capacity for a period during which no pulse of the variable clock signal is output can be reduced as compared with the method of recording the entire period of the variable clock signal as shown in the examples of FIGS.
On the other hand, the r counter 103 that counts the number of pulses of the variable clock signal in FIG. 2 counts the number of pulses of the variable clock signal, so that the storage capacity is large no matter what timing the pulses of the variable clock signal are output. There will be no increase. Thus, the variable clock signal related information is information related to the total number of pulses of the variable clock signal during the 6400 pulse processing period, and the storage capacity required for each 6400 pulse processing period is constant.
[0116]
For example, in the method as shown in FIG. 14 described above, when the pulse output is intermittent, the storage capacity increases. On the other hand, in this case, the storage capacity can be made constant regardless of the output timing of the pulses of the variable clock signal.
[0117]
Further, by recording an integer quotient obtained by dividing the total number of pulses of the variable clock signal in the processing period of 6400 pulses by the number of unit pulses of 400 pulses, an increase in storage capacity proportional to the number of pulses of the variable clock signal occurs. Absent. For example, if the number of pulses of the variable clock signal is 1200 pulses, 1600 pulses, and 6000 pulses, a recording capacity proportional to the number of pulses of 1200 bits, 1600 bits, and 6000 bits is required if recording is performed as it is. However, since the integer quotient divided by the number of unit pulses of 400 pulses is recorded, in this case, “3”, “4”, and “15” may be recorded.
[0118]
As a result, the data recording and transmitting apparatus 1 can record the timing information based on the variable clock signal as the variable clock signal related information with a very small storage capacity. For example, consider a case where image data having a master clock signal of the encoder 80 of 10 MHz and an average bit rate of 5 Mbps is recorded for 10 minutes. At this time, if the variable clock signal is recorded as it is, the storage capacity becomes 1500 Mbytes. On the other hand, when recording is performed by the data recording / transmitting apparatus 1, since the storage capacity is 8 bits per 6400 pulses, it is 84.4 Mbytes.
[0119]
Further, in the data recording / transmitting apparatus 1 of the present embodiment, the T counter 137 of the data transmitting circuit 20 shown in FIG. 6 measures the processing period of 6400 pulses, and the T counter 137 outputs an active signal every 6400 pulses. Based on the signal, the control unit 50 reads the variable clock signal related information, and the clock counter 139 transmits the variable clock signal based on the variable clock signal related information. As a result, in the processing period of 6400 pulses, the number of pulses of the variable clock signal transmitted is the same as the number of pulses of the variable clock signal output from the encoder 80. As a result, the stream data can be reproduced in real time by the reproduction apparatus 90 of the transmission destination.
[0120]
However, the bit rate in the processing period unit of 6400 pulses is substantially equal to the bit rate when output from the encoder 80, but as described above, the bit rate in a period smaller than the processing period of 6400 pulses is The bit rate when output from the encoder 80 generally does not match. However, there is no influence on the playback by the playback device 90. The reason for this will be explained. Conventionally, since a variable clock signal has not been recorded, the transmission timing is not known, and the decoder 92 of the transmission destination reproduction device 90 is applicable to the transmission destination buffer 91 at a timing when the decoder 92 tries to read it from the buffer 91. The inability to transmit the stream data was the reason why reproduction was not possible. That is, it is not necessary to transmit at exactly the same timing as the output of the encoder 80 (synchronized in units of pulses), and the stream data corresponding to the buffer 91 of the reproducing device 90 is read at the timing when the decoder 92 of the reproducing device 90 tries to read. It only has to be transmitted. In other words, it is only necessary to transmit one image (in units of frames).
[0121]
The data recording / transmitting apparatus 1 of the present embodiment uses the r counter 103 that indicates the number of pulses of the variable clock signal every 400 pulses, and the r counter when the T counter 101 measures the processing period of 6400 pulses. Reference numeral 103 denotes a fraction of the number of pulses of the variable clock signal. As a result, the remainder obtained by dividing the number of pulses of the variable clock signal in a certain processing period by the number of unit pulses of 400 pulses is added to the number of pulses of the variable clock signal in the next processing period. That is, the variable clock signal related information recorded every 6400 pulses can be handled as an integer, and the number of pulses of the fractional variable clock signal is not lost.
[0122]
Furthermore, the data recording / transmitting apparatus 1 of the present embodiment directly reads and records the number of pulses of the variable clock signal in the last processing period from the r counter 103 in the reading process of the control unit 50. As a result, the number of pulses of the variable clock signal remaining in the last r counter 103 is not lost.
[0123]
In the data recording and transmitting apparatus 1 of the present embodiment, the T counter 101 that measures 6400 pulses, which is an integral multiple of the 400 pulse r counter 103 in FIG. 2, is used. There is also an effect that the circuit configuration is simplified. Further, in the data holding circuit 10 in the data recording and transmitting apparatus 1 of the present embodiment, the master clock generator 111 generates the master clock signal based on the variable clock signal from the encoder. Thereby, it is possible to record data in synchronization with the encoding process of the encoder 80. On the other hand, when the variable clock signal from the encoder 80 is not created by thinning out the master clock signal of the encoder 80 but created by changing the cycle, the master clock signal is the data holding circuit 10 of the present embodiment. You may create your own.
[0124]
As described above, the present invention is not limited to such an embodiment, and can be implemented in various forms without departing from the gist of the present invention.
For example, in the above embodiment, data is transferred by the control unit 50 in units of 8 bits. However, a buffer may be provided to transfer a plurality of bytes at a time. Furthermore, it is useful to use an interrupt or DMA for data transfer.
The file format is not limited to two files as in the above embodiment, but can be combined into one file. In this case, it is necessary to record the variable clock signal related information first. This is because the data length at the time of transmission must be recognized from the variable clock signal related information. As a configuration for that purpose, the stream data is held in the buffer during the processing period of 6400 pulses, and after the variable clock signal related information in the processing period is determined, the variable clock signal related information and the stream data are recorded in the file in this order. You can do it.
[0125]
Further, the processing period and the number of unit pulses are set for each data recording / transmitting apparatus. In this embodiment, the processing period is 6400 pulses and the number of unit pulses is 400 pulses, but the present invention is not limited to this. .
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a schematic configuration of a data recording and transmitting apparatus according to an embodiment.
FIG. 2 is a circuit diagram of a data holding circuit of the data recording and transmitting apparatus according to the embodiment.
FIG. 3 is a flowchart showing data recording processing from a data holding circuit.
FIG. 4 is a block diagram showing a schematic configuration of a master clock generator of the data holding circuit.
FIG. 5 is a time chart of signals for a master clock generator of a data holding circuit.
FIG. 6 is a circuit diagram of a data transmission circuit of the data recording / transmission apparatus of the embodiment.
FIG. 7 is a first half of a flowchart showing a data transmission process to a data recording circuit in a CPU.
FIG. 8 is the latter half of the flowchart showing the data transmission process to the data recording circuit in the CPU.
FIG. 9 is a flowchart showing a pulse number calculation process for calculating the number of pulses of the variable clock signal from the variable clock signal related information in the CPU.
FIG. 10 is a time chart showing recording and transmission of a variable clock signal.
FIG. 11 is a time chart showing recording and transmission of a variable clock signal and stream data.
FIG. 12 is a time chart showing signals output from the encoder.
FIG. 13 is a time chart expressing a variable clock signal in units of pulses.
FIG. 14 is a time chart showing a state where a variable clock signal is run-length encoded.
FIG. 15 is a time chart illustrating an output signal from an encoder.
FIG. 16 is an explanatory diagram of a recording format of variable clock signal related information.
FIG. 17 is an explanatory diagram of a time table in the terminal.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Data recording transmission apparatus 10 ... Data holding circuit
20 ... Data transmission circuit 50 ... Control unit
51 ... CPU 52 ... ROM
53 ... RAM 61 ... Disk interface
62 ... I / O interface 70 ... Hard disk drive
80 ... Encoder 82 ... Terminal
83 ... Timetable 85 ... Video equipment
90 ... Playback device 91 ... Buffer
92 ... Decoder 93 ... Monitor
94: Transmission path
101 ... T counter 103 ... r counter
104 ... h counter 106 ... address decoder
107: 8-bit counter 109: Shift register
111 ... Master clock generator
112 ... Master clock oscillator
113 ... PLL
102, 150, 108, 110 ... Latch
132: Shift register 133: 8-bit counter
134: Address decoder 135 ... Clock generator
137 ... T counter 139 ... Clock counter
131, 136, 138 ... latch 140 ... clock latch
141, 142 ... 2-input OR

Claims (5)

A variable clock signal set to output pulses corresponding to the number of pulses of the master clock signal corresponding to stream data to be output within the predetermined period in order to achieve the target bit rate for the predetermined period; and A method for performing data recording and transmission based on the variable clock signal and stream data input from an encoder capable of outputting stream data output in synchronization with a variable clock signal,
A quotient calculated by dividing the total number of pulses of the variable clock signal output from the encoder in a predetermined processing period by the number of unit pulses is recorded as variable clock signal related information for each predetermined processing period,
While measuring the predetermined processing period, creating a variable clock signal of the number of pulses calculated by multiplying the recorded variable clock signal related information by the number of unit pulses, and transmitting it every predetermined processing period, Record the stream data output together with the variable clock signal from the encoder,
A data recording and transmitting method, wherein the recorded stream data is transmitted in correspondence with the pulse of the variable clock signal to be transmitted. When the remainder is calculated by dividing the total number of pulses of the variable clock signal in the predetermined processing period by the number of unit pulses, the remainder is added to the number of pulses of the variable clock signal in the next processing period. The data recording and transmitting method according to claim 1. For the variable clock signal output after the last processing period that can be divided when the entire output period from the encoder is divided into the predetermined processing period, the number of pulses of the variable clock signal is directly recorded. The data recording and transmitting method according to claim 1 or 2. 4. The data recording and transmitting method according to claim 1, wherein the predetermined processing period is a period in which a pulse that is an integral multiple of the number of unit pulses is counted based on a clock signal having a constant period. A variable clock signal set to output pulses corresponding to the number of pulses of the master clock signal corresponding to stream data to be output within the predetermined period in order to achieve the target bit rate for each predetermined period; and A data recording and transmitting apparatus for performing data recording and transmission based on the variable clock signal and stream data input from an encoder capable of outputting stream data output in synchronization with a variable clock signal,
Stream data recording means for recording the stream data output from the encoder;
A master clock signal creating means for creating a master clock signal;
Clocking means for clocking a predetermined processing period based on the master clock signal creating means;
Counting means for counting pulses of the variable clock signal output from the encoder, determining that the sum is equal to the number of unit pulses, and counting the number of determinations;
A recording initialization means for recording and initializing the number of times of the judgment counted by the counting means at the end of the time measurement of the predetermined processing period by the time measuring means;
The number of determinations recorded by the recording initialization unit is read, the number of pulses is calculated by multiplying the number of read determinations by the unit pulse number, and the predetermined processing period timed by the time measuring unit A variable clock signal transmitting means for generating and transmitting a variable clock signal having the number of pulses calculated by the pulse number calculating means;
Stream data transmission means for transmitting the stream data recorded by the stream data recording means in correspondence with the pulses of the variable clock signal transmitted by the variable clock signal transmission means;
A data recording / transmission apparatus comprising:

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