JP3644664B2 - Sequential circuit using ferroelectric and semiconductor device using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a sequential circuit, and more particularly to a sequential circuit using a ferroelectric.
[0002]
[Prior art]
Sequential circuits such as latch circuits and flip-flop circuits are known. FIG. 8 shows a flip-flop circuit 2 as an example of a conventional sequential circuit. FIG. 9 is a timing chart showing the operation of the flip-flop circuit 2 shown in FIG. The flip-flop circuit 2 is configured by connecting a latch circuit 4 (master latch circuit) and a latch circuit 6 (slave latch circuit) in series. Note that PA in FIG. 9 represents an output signal of the latch circuit 4, that is, a signal at point PA in FIG.
[0003]
When the clock pulse Cp changes from “H” to “L” (see FIG. 9, (a)), the latch circuit 4 enters the latched state and the latch circuit 6 enters the unlatched state. Therefore, the data corresponding to the data Dn (current data) at the falling edge of the clock pulse Cp (the signal at the point PA is a value obtained by inverting the data Dn) is latched by the latch circuit 4 and output. The data Dn is output to Q.
[0004]
Next, when the clock pulse Cp changes from “L” to “H” (see FIG. 9, (b)), the latch circuit 4 enters the unlatched state and the latch circuit 6 enters the latched state. Therefore, the data Dn is latched by the latch circuit 6, and the data Dn is also output to the output Q.
[0005]
Next, when the clock pulse Cp changes from “H” to “L” (see FIG. 9, (c)), the latch circuit 4 is again in the latch state and the latch circuit 6 is in the unlatched state. Accordingly, the data corresponding to the data Dn + 1 (next data) at the falling edge of the clock pulse Cp (the signal at the PA point is an inverted value of the data Dn) is latched by the latch circuit 4. The data Dn + 1 is output to the output Q.
[0006]
As described above, when the flip-flop circuit 2 is used, data can be latched at the falling timing of the clock pulse Cp, and the latched data can be output for a time corresponding to one cycle of the clock pulse Cp. For this reason, noise can be removed from the data and a stable output can be obtained.
[0007]
Therefore, by using a combination of a sequential circuit such as the flip-flop circuit 2 and a combinational circuit such as a logic gate, highly reliable sequence processing or the like can be performed.
[0008]
[Problems to be solved by the invention]
However, the conventional sequential circuit such as the above-described flip-flop circuit 2 has the following problems. In a conventional sequential circuit, a voltage must always be applied to the circuit in order to retain the data being processed.
[0009]
Therefore, if the power is shut off due to an accident in the middle of the sequence processing, even if the power is restored, the data immediately before the accident does not remain, and in order to return the sequence processing to the state immediately before the accident, the sequence processing must be performed again. I had to start over. This is wasteful and lacks processing reliability.
[0010]
An object of the present invention is to provide a nonvolatile sequential circuit or the like that can solve the problems of sequential circuits such as the conventional flip-flop circuit and can retain data even when the power is cut off.
[0011]
[Means for Solving the Problem, Action and Effect of the Invention]
  This inventionEach of the sequential circuit and the semiconductor device includes a ferroelectric memory unit that is coupled to the output terminal of the gate unit and holds a polarization state corresponding to a signal appearing at the output terminal.
[0012]
Therefore, the ferroelectric memory unit holds a signal appearing at the output terminal of the gate unit constituting the sequential circuit such as a latch circuit in the form of a polarization state corresponding to the signal. For this reason, even if the power supply is cut off, the data is held by the ferroelectric memory unit.
[0013]
As a result, when the power is restored, the state of the sequential circuit can be reliably and promptly restored to the state before the power is shut off using the stored data. That is, a sequential circuit such as a nonvolatile latch circuit can be realized.
[0014]
  This inventionThe sequential circuit includes a normalization circuit that normalizes signals to a predetermined standard value, and is configured to output output data via the normalization circuit.
[0015]
Therefore, even if the signal obtained in the normal operation or the operation at the time of return is deviated from the standard value, it can be standardized and output by providing the standardization circuit. For this reason, subsequent processing can be performed more accurately.
[0016]
  This inventionThis sequential circuit is characterized in that the ferroelectric memory portion is a ferroelectric capacitor.
[0017]
Therefore, by using the ferroelectric capacitor, the signal appearing at the output terminal of the gate portion constituting the sequential circuit can be held as the polarization state of the ferroelectric capacitor. For this reason, a non-volatile sequential circuit can be easily realized. In addition, the number of transistors or the like included in the sequential circuit can be easily reduced.
[0018]
  This inventionIn the sequential circuit, one end of the ferroelectric capacitor is coupled to the output end of the gate portion, and a voltage synchronized with the gate control signal is applied to the other end of the ferroelectric capacitor. .
[0019]
Therefore, in synchronization with the gate control signal, the signal appearing at the output terminal of the gate part constituting the sequential circuit is held in the ferroelectric capacitor, or the information held in the ferroelectric capacitor is reproduced. Can do. For this reason, the signal appearing at the output terminal of the sequential circuit can be easily stored and reproduced in a nonvolatile manner.
[0020]
  This inventionIn the sequential circuit, a gate unit that interrupts input data according to a gate control signal,A normalization circuit that normalizes the data through the gate unit to a predetermined standard value;With a signal corresponding to the input dataThrough the standardization circuitOutput as output data, and when the gate is in a disconnected state, a signal corresponding to the input data immediately before the disconnected state is substantially generatedFrom standardized circuitA sequential circuit configured to output as output data,
  TheIn seriesTwo sequential circuits that provide output data of an input-side sequential circuit as input data of an output-side sequential circuit to a gate portion of an output-side sequential circuit,
At least one sequential circuit of the two coupled sequential circuits is
A ferroelectric capacitor that is coupled to the output terminal of the gate portion and holds a polarization state corresponding to a signal appearing at the output terminal,
The one end of the ferroelectric capacitor is coupled to the output end of the gate unit, and the other end of the ferroelectric capacitor is configured to apply a voltage synchronized with the gate control signal,
The gate control signal for controlling the gate part of the sequential circuit on the input side and the gate control signal for controlling the gate part of the sequential circuit on the output side are in a mutually inverted phase.
  It is characterized by that.
[0021]
Accordingly, a signal appearing at the output terminal of the gate part constituting at least one of the sequential circuits such as the two latch circuits constituting the sequential circuit such as the flip-flop circuit is a polarization state corresponding to the signal. Is held by the ferroelectric memory. For this reason, even if the power supply is cut off, the data is held by the ferroelectric memory unit.
[0022]
As a result, when the power supply is restored, the state of the sequential circuit such as the latch circuit can be reliably and promptly restored to the state before the power supply is shut off using the stored data. It becomes. That is, a sequential circuit such as a nonvolatile flip-flop circuit can be realized.
[0023]
  This inventionThe sequential circuit has a configuration in which two sequential circuits are coupled in series, and the output data of the sequential circuit on the input side is used as the input data of the sequential circuit on the output side. The gate control signal for controlling the gate part of the sequential circuit on the input side and the gate control signal for controlling the gate part of the sequential circuit on the output side have mutually inverted phases. A voltage is applied to the other end of the ferroelectric capacitor of the sequential circuit at the same timing.
[0024]
Accordingly, the ferroelectric memory unit converts the signal appearing at the output terminal of each gate unit constituting the sequential circuit such as the two latch circuits constituting the sequential circuit such as the flip-flop circuit into the polarization state corresponding to the signal. keeping. For this reason, even if the power supply is cut off, the data is held by both the ferroelectric storage units.
[0025]
As a result, even when the power is shut off, it is possible to more reliably return to the state before the power is shut off. Further, even in a normal operation state, the signal can be held more reliably without providing a feedback circuit.
[0026]
  This inventionIn the data storage / reproduction method, a gate unit for switching data according to a gate control signal is provided, and when the gate unit is in a connected state, a signal corresponding to the input data is output as output data, and the gate unit is in a disconnected state. A sequential circuit configured to output, as output data, a signal substantially corresponding to input data immediately before the disconnection state, and includes a ferroelectric storage unit that stores information corresponding to the data Is a method for storing and reproducing data using a sequential circuit, wherein information corresponding to the held data is stored in the ferroelectric memory unit and based on the information stored in the ferroelectric memory unit And reproducing the data.
[0027]
Therefore, the ferroelectric memory unit stores data held in a sequential circuit such as a latch circuit. For this reason, even if the power supply is cut off, the data is held by the ferroelectric memory unit.
[0028]
As a result, when the power supply is restored, the state of the sequential circuit can be reliably and promptly restored to the state before the power supply is shut off using the stored data.
[0029]
  This inventionIn the data storage / reproduction method, a gate unit for switching data according to a gate control signal is provided, and when the gate unit is in a connected state, a signal corresponding to the input data is output as output data, and the gate unit is in a disconnected state. In this case, a sequential circuit having a configuration in which two or more sequential circuits configured to output a signal corresponding to input data immediately before the disconnection state is output as output data is combined, and information corresponding to the data Is a method of storing and reproducing data using a sequential circuit having a ferroelectric memory unit for storing data, and stores information corresponding to the held data in the ferroelectric memory unit and ferroelectric The data is reproduced based on information stored in the body storage unit.
[0030]
Therefore, the ferroelectric memory unit stores data held in a sequential circuit such as a flip-flop circuit. For this reason, even if the power supply is cut off, the data is held by the ferroelectric memory unit.
[0031]
As a result, when the power is restored, the state of the sequential circuit can be reliably and promptly restored to the state before the power is shut off using the stored data.
[0032]
The term “ferroelectric storage section” in the claims refers to a portion that stores information using the hysteresis characteristics of a ferroelectric, and a circuit that combines these in addition to a ferroelectric transistor or a ferroelectric capacitor itself. It is a concept that also includes In the embodiment, the ferroelectric capacitors C1 and C2 shown in FIG. 1 correspond to this.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit diagram showing a flip-flop circuit 42 which is a sequential circuit used in a semiconductor device according to an embodiment of the present invention. The flip-flop circuit 42 is a basic D flip-flop circuit having a configuration in which a latch circuit LT1 (master latch circuit) and a latch circuit LT2 (slave latch circuit), which are sequential circuits, are connected in series.
[0034]
The latch circuit LT1 includes a transistor GT1 (N-channel MOSFET) that is a gate portion, a ferroelectric capacitor C1 that is a ferroelectric memory portion, and an inverter circuit portion INV1 that is a standardization circuit.
[0035]
The inverter circuit unit INV1 is, for example, a CMOS inverter circuit, and includes a configuration (not shown) in which a transistor PT that is a P-channel MOSFET and a transistor NT that is an N-channel MOSFET are connected in series.
[0036]
The ferroelectric capacitor C1 is formed so as to sandwich a ferroelectric layer made of PZT or the like between two electrodes. The ferroelectric capacitor C1 holds a polarization state corresponding to the input data D, as will be described later.
[0037]
One end of the ferroelectric capacitor C1 is connected to the output terminal of the transistor GT1 of the latch circuit LT1 shown in FIG. 1 and to the input terminal of the inverter circuit unit INV1. The other end of the ferroelectric capacitor C1 is connected to the plate line PL. In addition, a parasitic capacitance C3 exists between the wiring extending from the output terminal of the transistor GT1 to the input terminal of the inverter circuit unit INV1 and the ground.
[0038]
As shown in FIG. 1, the latch circuit LT1 does not include a feedback path. However, since the ferroelectric capacitor C1 and the parasitic capacitance C3 described above exist, even if the wiring from the output terminal of the transistor GT1 to the input terminal of the inverter circuit unit INV1 is in a floating state (that is, the transistor GT1 is turned off). The potential of the wiring is maintained for a while. Therefore, as long as the period of the clock pulse Cp is not so long, the latch contents of the latch circuit LT1 are held even if no feedback path is provided.
[0039]
The input data D input via the transistor GT1 is inverted by the inverter circuit unit INV1, and then input to the latch circuit LT2. The latch circuit LT2 has a configuration similar to that of the latch circuit LT1, and includes a transistor GT2, which is a gate portion, a ferroelectric capacitor C2, an inverter circuit portion INV2, and a parasitic capacitance C4. The transistor GT2 has the same configuration as the transistor GT1, and the inverter circuit unit INV2 has the same configuration as the inverter circuit unit INV1.
[0040]
The operation of the latch circuit LT2 is the same as that of the latch circuit LT1. That is, the output of the inverter circuit unit INV1 input through the transistor GT2 is inverted by the inverter circuit unit INV2, and then becomes the output Q of the flip-flop circuit 42.
[0041]
A clock pulse Cp that is a gate control signal is applied to the gate of the transistor GT2 of the latch circuit LT2, and a clock pulse CpB (control signal) that is an inverted signal of the clock pulse Cp is applied to the gate of the transistor GT1 of the latch circuit LT1. Given. As shown in FIG. 2, a signal synchronized with the clock pulse Cp is applied to the plate line PL.
[0042]
The operation of the flip-flop circuit 42 is similar to the operation of the conventional flip-flop circuit 2 shown in FIG. 8 (see FIG. 9). However, as will be described later, the data is retained even when the power is turned off. Thus, the conventional flip-flop circuit 2 is different. In this embodiment, unlike the flip-flop circuit 2, the input data D is latched at the rising timing of the clock pulse Cp.
[0043]
The operation of the flip-flop circuit 42 will be described using the timing chart shown in FIG.
[0044]
When the clock pulse Cp changes from “L” to “H” (see FIG. 2, (a)), the transistor GT1 of the latch circuit LT1 is turned OFF (disconnected state), and the transistor GT2 of the latch circuit LT2 is turned ON (connected state). )become. Therefore, data corresponding to the data Dn (current data) at the rising edge of the clock pulse Cp is latched in the latch circuit LT1, and the data Dn is output to the output Q.
[0045]
Next, when the clock pulse Cp changes from “H” to “L” (see FIG. 2, (b)), the transistor GT1 of the latch circuit LT1 is turned on (connected state), and the transistor GT2 of the latch circuit LT2 is turned off. (Disconnected state). Therefore, the data Dn is latched by the latch circuit LT2, and the data Dn is also output to the output Q.
[0046]
Next, when the clock pulse Cp changes from “L” to “H” (see FIG. 2, (c)), the transistor GT1 of the latch circuit LT1 is turned off again (disconnected state) and the transistor GT2 of the latch circuit LT2 is turned on again. Is turned on (joining state). Therefore, the data corresponding to the data Dn + 1 (next data) at the rising edge of the clock pulse Cp is latched by the latch circuit LT1, and the data Dn + 1 is output to the output Q.
[0047]
As described above, when the flip-flop circuit 42 is used, data can be latched at the rising timing of the clock pulse Cp, and the latched data can be output for a time corresponding to one cycle of the clock pulse Cp.
[0048]
As described above, unlike the conventional flip-flop circuit 2, the flip-flop circuit 42 retains data even when the power is turned off. Data holding and reproduction operations will be described. Note that the PA point in FIG. 1 represents one end of the ferroelectric capacitor C1, and the PB point represents one end of the ferroelectric capacitor C2.
[0049]
FIG. 3 shows a circuit diagram in the vicinity of the ferroelectric capacitor C1 and the parasitic capacitor C3 constituting the latch circuit LT1. FIG. 4 shows the voltage related to the ferroelectric capacitor C1 (the potential at the point PA when the plate line PL shown in FIG. 3 is the reference potential) and the polarization state (in the figure, “charge” equivalent to the “polarization state”). The hysteresis curve (voltage / charge characteristics) representing the relationship with
[0050]
In FIG. 4, a state in which the remanent polarization Z1 is generated is a polarization state P1, and a state in which the remanent polarization Z2 is generated is a polarization state P2.
[0051]
As described above, at the rising edge of the clock pulse Cp, that is, the data Dn immediately before the clock pulse Cp changes from “L” to “H” (see FIG. 2A) (in this embodiment, the data “H”). ) Is latched by the latch circuit LT1. FIG. 3 shows the state of signals in the vicinity of the ferroelectric capacitor C1 and the parasitic capacitance C3 immediately before FIG.
[0052]
At this time, as shown in FIG. 3, one end (point PA) of the ferroelectric capacitor C1 is given an “H” potential by data “H”, and the other end (plate line) of the ferroelectric capacitor C1. “L” potential is applied to PL).
[0053]
As a result, the ferroelectric capacitor C1 is charged together with the parasitic capacitance C3. At this time, the ferroelectric capacitor C1 exhibits a polarization state P3 shown in FIG.
[0054]
Thereafter, when the clock pulse Cp rises (see FIG. 2, (a)) and becomes “H”, the transistor GT1 is turned off. However, due to the charged parasitic capacitance C3 and the charge of the ferroelectric capacitor C1, The potential of does not change so much. That is, as described above, data “H” is latched in the latch circuit LT1 for a while.
[0055]
Thereafter, when the clock pulse Cp falls (see FIG. 2, (b)) and becomes “L”, the transistor GT1 is turned on, and again returns to the state shown in FIG. 3, and the parasitic capacitance C3 and the ferroelectric capacitor C1. Will be charged. During this time, although the polarization state of the ferroelectric capacitor C1 slightly fluctuates, the polarization state P3 shown in FIG. 4 is maintained.
[0056]
In this state, when the plate line PL next becomes “H” (see FIG. 2, (d)), the polarization state of the ferroelectric capacitor C1 becomes the polarization state P1 shown in FIG. As described above, when the input data D is “H”, the polarization state of the ferroelectric capacitor C1 goes back and forth between the polarization state P3 and the polarization state P1 shown in FIG. That is, the polarization state P3 to the polarization state P1 of the ferroelectric capacitor C1 correspond to the data “H”.
[0057]
Thereafter, when the input data D becomes “L” (see FIG. 2, (e)), the potential at the PA point also becomes “L” (see FIG. 2, (h)). When the potential at the PA point becomes “L”, if the plate line PL is “H”, the parasitic capacitance C3 is forcibly discharged, and the ferroelectric capacitor C1 has the “L” point on the PA point side. The plate line PL side is set to “H” (a state opposite to the state shown in FIG. 3) and charged (see FIG. 2, (f)). Therefore, the polarization state of the ferroelectric capacitor C1 becomes a polarization state P4 shown in FIG.
[0058]
In this state, when the plate line PL becomes “L” next (see FIG. 2, (g)), the polarization state of the ferroelectric capacitor C1 becomes the polarization state P2 shown in FIG. As described above, when the input data D is “L”, the polarization state of the ferroelectric capacitor C1 goes back and forth between the polarization state P4 and the polarization state P2 shown in FIG. That is, the polarization state P4 or the polarization state P2 of the ferroelectric capacitor C1 corresponds to the data “L”.
[0059]
When the potential at the PA point becomes “L” (see FIG. 2, (h)) and the plate line PL is already “L”, the ferroelectric capacitor C1 is forcibly discharged. Thus, the polarization state P1 shown in FIG. 4 is obtained. Therefore, in this case, the ferroelectric capacitor C1 is still in the polarization state corresponding to the data “H”. In such a case, the ferroelectric capacitor C1 is in the polarization state corresponding to the data “L” when the transistor GT1 is next turned ON and the plate line PL is set to “H” (FIG. 2, (See (i)).
[0060]
As described above, the polarization state of the ferroelectric capacitor C1 changes according to the potential at the PA point that changes substantially corresponding to the input data D, although there is some variation depending on the timing at which the input data D changes.
[0061]
Similarly, although the polarization state of the ferroelectric capacitor C2 constituting the latch circuit LT2 varies slightly depending on the timing at which the input data D changes, it almost follows the potential at the PB point obtained by inverting the potential at the PA point. ,Change. Therefore, the ferroelectric capacitor C2 is in a polarization state almost opposite to that of the ferroelectric capacitor C1.
[0062]
Next, it is assumed that the power supply is cut off in the polarization state corresponding to the data “L” in the ferroelectric capacitor C1 (see FIG. 2, (j)). After a while since the power supply is cut off, the polarization state of the ferroelectric capacitor C1 becomes the polarization state P2 shown in FIG. The parasitic capacitance C3 is in a discharged state.
[0063]
By turning on the power, the clock pulse Cp is set to “H” and the plate line PL is set to “H”. With this configuration, the polarization state of the ferroelectric capacitor C1 becomes the polarization state P5 shown in FIG. 4 when the power is turned on (see FIG. 2, (k)). That is, in this case, according to the graphical solution, the potential at the PA point with respect to the ground is V2-Vp shown in FIG. 4 (see FIG. 2, (l)). Since the potential at the point PA (V2-Vp) is smaller than the reference value Vref-Vp, the logic level is "L".
[0064]
At this time, since the transistor GT2 of the latch circuit LT2 is ON, the potential at the point PB becomes "H" level by the action of the inverter circuit section INV1 of the latch circuit LT1 (see FIG. 2, (m)).
[0065]
When the potential at the point PB becomes “H”, the output Q becomes “L” by the action of the inverter circuit section INV2 of the latch circuit LT2 (see FIG. 2, (n)).
[0066]
In this way, the data “L” held in the flip-flop 42 immediately before the power is turned off is reproduced when the power is restored. 4 represents the “H” potential of the plate line PL, and L1 represents the capacitance of the parasitic capacitance C3.
[0067]
On the other hand, if the ferroelectric capacitor C1 is turned off in the polarization state corresponding to the data “H”, the polarization state of the ferroelectric capacitor C1 is changed to the polarization state shown in FIG. 4 after a while after the power supply is turned off. It becomes P1. The parasitic capacitance C3 is in a discharged state.
[0068]
Here, when the power is turned on (see FIG. 2, (k)), the polarization state of the ferroelectric capacitor C1 becomes the polarization state P6 shown in FIG. That is, the potential at the PA point with respect to the ground is V1-Vp (see FIG. 2, (l ')) shown in FIG. Since the potential at the point PA (V1-Vp) is larger than the reference value Vref-Vp, the logic level is "H".
[0069]
At this time, since the transistor GT2 of the latch circuit LT2 is ON, the potential at the point PB becomes "L" level by the action of the inverter circuit section INV1 of the latch circuit LT1 (see FIG. 2, (m ')). .
[0070]
When the potential at the point PB becomes “L”, the output Q becomes “H” by the action of the inverter circuit section INV2 of the latch circuit LT2 (see FIG. 2, (n ′)).
[0071]
In this way, the data “H” held in the flip-flop 42 immediately before the power is turned off is reproduced when the power is restored.
[0072]
After that, when the transistor GT1 is turned on when the clock pulse Cp becomes “L” (see FIG. 2, (o)), the potential at the PA point is changed to new input data D (here, “L”). Therefore, it becomes “L”. However, since the transistor GT2 is OFF, the potential at the point PB remains “L”. Therefore, the output Q remains “H”. The output Q becomes “L” in accordance with the new input data “L”, as described above, at the rise of the next clock pulse Cp (see FIG. 2, (p)).
[0073]
Thus, according to the polarization state of the ferroelectric capacitor C1 corresponding to the data held in the flip-flop 42 immediately before the power supply is cut off, the data is reproduced when the power supply is restored. As described above, when the data is reproduced according to the polarization state of the ferroelectric capacitor C1, the ferroelectric capacitor C2 constituting the latch circuit LT2 can be omitted.
[0074]
In the above-described embodiment, the data held in the flip-flop 42 immediately before power-off is reproduced according to the polarization state held by the ferroelectric capacitor C1 constituting the latch circuit LT1. The invention is not limited to this.
[0075]
For example, according to the polarization state held by the ferroelectric capacitor C2 constituting the latch circuit LT2, the data held by the flip-flop 42 immediately before the power supply can be reproduced. In this case, it is preferable to set the clock pulse Cp to “L” and the plate line PL to “H” by turning on the power. When the data is reproduced according to the polarization state of the ferroelectric capacitor C2, the ferroelectric capacitor C1 constituting the latch circuit LT1 can be omitted.
[0076]
However, as shown in FIG. 1, if both the ferroelectric capacitors C1 and C2 are provided, it is not necessary to limit the state of the clock pulse Cp when the power is turned on, which is convenient.
[0077]
Thus, the flip-flop circuit 42 includes the ferroelectric capacitors C1 and C2 that are connected to the output terminals of the transistors GT1 and GT2 and hold the polarization state corresponding to the signal appearing at the output terminals.
[0078]
Therefore, the ferroelectric capacitors C1 and C2 hold the signals appearing at the output terminals of the transistors GT1 and GT2 constituting the flip-flop circuit 42 in a polarization state corresponding to the signals. For this reason, even if the power supply is cut off, the data is held by the ferroelectric capacitors C1 and C2.
[0079]
As a result, when the power is restored, the state of the flip-flop circuit 42 can be reliably and promptly restored to the state before the power is shut off using the stored data. . That is, a nonvolatile flip-flop circuit can be realized.
[0080]
In addition, since the time required for the polarization inversion of the ferroelectric is short, the time until the ferroelectric capacitors C1 and C2 reach the polarization state corresponding to the input data D is short when writing data. Therefore, high-speed response is possible.
[0081]
Further, in the case of a ferroelectric material, a high voltage is not required when data is written or erased. Therefore, there is no need to provide a booster circuit in the chip or to separately prepare a high-voltage power supply in addition to the normal power supply. For this reason, an increase in chip size and an increase in manufacturing cost can be suppressed.
[0082]
In this embodiment, inverter circuits INV1 and INV2 are provided as standardization circuits for normalizing signals to predetermined standard values, and data is output via the inverter circuit sections INV1 and INV2. .
[0083]
Therefore, even if the signal obtained in the normal operation or the operation at the time of return is deviated from the standard value, it can be standardized and output by providing the inverter circuit portions INV1 and INV2. For this reason, subsequent processing can be performed more accurately.
[0084]
In this embodiment, the ferroelectric memory unit is made of ferroelectric capacitors C1 and C2. Therefore, the signal appearing at the output terminals of the transistors GT1 and GT2 constituting the flip-flop circuit 42 can be held as the polarization state of the ferroelectric capacitors C1 and C2. For this reason, a nonvolatile flip-flop circuit can be easily realized. In addition, the number of transistors and the like constituting the flip-flop circuit can be easily reduced.
[0085]
In this embodiment, one end (PA point, PB point) of the ferroelectric capacitors C1, C2 is coupled to the output ends of the transistors GT1, GT2, and the other end of the ferroelectric capacitors C1, C2 is connected to the clock. A voltage synchronized with the pulse Cp is applied.
[0086]
Therefore, in synchronization with the clock pulse Cp, signals appearing at the output terminals of the transistors GT1 and GT2 constituting the flip-flop circuit 42 are held in the ferroelectric capacitors C1 and C2, or are stored in the ferroelectric capacitors C1 and C2. The stored information can be reproduced. Therefore, the data latched in the flip-flop circuit can be easily stored and reproduced in a nonvolatile manner.
[0087]
In the above-described embodiment, the transistors GT1 and GT2 are used as the gate portion, but the gate portion is not limited to this. As the gate portion, for example, a transmission gate, a clocked CMOS inverter, or the like can be used.
[0088]
Note that the above-described variations can be similarly applied to various other embodiments described below.
[0089]
In each of the above-described embodiments, the basic D flip-flop circuit has been described as an example, but the present invention is not limited to this. For example, the present invention can be applied to flip-flop circuits in general, such as a D flip-flop circuit with S-R (set / reset) and a JK flip-flop circuit.
[0090]
FIG. 5 shows a circuit diagram of a flip-flop circuit 44 which is an example of a D flip-flop circuit with SR (set / reset) to which the present invention is applied. FIG. 6 is a table showing the operation of the flip-flop circuit 44.
[0091]
Similarly to the flip-flop circuit 42 shown in FIG. 1, the flip-flop circuit 44 has a configuration in which a latch circuit LT1 (master latch circuit) and a latch circuit LT2 (slave latch circuit), which are sequential circuits, are connected in series.
[0092]
The output terminal of the latch circuit LT1 is not connected to the inverter circuit unit INV1 (see FIG. 1) but is connected to a logic gate unit LG1 that is a combination of a plurality of logic gates. A signal from the point PA, a signal from the reset terminal R, and a signal from the set terminal S are input to the logic gate part LG1. The output of the logic gate part LG1 becomes the output of the latch circuit LT1.
[0093]
As shown in FIG. 6, by inputting a signal “H” to the reset terminal R, the stored contents of the flip-flop circuit 44 can be reset (cleared), and a signal “L” is input to the reset terminal R. By inputting the signal “H” to the set terminal S, the stored contents of the flip-flop circuit 44 can be set (preset).
[0094]
If the signal “L” is given to the reset terminal R and the set terminal S, the same function as the above-described flip-flop circuit 42 (see FIG. 1) is obtained.
[0095]
The latch circuit LT2 has the same configuration as the latch circuit LT1 and includes a logic gate part LG2. The logic gate part LG2 has the same configuration as the logic gate part LG1.
[0096]
As described above, the flip-flop circuit 44 includes the set terminal S and the reset terminal R, and includes the logic gate unit LG1 and the logic gate unit LG2 instead of the inverter circuit units INV1 and INV2. For example, the configuration is the same as that of the flip-flop circuit 42 shown in FIG.
[0097]
FIG. 7A shows a circuit diagram of a flip-flop circuit 46 which is an example of a JK flip-flop circuit to which the present invention is applied. FIG. 7B is a table showing the operation of the flip-flop circuit 46.
[0098]
The flip-flop circuit 46 includes the flip-flop circuit 42 shown in FIG. 1 and a logic gate unit LG that combines a plurality of logic gates. The logic gate unit LG is supplied with an input from the input terminal J, an input from the input terminal K, and an output Q from the flip-flop circuit 42 as inputs. The output of the logic gate part LG is given to the input terminal D of the flip-flop circuit 42.
[0099]
As shown in FIG. 7B, when a signal “H” is applied to the input terminal J and a signal “L” is applied to the input terminal K, data “H” is output from the output Q at the rising edge of the clock pulse Cp. Conversely, if a signal “L” is applied to the input terminal J and a signal “H” is applied to the input terminal K, data “L” is output from the output Q at the rising edge of the clock pulse Cp.
[0100]
If the signal “H” is applied to both the input terminal J and the input terminal K, the contents of the output Q are inverted at the rising edge of the clock pulse Cp. On the other hand, if the signal “L” is applied to both the input terminal J and the input terminal K, the contents of the output Q are retained.
[0101]
In each of the above-described embodiments, the flip-flop circuit has been described as an example of the sequential circuit. However, the present invention is not limited to this. The present invention can also be applied to a latch circuit as a sequential circuit, for example.
[0102]
As the latch circuit, for example, there is a latch circuit LT1, which is a component of the flip-flop circuit 42 shown in FIG. Like the above-described flip-flop circuits, the latch circuit LT1 and the like can retain data even when the power is turned off. When the power is restored, the latch circuit LT1 is restored to the state immediately before the power is turned off.
[0103]
In this embodiment, a ferroelectric capacitor is used as the ferroelectric memory unit. However, the ferroelectric memory unit is not limited to the ferroelectric capacitor. As the ferroelectric memory unit, for example, a ferroelectric transistor can be used.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a flip-flop circuit 42 which is a sequential circuit used in a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of the flip-flop circuit 42;
FIG. 3 is a circuit diagram in the vicinity of a ferroelectric capacitor C1 and a parasitic capacitor C3 constituting the latch circuit LT1.
FIG. 4 is a diagram showing a hysteresis curve representing a relationship between a voltage and a polarization state related to a ferroelectric capacitor C1.
FIG. 5 is a circuit diagram showing a flip-flop circuit 44 which is a sequential circuit used in a semiconductor device according to another embodiment of the present invention.
6 is a table showing the operation of the flip-flop circuit 44. FIG.
FIG. 7A is a circuit diagram of a flip-flop circuit 46 which is an example of a JK flip-flop circuit to which the present invention is applied. FIG. 7B is a table showing the operation of the flip-flop circuit 46.
FIG. 8 is a circuit diagram of a flip-flop circuit 2 which is an example of a conventional sequential circuit.
9 is a timing chart representing the operation of flip-flop circuit 2 shown in FIG.
[Explanation of symbols]
42... Flip-flop circuit
C1 ... Ferroelectric capacitor
D ... Input data
GT1... Transistor
LT1... Latch circuit
Q ・ ・ ・ ・ ・ ・ Output

Claims (7)

Equipped with a gate part that relays input data according to the gate control signal, and a normalization circuit that normalizes the data through the gate part to a predetermined standard value, and supports input data when the gate part is in the relay state The output signal is output as output data through the standardization circuit, and when the gate portion is in the disconnected state, the signal corresponding to the input data immediately before the disconnection state is substantially output from the standardization circuit as the output data. A sequential circuit configured as follows,
A ferroelectric capacitor that is coupled to the output terminal of the gate portion and holds a polarization state corresponding to a signal appearing at the output terminal,
The one end of the ferroelectric capacitor is coupled to the output end of the gate unit, and the other end of the ferroelectric capacitor is configured to apply a voltage synchronized with the gate control signal.
A sequential circuit using a ferroelectric material. The sequential circuit using the ferroelectric according to claim 1,
Constructed to raise the voltage from the other end of the ferroelectric capacitor synchronized with the gate control signal when the sequential circuit is powered on,
A sequential circuit using a ferroelectric material. Equipped with a gate part that relays input data according to the gate control signal, and a normalization circuit that normalizes the data through the gate part to a predetermined standard value, and supports input data when the gate part is in the relay state The output signal is output as output data through the standardization circuit, and when the gate portion is in the disconnected state, the signal corresponding to the input data immediately before the disconnection state is substantially output from the standardization circuit as the output data. Sequential circuit, configured as
Are connected in series, and the output data of the sequential circuit on the input side is given to the gate portion of the sequential circuit on the output side as input data of the sequential circuit on the output side,
At least one sequential circuit of the two coupled sequential circuits is
A ferroelectric capacitor that is coupled to the output terminal of the gate portion and holds a polarization state corresponding to a signal appearing at the output terminal,
The one end of the ferroelectric capacitor is coupled to the output end of the gate unit, and the other end of the ferroelectric capacitor is configured to apply a voltage synchronized with the gate control signal,
The gate control signal for controlling the gate part of the sequential circuit on the input side and the gate control signal for controlling the gate part of the sequential circuit on the output side are in a mutually inverted phase.
A sequential circuit using a ferroelectric material. A sequential circuit using the ferroelectric according to claim 3,
The other end of the ferroelectric capacitor of the sequential circuit on the input side and the output side is configured to apply the voltage at the same timing,
A sequential circuit using a ferroelectric material. Use of the circuit according to any one of claims 1 to 4.
A semiconductor device characterized by the above. Equipped with a gate part that relays input data according to the gate control signal, and a normalization circuit that normalizes the data through the gate part to a predetermined standard value, and supports input data when the gate part is in the relay state The output signal is output as output data through the standardization circuit, and when the gate portion is in the disconnected state, the signal corresponding to the input data immediately before the disconnection state is substantially output from the standardization circuit as the output data. A method of storing and reproducing data using a sequential circuit configured as described above, wherein the sequential circuit includes a ferroelectric capacitor that couples one end storing information corresponding to data to the output end of the gate unit. There,
A voltage synchronized with the gate control signal is applied to the other end of the ferroelectric capacitor,
Storing information corresponding to the held data in a ferroelectric capacitor and reproducing the data based on the information stored in the ferroelectric capacitor ;
A data storage and reproduction method characterized by the above. Equipped with a gate part that relays input data according to the gate control signal, and a normalization circuit that normalizes the data through the gate part to a predetermined standard value, and supports input data when the gate part is in the relay state The output signal is output as output data through the standardization circuit, and when the gate portion is in the disconnected state, the signal corresponding to the input data immediately before the disconnection state is substantially output from the standardization circuit as the output data. A sequential circuit having a configuration in which two or more sequential circuits configured in such a manner are coupled in series, and includes a ferroelectric capacitor that couples one end storing information corresponding to data to the output end of the gate unit , A method for storing and reproducing data using
A gate control signal for controlling the gate part of the sequential circuit on the input side and a gate control signal for controlling the gate part of the sequential circuit on the output side are given as mutually inverted phases,
A voltage synchronized with the gate control signal is applied to the other end of the ferroelectric capacitor,
Storing information corresponding to the held data in a ferroelectric capacitor and reproducing the data based on the information stored in the ferroelectric capacitor ;
A data storage and reproduction method characterized by the above.

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