JP3644399B2 - PCI bus defective part isolation method and program thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for isolating a defective part of a PCI bus conforming to the PCI bus specification. In particular, the present invention logically separates a defective device / function on the PCI bus without adding H / W on the PCI bus. The system is started and the continuous operability of the system is improved.
[0002]
[Prior art]
FIG. 12 is a block diagram showing a PCI bus processing apparatus disclosed in, for example, Japanese Patent Application Laid-Open No. 11-191073. In the figure, 20 is a PCI bus processing device, 21 is a transaction start detection circuit for detecting the start of a transaction on the PCI bus, and inputs FRAME # of the PCI bus signal. 22 is a holding register for holding information on the address / data line and command / byte enable line on the PCI bus, 23 is an abnormality detection circuit for detecting an abnormality on the PCI bus, and 24 indicates whether or not it is valid. A storage register 25 that has a valid bit and stores an address and command information when an abnormality occurs. A PCI bus interface 25 inputs all PCI bus signals.
[0003]
Next, the operation will be described.
(1) When the bus master on the PCI bus starts a transaction on the PCI bus, the transaction start detection circuit in the PCI bus processing device 20 detects the start of the transaction and notifies the holding register 22. Stores command information.
(2) Next, the abnormality detection circuit 23 monitors a transaction on the PCI bus. When an abnormality is detected, the contents of the holding register 22 are stored in the storage register 24 and at the same time the validbit is validated.
[0004]
(3) Then, the host CPU (not shown) having received the abnormality report on the PCI bus reads the storage register 24 in the PCI bus processing device 20 via the PCI bus.
(4) The PCI bus interface 25 in the PCI bus processing device 20 receives a PCI read transaction from the host CPU, and returns the value of the storage register 24 to the host CPU only when the validbit is valid.
On the other hand, when validbit is invalid, “FFFFFFFFh” is returned.
[0005]
Therefore, since the address and command information at the time of occurrence of an abnormality are output on the PCI bus via the PCI bus interface, the host CPU identifies the abnormal PCI function and abnormal PCI device by the abnormality occurrence address when an abnormality occurs, Isolate the location where the error occurred.
[0006]
[Problems to be solved by the invention]
Since the abnormal part is identified by the conventional PCI bus processing apparatus as described above, it is necessary to add a special H / W circuit for analyzing a PCI transaction.
[0007]
In addition, since a circuit is connected on the PCI bus, there is a problem that an electric load is generated on the PCI bus and one expansion slot of the PCI bus is occupied.
[0008]
In addition, when a PCI configuration cycle is executed for a PCI device / function that is abnormal from the beginning, the PCI device / function will retry indefinitely indicating that the initialization has not been completed. Since this transaction is normal, it cannot be detected by a conventional PCI bus processing device, and the host CPU cannot identify an abnormal part.
[0009]
[Means for Solving the Problems]
(1) A PCI bus defective portion isolation method according to the first aspect of the present invention is a host CPU.cardAnd a PCI device with a built-in PCI function connected to the system via the PCI bus, if there is an abnormality when the PCI function or PCI device is configured, the PCI function or PCI device to be abnormally In a method for isolating a defective PCI bus from a system, a first step of sequentially performing configuration for each PCI function or each PCI device at the time of starting the system, and an abnormality during the configurationButIf there,The host CPU card andA second step of resetting all PCI functions or PCI devices and a step of performing configuration sequentially for each remaining PCI function or PCI device by disconnecting the PCI function or PCI device that has failed after the resetting. 3 steps andIf the abnormality is not resolved even after executing the configuration in the third step, the second step is performed so as to return to the second step and reset the host CPU card and all PCI functions or PCI devices. And the fifth step in which the third step is repeated a predetermined number of times or until the abnormality is resolved is performed on the host CPU card, so that a plurality of abnormal PCI functions or PCI devices can be separated from the system.Is.
[0010]
(2) The PCI bus fault location isolation method according to the invention of claim 2 is the PCI bus fault location isolation method according to claim 1, after resetting in the second step, returning to the first step, The first step and the second step are repeated at least once so as to configure the PCI function or PCI device, and if the abnormality is not resolved, the fourth step proceeds to the third step.IncludingIt is a thing.
[0011]
(3) The PCI bus fault location isolation method according to the invention of claim 3 is the PCI bus fault location isolation method according to claim 1 or 2, wherein the abnormality is not resolved even if the third step is executed. Alternatively, if the abnormality is not resolved after a desired time after the third step is executed, or if any one of the first to third steps cannot be executed, the sixth determination is made that the host CPU card is abnormal. Including the stepsIs.
[0012]
(4) The program for executing the PCI bus defective part isolation method according to the invention described in claim 4 is a program for executing the PCI bus defective part isolation method according to any one of claims 1 to 3. Is.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
  An embodiment of the present invention will be described below.
Embodiment 1 FIG.
  FIG. 1 is a configuration diagram of a system having a PCI bus. Reference numeral 10 denotes a PCI bus to which a host CPU card 11 and add-in cards 12, 13, and 14 are connected. The host CPU card 11 incorporates a host CPU 11a and various computer functions such as a memory and an interface (not shown) to form a host CPU function. In addition, various necessary S / Ws 11b are also built in, and software of the PCI bus fault location isolation method of the present invention is also built in. The add-in cards 12, 13, and 14 are provided with PCI devices 12a, 13a, and 14a made of, for example, LSI, and PCI functions 12b, 12c, 13b, 14b, and 14c having various functions are included in these PCI devices. Built in.
[0014]
  FIG. 2 is a block diagram for realizing the PCI bus fault location isolation method according to the first embodiment of the present invention. In FIG. 2, 1 operates on a host CPU card connected to the PCI bus and executes a PCI configuration cycle. PCI configuration cycle execution unit to perform, 2 is an access address storage area for storing an access address (combination of PCI bus number / device number / function number) for executing a PCI configuration cycle from now on, and 3 is a logical for all functions It is a function management table (refer FIG. 6) which manages the cutting | disconnection condition.
[0015]
  4Is a WDT circuit that monitors the normal operation of the CPU on the host CPU card and the software operating on it, and 5 is the software when the CPU on the host CPU card and the software operating on the CPU are operating normally. This is a WDT clear register that is periodically written. By writing, the WDT counter value is cleared before the WDT counts up. If the operation of the CPU on the add-in card or the software operating on the add-in card is abnormal, it appears as an abnormality of the CPU on the host CPU card and the software operating on the CPU, and as a result, writing to the WDT clear register 5 is performed. Stop. Therefore, the add-in card side is also monitored by the WDT circuit 4.
[0016]
6 is a reset generation circuit that is activated when the WDT circuit 4 counts up and issues a wake up reset to the system, and 7 is a reset indicating whether the reset is released by power-on or the wake-up reset is released. It is a factor register and can be read from the PCI configuration cycle execution unit 1.
The contents are stored in the memory of the access address storage area 2 and the function management table 3, and the contents are retained even after a wake-up reset.
[0017]
Next, the operation of the WDT circuit 4 will be described.
3 and 4 are diagrams showing an example of the movement of the counter value of the WDT circuit 4.
(1) First, in FIG. 3A, the WDT circuit 4 starts counting at power-on reset release (time: T1).
(2) The host CPU and the software operating on the host CPU are operating normally, and the WDT counter is cleared by writing to the WDT clear register 5 by the software before the WDT count up. During this time, configuration is complete and the system is up.
[0018]
(3) As shown in FIG. 3 (b), if there is an abnormality in a PCI function and the PCI configuration processing for that PCI function is stopped at time T2, writing to the WDT clear register 5 by software Stops, and after the period P1, the WDT counter value is counted up. Since this is the first WDT count up, the reset generation circuit 6 requests the reset generation circuit 6 to execute the wakeup reset, and the reset generation circuit 6 performs the wakeup reset. (Time: T3).
(4) The WDT circuit 4 starts counting again after canceling the wakeup reset, but this time the configuration is completed before the WDT count-up by passing the configuration to the abnormal PCI function, and the WDT clear register 5 is set by software. Since the system is cleared, the system will start up normally.
[0019]
(5) If an abnormality occurs in the PCI function and the abnormality has not been recovered, writing to the WDT clear register 5 by the software remains stopped as shown in FIG. 4A, so the period P2 (= P1) Later, the WDT counter value is counted up again, and since this is the second consecutive WDT count up, it is determined that the function of the host CPU or the PCI bus itself, which is a common unit, is stopped, and an alarm signal is sent, for example. An abnormality determination process is performed (time T5).
(6) As shown in FIG. 4B, if the software writes to the WDT clear register 5 even once during the period P2, the next WDT count-up is regarded as the first time and the wake-up reset is performed. It becomes. (Since the WDT clear process is entered during the period P2, it is not the second consecutive time.)
[0020]
Next, the entire processing flow will be described.
FIG. 5 is a flowchart showing an example in which the PCI configuration cycle execution unit 1 configures each function on the PCI bus. First, the case where all PCI buses / devices / functions are normal and the reset factor is power ON will be described.
[0021]
(1) The PCI configuration cycle execution unit 1 reads the contents of the reset factor register 7 (step ST1-1),
(2) Check the cause of reset this time (step ST1-2),
(3) Since the reset factor is other than wake-up reset by WDT count-up, all function statuses in the function management table 3 are initialized to “0: normal” (step ST1-3),
(4) Move to configuration repetition processing for all PCI buses / devices / functions (step ST1-4),
(5) Check the target function status to be configured during the current iterative process (step ST1-5),
[0022]
(6) Since there is no abnormality, the access address to be configured this time is stored in the access address storage area 2 (step ST1-6).
(7) PCI configuration execution of target function (step ST1-7),
(8) After completion, the access address storage area 2 is cleared (step ST1-8), and all PCI buses / devices / functions are repeatedly executed from step ST1-4 (step ST1-9) to complete all PCI configurations.
(9) Write to the WDT clear register 5 before counting up the WDT (step ST1-10). (The counter value is determined so that the WDT does not count up even at the normal end.)
[0023]
Next, the flow from the power-on reset in the state where an abnormality has occurred with PCI bus number = 0 / device number = 1 / function number = 1 will be described.
(1) Steps ST1-1 to ST1-6 are exactly the same as described above.
(2) When PCI configuration is performed for PCI bus number = 0 / device number = 1 / function number = 1 (step ST1-7),
[0024]
(3) There are cases where the PCI configuration cycle repeats retry processing indefinitely and does not end. (In the case of a PCI target card (add-in card) in which a general-purpose PCI chip set and a CPU are mounted and this general-purpose PCI chip is initialized by an S / W operating on the CPU, the S / W does not operate normally. If a malfunction occurs, the initialization of the PCI chip will not be completed, and in this case, the retry process may be repeated infinitely for the PCI configuration cycle from the host CPU card.) As a result, before the WDT count up Since no data can be written to the WDT clear register 5, a wake-up reset occurs.
[0025]
Next, the flow after the occurrence of the wake-up reset will be described.
(1) The PCI configuration cycle execution unit 1 reads the contents of the reset factor register (step ST1-1),
(2) Check the cause of reset this time (step ST1-2),
(3) Since the reset factor is a wake-up reset by WDT count-up, the contents of the access address storage area 2 are read (step ST1-11),
(4) Check the stored contents (step ST1-12),
(5) Since the access address where the abnormality has occurred is stored, the access address storage area 2 is cleared (step ST1-13),
[0026]
(6) Based on PCI bus number = 0 / device number = 1 / function number = 1, which is information accessed before the occurrence of wakeup reset, the corresponding function status in the function management table 3 is set to “1: Abnormal”. "(Step ST1-14)
(7) Move to configuration repetition processing for all PCI buses / devices / functions (step ST1-4),
(8) Check the target function status to be configured during the current iterative process (step ST1-5),
[0027]
(9) Since the function status of PCI bus number = 0 / device number = 1 / function number = 1 is set to “1: abnormal”, PCI bus number = 0 / device number = 1 / function number = 1 The PCI configuration processing is omitted, and the remaining PCI buses / devices / functions are repeatedly executed from step ST1-4 (step ST1-9) to complete the entire PCI configuration.
(10) Write to the WDT clear register 5 before counting up the WDT (step ST1-10).
[0028]
(11) If the same abnormality occurs in other functions during the PCI configuration of all remaining PCI buses / devices / functions, it stops at the PCI configuration process, and after the second consecutive WDT count up, the host CPU It is determined that the function is stopped.
In other words, only the process of disconnecting one PCI function that first detects an abnormality is performed. If a plurality of PCI functions are abnormal, it is determined that the function of the host CPU or the PCI bus itself that is a common unit is stopped, and an alarm, etc. Perform sending processing.
[0029]
FIG. 6 shows an example of the function management table 3 after a PCI bus number = 0 / device number = 1 / function number = 1 and an abnormality occurs and the PCI configuration processing is omitted.
[0030]
In this way, a wake-up reset by counting up the WDT is provided so that the reset can be recovered from the stop of the PCI configuration cycle processing for the abnormal function. Further, the access address storage area 2 and the function management table 3 cause an abnormality. A means for storing and holding the access destination (PCI bus number / device number / function number) of the PCI configuration cycle is provided, and a WDT clear process is performed only after completion of all PCI configurations. The one PCI function can be logically separated, and the continuous operability of the system in the normal part can be improved.
[0031]
Further, it is not necessary to add a special H / W circuit for analyzing a PCI transaction.
[0032]
Further, since no electrical load is applied on the PCI bus, one PCI slot expansion slot is not occupied, so that the PCI bus expansion slot can be used effectively.
[0033]
Embodiment 2. FIG.
In the first embodiment, in FIG. 4A, after the wake-up reset is performed by the first WDT count-up at time T3, the PCI configuration is executed for the remaining PCI functions except for the abnormal PCI function. However, a transient abnormality may occur due to the influence of noise or the like, and a normal PCI function may be regarded as abnormal.
In the second embodiment of the present invention, the PCI configuration is re-executed for the PCI functions of all addresses without removing the PCI functions of the abnormal addresses.
That is, the operation corresponding to the period P1 in FIG. 4A is repeated at least once, and then the process proceeds to the period P2.
[0034]
Embodiment 3 FIG.
Next, a third embodiment of the present invention will be described. In the third embodiment, the block diagram is the same as that in FIG. 2 in the first embodiment. The difference from the first embodiment is the flowchart of FIG. 7 showing the processing of the PCI configuration cycle execution unit 1 and the use of FIG. This is the contents of the function management table.
[0035]
Next, the operation will be described.
FIG. 7 is a flowchart showing an example in which the PCI configuration cycle execution unit 1 according to the third embodiment of the present invention performs processing using the function management table 3. In FIG. 7, the same processing steps as those in the first embodiment are given the same step numbers as in FIG. Further, in FIG. 7, only the parts different from those in FIG. 5 will be described with new step numbers ST2-15.
[0036]
When all the PCI buses / devices / functions are normal, the processing is the same as that of the first embodiment, and the description thereof is omitted.
Further, the flow from the power-on reset to the first occurrence of the wake-up reset in the state where an abnormality has occurred with PCI bus number = 0 / device number = 1 / function number = 1 is the same as that of the first embodiment. The description is omitted because it is a process.
[0037]
Next, the flow after the first occurrence of the wakeup reset will be described.
(1) Steps ST1-1 to ST1-14 are the same as in the first embodiment. At this time, the function in the function management table 3 corresponding to PCI bus number = 0 / device number = 1 / function number = 1. The status is set to “1: Abnormal”.
(2) Thereafter, in the third embodiment, a write process to the WDT clear register 5 is performed (step ST2-15),
(3) Shift to configuration repetition processing for all PCI buses / devices / functions (step ST1-4),
(4) Check the target function status to be configured during the current iterative process (step ST1-5),
(5) Since the function status of PCI bus number = 0 / device number = 1 / function number = 1 is set to “1: abnormal”, PCI bus number = 0 / device number = 1 / function number = 1 The PCI configuration process is omitted, and the remaining PCI bus / device / function is repeatedly executed from step ST1-4 (step ST1-9).
[0038]
(6) Here, when the same abnormality occurs in other PCI functions during the PCI configuration of all remaining PCI buses / devices / functions, PCI bus number = 0 / device number = 1 / function number = 3 (See FIG. 8). The PCI configuration processing for the PCI bus number = 0 / device number = 1 / function number = 3 is repeated indefinitely and does not end. As a result, the WDT counter counts up again.
(7) Here, the difference from the first embodiment is that the write to the WDT clear register 5 is performed once in step ST2-15, and therefore a wake-up reset occurs even in the current count-up.
[0039]
(8) After wake-up reset, start again from step ST1-1,
(9) Eventually, an abnormality of both functions of PCI bus number = 0 / device number = 1 / function number = 1 and PCI bus number = 0 / device number = 1 / function number = 3 is detected, and both functions are detected. By omitting the PCI configuration process, both functions are logically separated from the PCI bus.
[0040]
In FIG. 8, after the PCI configuration processing is omitted due to the occurrence of an abnormality with PCI bus number = 0 / device number = 1 / function number = 1 and PCI bus number = 0 / device number = 1 / function number = 3 An example of the function management table 3 is shown.
[0041]
In this way, a wake-up reset by counting up the WDT is provided so that the reset can be recovered from the stop of the PCI configuration cycle processing for the abnormal function. Further, the access address storage area 2 and the function management table 3 cause an abnormality. A means for storing and holding the access destination (PCI bus number / device number / function number) of the PCI configuration cycle is provided, and WDT clear processing is performed each time an abnormal function is detected. It is possible to logically separate the detection and the plurality or all of the abnormal PCI functions, and the continuous operability of the system in the normal part can be improved.
[0042]
  As described above, there are multiple abnormal PCI functions, and all PCI functions with these abnormalities.ButThe configuration can be repeated to complete the configuration until disconnected.
  However, the host CPUcardIf there is a failure, the configuration operation is repeated. To prevent this, if the configuration is performed a predetermined number of times, it is determined that the function of the host CPU or the PCI bus itself, which is a common unit, has stopped, and an alarm is sent to cancel the configuration. You may make it do.
[0043]
Embodiment 4 FIG.
There are many configurations of 1 card = 1 device = 1 function or 1 card = 1 device = multiple functions as hardware mounted on the PCI bus as a system configuration, and an abnormal unit is also a card unit, that is, a device It is often a unit. In the fourth embodiment, logical separation is performed in units of PCI devices, and the system rise time is further shortened.
[0044]
FIG. 9 is a block diagram for realizing a PCI bus fault location isolation method according to the fourth embodiment of the present invention. In the figure, the same blocks as those in the third embodiment are given the same numbers as in FIG. Omitted. Further, in FIG. 9, only parts different from FIG. 2 will be described with new block numbers in the 30s.
In the fourth embodiment, since the unit of logical separation from the PCI bus is a PCI device, the function management table 3 in the third embodiment is a device management table 33. Other blocks are the same as those in the third embodiment.
[0045]
Next, the operation will be described.
FIG. 10 is a flowchart showing an example in which the PCI configuration cycle execution unit 1 according to the fourth embodiment of the present invention performs processing using the device management table 33. In the figure, the same step numbers as those in FIG. In FIG. 10, only steps different from FIG. 7 will be described with new step numbers ST3-3, ST3-5, and ST3-14.
[0046]
When all the PCI buses / devices / functions are normal, the processing is the same as that of the third embodiment, so that the description is omitted.
A flow from a power-on reset in the state where an abnormality has occurred with PCI bus number = 0 / device number = 1 / function number = 1 will be described.
(1) Steps ST1-1 to ST1-2 are exactly the same as in the third embodiment.
(2) Since the reset factor is other than wake-up reset by WDT count-up, all device statuses in the device management table 33 are initialized to “0: normal” (step ST3-3).
[0047]
(3) Steps ST1-4 to ST1-6 perform the same processing as in the third embodiment, and when PCI configuration is performed for PCI bus number = 0 / device number = 1 / function number = 1 (step ST1-7) In some cases, the PCI configuration cycle repeats retry processing indefinitely and does not end. As a result, since writing to the WDT clear register 5 cannot be performed before the WDT count-up, a wake-up reset occurs.
[0048]
Next, the flow after the occurrence of the wake-up reset will be described.
(1) In steps ST1-1 to ST1-13, as in the third embodiment, PCI bus number = 0 / device number = 1 / function number = 1, which is information accessed before the wake-up reset is generated. Originally, the corresponding device status in the device management table 33 is set to “1: abnormal” (step ST3-14),
(2) Move to configuration repetition processing for all PCI buses / devices / functions (step ST1-4),
(3) Check the target device status to be configured during the current iterative process (step ST3-5),
[0049]
(4) Since the device status of PCI bus number = 0 / device number = 1 is set to “1: abnormal”, the PCI configuration processing for all functions of PCI bus number = 0 / device number = 1 is omitted. The remaining PCI bus / device / function is repeatedly executed from step ST1-4 (step ST1-9) to complete the entire PCI configuration.
(5) Write to the WDT clear register 5 before counting up the WDT (step ST1-10).
[0050]
(6) If the same abnormality occurs in other devices during the PCI configuration of all remaining PCI buses / devices / functions, the corresponding device status in the device management table 33 is set to “1: abnormal”. Then, it restarts again from step ST1-1.
Even in this case, since the device management table 33 is held without being cleared, a device for which the PCI configuration processing has already been omitted because of an abnormality last time is omitted again this time.
[0051]
In FIG. 11, after PCI bus number = 0 / device number = 1 / function number = 1 and PCI bus number = 0 / device number = 3 / function number = 1, an error occurs and PCI configuration processing is omitted. An example of the device management table 33 is shown. Note that when configuring or detecting an abnormality in units of functions, since disconnection is in units of devices, no function number is displayed in the device management table 33 in FIG.
[0052]
In this way, a wake-up reset by counting up the WDT is provided so that the reset can be returned from the stop of the PCI configuration cycle processing for the abnormal device. Further, the access address storage area 2 and the device management table 33 cause an abnormality. A means for storing and holding the access destination (PCI bus number / device number) of the PCI configuration cycle is provided, and a WDT clear process is performed every time an abnormal device is detected. The plurality or all of the abnormal PCI devices can be logically separated, and the continuous operability of the system in the normal part can be improved.
[0053]
In addition, the logical detachment in units of PCI devices shortens the system startup time compared with the logical detachment in units of PCI functions.
[0054]
In each of the above embodiments, the PCI bus has been described. However, the present invention can also be applied to a Compact PCI bus that is frequently used recently.
[0055]
【The invention's effect】
(1) As described above, according to the first aspect of the present invention, it is possible to detect one abnormal PCI function and logically separate the one PCI function, and the continuous operation of the system in a normal part. There is an effect of improving.
[0056]
(2) According to the invention described in claim 2, even if there is an abnormality, it is normal even if a transient abnormality occurs due to the influence of noise or the like by repeating the configuration for all PCI functions at least once. The PCI function is prevented from being regarded as abnormal.
[0057]
(3)Claims 1 and 2According to the described invention, if there is an abnormality, the remaining PCI functions are sequentially configured to detect a plurality or all of the abnormal PCI functions and logically separate the plurality or all of the abnormal PCI functions. It is possible to start up only with a normal PCI function, and there is an effect of improving the continuous operability of the system in a normal part.
[0058]
(4) Claim3According to the described invention, since an abnormality is detected in units of PCI devices and the PCI devices are disconnected, there is an effect of improving the continuous operability of the system in a normal part.
[0059]
(5) Claim4According to the described invention, there is an effect that the program improves the continuous operability of the system in the normal part.
[0060]
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a PCI bus system according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing an example of a PCI defective portion isolation method according to the first embodiment of the present invention.
FIG. 3 is an operation example of a WDT circuit used in the PCI defective portion isolation method according to the first embodiment of the present invention;
FIG. 4 is an operation example of a WDT circuit used in the PCI defective portion isolation method according to the first embodiment of the present invention.
FIG. 5 is a flowchart showing an example of a PCI defective portion isolation method according to the first embodiment of the present invention.
FIG. 6 is an example of a function management table used in the PCI defective portion isolation method according to the first embodiment of the present invention.
FIG. 7 is a flowchart showing an example of a PCI defective portion isolation method according to Embodiment 3 of the present invention.
FIG. 8 is an example of a function management table used in the PCI defective portion isolation method according to the third embodiment of the present invention.
FIG. 9 is a block diagram showing an example of a PCI defective portion isolation method according to Embodiment 4 of the present invention.
FIG. 10 is a flowchart showing an example of a PCI defective portion isolation method according to Embodiment 4 of the present invention.
FIG. 11 is an example of a device management table used in the PCI defective portion isolation method according to the fourth embodiment of the present invention.
FIG. 12 is a configuration example of a conventional PCI bus processing device.
[Explanation of symbols]
1 PCI configuration cycle execution unit
2 Access address storage area 3 Function management table
4 WDT circuit 5 WDT clear register
6 Reset generation circuit 7 Reset factor register
12, 13, 14 Add-in card
12a, 13a, 14a PCI devices
12b, 12c, 13b, 14b, 14c PCI function

Claims (4)

If an abnormality occurs when the PCI function or PCI device is configured in a system in which a host CPU card and a PCI device with a built-in PCI function are connected via a PCI bus, the PCI function or PCI that is the target of the abnormality is detected. In the method of isolating a defective part of the PCI bus that isolates the device from the system,
A first step of sequentially performing configuration for each PCI function or each PCI device at the time of starting the system;
A second step of resetting the host CPU card and all PCI functions or PCI devices if there is an abnormality during the configuration;
A third step of disconnecting the PCI function or PCI device having an abnormality after the reset and sequentially performing configuration for each remaining PCI function or PCI device ;
If the abnormality is not resolved even after the configuration is executed in the third step, the second and the second steps are performed so that the host CPU card and all PCI functions or PCI devices are reset. It is characterized in that a plurality of abnormal PCI functions or PCI devices can be separated from the system by performing the fifth step of repeating the third step a predetermined number of times or until the abnormality is resolved with the host CPU card. To isolate defective PCI bus parts. 2. The PCI bus fault location isolation method according to claim 1, wherein after resetting in the second step, returning to the first step and again configuring all PCI functions or PCI devices. at least one repetition, abnormality when persists fourth step the method disconnect the PCI bus failed portion, characterized in that was free Me of the transition to the third step a. 3. The method for isolating a defective PCI bus location according to claim 1 or 2 , wherein the abnormality is not resolved even if the third step is executed, or the abnormality is not eliminated after a desired time after the execution of the third step. or, first to the case where any one of the steps of the third step can not be executed, PCI bus defective portion disconnect method is characterized in that there was including Me a sixth step of determining an abnormality of the host CPU card. The program for performing the PCI bus fault location isolation | separation method of any one of Claims 1-3 .

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