JP3641944B2 - Digital signal circuit of control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital signal circuit of a control device that can reduce the number of transmission lines of a digital signal transmitted from a host control device to a lower control device.
[0002]
[Prior art]
For example, a machine tool includes a plurality of electric motors for driving a workpiece and driving or exchanging a machining tool. The spindle motor that drives the workpiece must adjust the moving speed and rotation speed of the workpiece appropriately, and must also control the stop position so that the workpiece surface is at the proper position. I must. Moreover, the electric motor that drives the machining tool must individually control the rotation speed or the stop position. Recently, the performance of inverters using semiconductor switch elements has been improved and the control of induction motors can be performed freely, so the overload capacity is small and expensive, and direct current is troublesome for maintenance and inspection. Induction motors are often used instead of electric motors. Therefore, the case where the induction motor is controlled by an inverter will be described below.
[0003]
FIG. 5 is a circuit diagram showing a conventional example of the state of a signal transmission line for digital signals laid between a host controller and a slave controller, in which a master controller as a host controller serves as a slave controller. A case is shown in which a digital speed command value and position command value are sent to each of three inverters.
Conventional speed control and position control of motors were mainly done with analog quantities, but because of the improved performance of microcomputers, control with digital quantities has recently been improved to improve control accuracy and responsiveness. A lot is happening. In the conventional example shown in FIG. 5, a speed command value of a plurality of bits (12 bits in the circuit of FIG. 5) is sent from the master controller 1 to the No. 1 inverter 11 in order to operate the No. 1 motor 10 at a desired rotational speed. However, the speed command transmission line 12 having the number of circuits (12 circuits in FIG. 5) corresponding to the number of bits is laid between the both. Further, in order to stop a load (not shown) driven by the No. 1 motor 10 at a predetermined stop position, a position command value of a plurality of bits (12 bits in FIG. 5) is given from the master controller 1 to the No. 1 inverter 11. Therefore, the position command transmission lines 13 having the number of circuits corresponding to the number of bits (12 circuits in FIG. 5) are laid between the two. The speed adjustment operation for inputting the speed command value to operate the No. 1 motor 10 at a desired rotational speed and the operation for inputting the position command value to stop the No. 1 motor 10 at a predetermined stop position are described in the present invention. Since this is irrelevant to this, the description thereof will be omitted.
[0004]
A 12-circuit speed command transmission line 22 and a 12-circuit position command transmission line 23 are also laid between the No. 2 inverter 21 that supplies power to the No. 2 motor 20 and the master controller 1, and power is supplied to the No. 3 motor 30. 12 circuit speed command transmission lines 32 and 12 circuit position command transmission lines 33 are also laid between the supplied No. 3 inverter 31 and the master controller 1. That is, 24 signal transmission lines are introduced into each inverter for speed control and position control.
[0005]
In addition, a signal transmission line for transmitting many other signals is laid from the master controller 1 to each of the inverters 11, 21, 31, but other signals are not related to the present invention. Therefore, illustration and description are omitted.
[0006]
[Problems to be solved by the invention]
As is apparent from the conventional circuit shown in FIG. 5, 24 signal transmission lines are required between the master controller 1 and the No. 1 inverter 11. The number of signal transmission lines increases in proportion to the number of types of digital signals given to each inverter from the master controller 1 and the number of bits of these digital signals. If the number of inverters controlled by the master controller 1 increases, the number of signal transmission lines increases. The number will increase, and a large space must be reserved for laying these many signal transmission lines. For this reason, the entire apparatus is enlarged, and the price of the apparatus is increased. In addition, since the master controller 1 and each inverter need a number of terminals corresponding to the number of signal transmission lines, the space for installing these terminals also has the disadvantage of further increasing the size of the apparatus. .
[0007]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to reduce the number of signal transmission circuits for transmitting a plurality of types of multi-bit digital signals from a host control device to a lower control device.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a digital signal circuit of a control device according to the present invention includes a first transmission line for transmitting a multi-bit digital signal from a high-order control device to a low-order control device, and from the high-order control device to the low-order control device. A second transmission line for transmitting a 1-bit digital signal to the second transmission line, a third transmission line for transmitting another 1-bit digital signal from the higher order control device to the lower order control device, and corresponding to the state of the 1-bit digital signal When the multi-bit digital signal is switched from one application to the other, the one application uses a first signal switching circuit that switches to the other application while retaining the multi-bit digital signal immediately before switching, When turning on or off the multi-bit digital signal for each application corresponding to the state of the 1-bit digital signal, Each application includes a second signal switching circuit that is turned off while retaining a multi-bit digital signal immediately before being turned off, and the second signal switching circuit is configured to receive data of the multi-bit digital signal. It is assumed that during the period from immediately before the change to the completion of the change, the other 1-bit digital signal is turned off.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a time chart showing the operation of the first embodiment of the present invention. FIG. 1 (1) is a change in a 12-bit digital signal, and FIG. 1 (2) is a speed command / position as a 1-bit digital signal. The change of the command switching signal, FIG. 1 (3) shows the change of the speed command signal, and FIG. 1 (4) shows the change of the position command signal, respectively. In this example, the data is simply referred to as a 12-bit signal), and the data sequentially changes in the order of A → B → C → D → E → F. In this case, the position command signal is selected when it is off, and the speed command signal is selected when it is on.
[0012]
In the time chart of FIG. 1, it is assumed that both the speed command signal and the position command signal are in the state of data A. At time t ₁ , the switching signal is off and the position command signal is selected. When changing to data B, the position command signal also changes to data B, but the speed command signal continues to hold data A. Since the 12-bit signal is data B when the switching signal is turned on at time t ₂ , the speed command signal is switched to data B here, and then is switched to data C at time t _3. The signal remains data B. However, when the switching signal is turned off again at time t ₄ , the position command signal is switched to data C, and is switched to data D at time t ₅ and switched to data E at time t ₆ according to the data of the 12-bit signal. The speed command signal during this period remains data C. When the switching signal is turned on again at time T ₇ , the speed command signal becomes data E and then switches to data F at time t ₈ , but the position command signal continues to hold data E.
[0013]
FIG. 2 is a time chart showing the operation of the second embodiment of the present invention. FIG. 2 (1) is a change in a 12-bit digital signal, and FIG. 2 (2) is a 12-bit digital signal as another 1-bit digital signal. Changes in the signal selection signal, FIG. 2 (3) is a change in the speed command / position command switching signal as a 1-bit digital signal, FIG. 2 (4) is a change in the speed command signal, and FIG. 2 (5) is a position command signal. The 12-bit signal is off when the 12-bit signal selection signal (hereinafter simply referred to as the selection signal) shown in (2) is off, and only when it is on. Bit signal can be selected. 2 (1), 2 (3), 2 (4), and 2 (5) are respectively the same as (1), (2), (3), and (4) described in FIG. Since it corresponds, these description is abbreviate | omitted.
[0014]
In the time chart of FIG. 2, the 12-bit signal shown in (1) changes in the order of A → B → C → D → E → F with the passage of time as in FIG. ▲ 2 ▼ in (simply referred to as selection signal in the following) 12-bit signal selection signal illustrated since turned off again at time t ₁₇ I I switched from OFF to ON at time t _11, the speed command or a 12-bit signal can be used as the position command is the period from the time t ₁₁ to time t _17. The second embodiment of FIG. 2 is different from the first embodiment of FIG. 1 in that this selection signal is added, and everything else is the same as the first embodiment already described in FIG. However, the operation is as follows.
[0015]
That is, until the selection signal is turned on at time t ₁₁ , neither the speed command signal nor the position command signal reads the 12-bit signal. Selection signal at time t ₁₁ the signal switching when turned on is selected and the position signal because it is off, the data A of 12-bit signal at that point becomes the position command signal. If the data of the 12-bit signal changes to B at time t ₁₂ , the position command signal also becomes data B. Then the signal switching time t ₁₃ the speed command signal is turned on is selected, the speed command signal becomes a data B of 12-bit signal at that time, at time t ₁₄ is changed to data C, position command signal continues to hold the data B at t ₁₃ time. Further, the position command signal becomes data C in response to the switching signal being turned off again at time t ₁₅ and selecting the position command signal, and then changes to data D at time t ₁₆ , but the speed command signal is t ₁₅ continues to hold the data C at the time. Since further selection signal at time t ₁₇ is 12-bit signal by turned off is turned off, the speed command signal and a position command signal both will continue to hold the data at that time. That is, the speed command signal holds data C, and the position command signal holds data D.
[0016]
FIG. 3 is a time chart showing the operation of the third embodiment of the present invention. FIG. 3 (1) shows a change in a 12-bit digital signal, and FIG. 3 (2) shows a 12-bit digital signal as another 1-bit digital signal. Changes in the signal selection signal, FIG. 3 (3) is the change in the speed command / position command switching signal as a 1-bit digital signal, FIG. 3 (4) is the change in the speed command signal, and FIG. 3 (5) is the position command signal. 2 and is the same as the time chart of the second embodiment already described in FIG. 2, but in this third embodiment, when the selection signal shown in FIG. This is different from the second embodiment of FIG. 2 in that the selection signal is temporarily turned off when the data of the 12-bit signal is switched. Changing the data of the 12-bit signal requires a switching time even if it is a short time, and the selection signal is temporarily turned off in order to prevent data disturbance during the switching time. As described above, since both the speed command signal and the position command signal have a function of holding data immediately before the selection signal is turned off, there is no problem even if the selection signal is turned off. When the selection signal is turned on after a short time, the speed command signal or the position command signal reads the new data that has been switched and continues the operation.
[0017]
FIG. 4 is a circuit diagram showing the implementation status of the third embodiment already described with reference to FIG. In FIG. 4, between the master controller 1 and the No. 1 inverter 11, a 12-bit signal line 41 (12 lines) as a first transmission line for transmitting a 12-bit digital signal and a second for transmitting a 1-bit digital signal. A speed / position switching signal line 42 (1 line) as a transmission line and a 12-bit signal selection signal line 43 (1 line) as a third transmission line for transmitting another 1-bit digital signal are laid. That is, by laying 14 lines in total, it is possible to exhibit the same function as the conventional 24 lines. However, illustration of other lines unrelated to the present invention is omitted. Further, in the No. 1 inverter 11, a first signal switching circuit 44 for switching a 12-bit signal to either a speed command or a position command in response to on / off of the speed command / position command switching signal described above, A second signal switching circuit 45 for turning on / off a 12-bit signal corresponding to on / off of the bit signal selection signal is incorporated.
[0018]
The same line is laid between the master controller 1 and the No. 2 inverter 21 and between the master controller 1 and the No. 3 inverter 31, and the No. 2 inverter 21 and the No. 3 inverter 31 have the same functions. First signal switching circuits 54 and 64 and second signal switching circuits 55 and 65 are provided.
[0019]
【The invention's effect】
In order to transmit separate multi-bit digital signals from the host controller to the lower controller for multiple applications, the number of transmission lines corresponding to the number of bits must be laid separately for each application. The subordinate control device requires a large space for installing a number of terminals corresponding to a large number of lines. In addition, a higher-level control device that controls a large number of lower-level control devices requires a larger terminal space in order to connect more lines. In addition, the number of lines between the upper and lower control devices has increased, resulting in problems such as an increase in the size of the entire device in order to secure a wiring space and a problem in that the price increases. According to the present invention, a second transmission line for transmitting a 1-bit digital signal as a switching signal and a first signal for switching operation so that a set of multiple-bit digital signals can be used by switching to a plurality of applications. By adding a switching circuit, the number of transmission lines for a multi-bit digital signal can be reduced from a plurality of sets to one set, so that the number of transmission lines can be reduced and the wiring space can be reduced. In addition, since the number of terminals to which lines are connected can be reduced and the terminal space can be reduced, the effect of miniaturizing the apparatus can be obtained. Further, in order to turn on / off the multi-bit digital signal, a third transmission line for transmitting another 1-bit digital signal and a second signal switching circuit for turning on / off the multi-bit digital signal are added. The effect of turning on / off the multi-bit digital signal is also obtained.
[Brief description of the drawings]
1 is a time chart showing the operation of the first embodiment of the present invention. FIG. 2 is a time chart showing the operation of the second embodiment of the present invention. FIG. 3 shows the operation of the third embodiment of the present invention. FIG. 4 is a circuit diagram showing the implementation status of the third embodiment described above in FIG. 3. FIG. 5 is a signal transmission line for digital signals laid between the host controller and the lower controller. Schematic showing the conventional example of the situation [Explanation of symbols]
1 Master Controller 10 as Host Controller No. 1 Motor 10
11 No. 1 inverter 12, 22, 32 as subordinate control device Speed command transmission line 13, 23, 33 Position command transmission line 20 No. 2 motor 21 No. 2 inverter 30 as subordinate control device No. 3 motor 31 As subordinate control device No. 3 inverters 41, 51, 61 12-bit signal lines 42, 52, 62 as first transmission lines Speed / position switching signal lines 43, 53, 63 as second transmission lines 12-bit signal selection as third transmission lines Signal lines 44, 54, 64 First signal switching circuit 45, 55, 65 Second signal switching circuit

Claims (1)

A first transmission line for transmitting a plurality of bits digital signal to the low order control device from the host controller, and a second transmission line for transmitting the 1-bit digital signal to the low order control device from said host controller, said from the host controller A third transmission line for transmitting another 1-bit digital signal to a lower-level control device, and the one of the plurality of bits when the multi-bit digital signal is switched from one application to the other in response to the state of the 1-bit digital signal. Uses a first signal switching circuit for switching to the other application while holding the multi-bit digital signal immediately before switching, and the multi-bit digital signal for each application corresponding to the state of the other 1-bit digital signal. When turning on or off, each application is turned off while retaining the multi-bit digital signal immediately before turning off. A second signal switching circuit provided in the lower-level control device, wherein the second signal switching circuit has a period from immediately before the change of the data of the multi-bit digital signal to the completion of the change of the other 1-bit digital signal. A digital signal circuit of a control device characterized by turning off the power .

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