JP3641878B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a low-resistance silicide electrode on a silicon (Si) substrate or a polysilicon layer in a self-aligning manner and with a small amount of silicon consumption.
[0002]
[Prior art]
As the performance of semiconductor devices such as integrated circuits increases, silicide electrodes using transition metals such as cobalt and titanium are used as a low-resistance electrode forming technique.
[0003]
A conventional example of a MOS FET using this technique will be described with reference to FIGS.
5 (a) to 5 (c) and FIGS. 6 (d) to 6 (e) are explanatory views of the first conventional example.
In FIG. 5A, a field oxide film 302 is formed on a p-type silicon (p-Si) substrate 301, and a gate oxide film 303 is formed on the element formation region by thermal oxidation.
[0004]
Next, a polysilicon film 304 is deposited, and a thermal oxide film 305 is formed on the surface by heating.
In FIG. 5B, a gate electrode G is formed by using a photolithography technique, and ions are implanted to form a source region 306 and a drain region 307.
[0005]
In FIG. 5C, an electrode forming window 308 is opened on the source region 306, the drain region 307, and the gate electrode G, and a transition metal film 309 such as cobalt and titanium is deposited on the entire surface of the substrate.
[0006]
In FIG. 6D, the substrate is heated to cause the metal in the region of the window 308 to react with silicon to form a metal silicide layer 310. Here, the metal silicide layer is, for example, CoSi ₂ (90 to 150 μΩ-cm), C54 phase TiSi ₂ (60 to 70 μΩ-cm).
[0007]
In FIG. 6 (e), unreacted metal in the region other than the window 308 is removed by etching, and heated again at a temperature higher than the above heating, so that the metal silicide becomes a lower resistance silicide. In this example, CoSi (15-20 μΩ-cm) and C49 phase TiSi ₂ (10-15 μΩ-cm).
[0008]
In this method, when a metal silicide is formed, an amount of silicon (Si) proportional to the metal film thickness is consumed, and the silicide / silicon boundary penetrates into the silicon to the consumed depth. In this case, the penetration depth differs depending on the metal, which is 3.58 times the thickness of the cobalt film in the case of cobalt silicide, and 2.28 times the thickness of the titanium film in the case of titanium silicide. In the case of cobalt silicide, the resistance does not increase even if the line width of the electrode is 1 μm or less, but the penetration depth is larger than that of titanium silicide.
[0009]
In this method, pure metal is deposited. However, in Japanese Patent Application Laid-Open No. 07-153717, instead of a pure metal film, metal and silicon are deposited at the same time, and both are mixed in the film (metal: silicon = 1). : 0.25 to 1: 0.75) is deposited and heated to reduce the consumption of the underlying silicon and reduce the penetration depth. Next, this example will be described with reference to FIG.
[0010]
7 (a) to 7 (d) are explanatory views of the second conventional example.
In FIG. 7 (a), a film (metal: silicon) in which metal and silicon are deposited at the same time, covering a portion 401A covered with an oxide film of a semiconductor device substrate 401 and a portion 401B where silicon is exposed, and simultaneously depositing metal and silicon. = 1: 0.25 to 1: 0.75).
[0011]
In FIG. 7 (b), when the substrate is heated, in the portion 401A covered with the oxide film, only silicon in the film reacts with the metal, so that a silicide layer 403 with a small silicon ratio is formed, while silicon is exposed. In the portion 401B, since silicon is also supplied from the underlying silicon, a silicide layer 404 having a large silicon ratio is formed.
[0012]
In FIG. 7C, only the silicide layer 403 with a small silicon ratio is etched, and only the silicide layer 403 with a small silicon ratio is selectively removed using an etchant that does not etch the silicide layer 404 with a large silicon ratio.
[0013]
In FIG. 7D, second heating is performed at a temperature higher than the above heating, and the silicide layer 40 4 is changed to a silicide layer 405 having a larger silicon ratio to form a low-resistance silicide electrode.
[0014]
[Problems to be solved by the invention]
As the integration density of MOS FET integrated circuits increased, the electrode dimensions became finer, and the width of the source and drain electrodes became 0.5 μm or less. In addition, as the pattern becomes finer, the depth of the impurity diffusion layers of the source and drain becomes smaller. Even if the electrode is for a shallow diffusion layer with such a fine dimension, the processing speed cannot be improved unless the resistance is maintained at the same level as that of a device with a low degree of integration. In other words, as the electrode width decreases, the thickness must be increased.
[0015]
It is an object of the present invention to reduce the depth of penetration of silicide when forming a silicide electrode and to reduce the resistance to achieve higher device integration and higher speed.
[0016]
[Means for Solving the Problems]
The solution to the above problem is
1) a first step of forming an insulating film having a region where the silicon layer is exposed on a substrate having a silicon layer; and a second step of depositing a metal film on the exposed substrate including the insulating film. A third step of depositing a silicon film on the metal film with a film thickness in which the silicon ratio is smaller than metal: silicon = 2: 1 by an element ratio; and heating the silicon substrate to form the silicon film Forming a metal silicide layer having a large silicon ratio in the exposed region and forming a metal silicide layer having a small silicon ratio in the region covered with the silicon oxide film; and a metal silicide layer having a small silicon ratio. A method of manufacturing a semiconductor device including a fifth step of selectively removing a layer, or 2) a method of manufacturing a semiconductor device according to 1 above, wherein the second and third steps are performed a plurality of times, or 3) the fourth step. After the, 4. The method for manufacturing a semiconductor device according to 1 above, wherein the heating is performed at a temperature higher than the heating in the fourth step, or 4) The method for manufacturing a semiconductor device according to 1 above, wherein the metal film is a transition metal film. Is done.
[0017]
In the present invention, when a silicide is formed by reacting a transition metal with silicon, a silicon film is deposited in advance on the metal film, and silicon necessary for the silicide formation is not only from the underlying silicon but also from the silicon film on the metal film. In addition, a low resistance metal silicide electrode is formed in a self-aligning manner and with a small amount of underlying silicon consumption by controlling the ratio of the metal and the silicon film thereon.
[0018]
FIGS. 1A to 1E are explanatory views of the principle of the present invention.
In FIG. 1A, a metal film 102 is deposited to cover a portion 101A covered with an oxide film of a semiconductor substrate 101 and a portion 101B where silicon is exposed, and a silicon film 103 is deposited thereon. At this time, the thickness of the silicon film 103 is determined to be smaller than 1/2 in terms of the element ratio with the metal film 102.
[0019]
In FIGS. 1B and 1C, when the substrate is heated, only the silicon in the film reacts with the metal in the portion 101A covered with the oxide film, so the silicon ratio is smaller than metal: silicon = 2: 1. A silicide layer 104 is formed. On the other hand, in the portion 101B where silicon is exposed, silicon is supplied also from the underlying silicon, so that a silicide layer 105 having a silicon ratio larger than metal: silicon = 2: 1 is formed.
[0020]
In FIG. 1D, only the silicide layer 104 having a small silicon ratio is etched, and only the silicide layer 104 having a small silicon ratio is selectively removed using an etchant that does not etch the silicide layer 105 having a large silicon ratio.
[0021]
In FIG. 1 (e), the second heating is performed at a temperature higher than the above heating, and the silicide layer 105 is changed to the silicide layer 106 having a larger silicon ratio to form a low-resistance silicide electrode.
[0022]
The operation of the present invention will be described.
When forming metal silicide, especially cobalt silicide, the depth that the silicide layer penetrates deeply into the underlying silicon is unique to the metal. Therefore, to reduce the penetration depth, the thickness of the metal film must be reduced. There was no other way. On the other hand, in the present invention, a silicon film is deposited on a metal film as a silicon supply source, and the penetration depth is reduced by reducing the consumption of the underlying silicon.
[0023]
As a result, as the degree of integration increases, the source and drain impurity diffusion layers become shallower. With this, even if the silicide layer must be thin, that is, the metal layer must be thin, without penetrating the shallow base impurity diffusion layer, The resistance of the electrode can be reduced by maintaining the thickness of the metal layer.
[0024]
Here, the thicker the silicon film on the metal film, the smaller the penetration of the silicide layer. However, the silicide formed on the field oxide film becomes silicon rich, and the selective etching with the silicide on the silicon substrate becomes impossible. Consistently, silicide cannot be formed on the silicon substrate.
[0025]
For this reason, in the present invention, selective etching is possible by suppressing the film thickness of the silicon film to be smaller than metal: silicon = 2: 1 in terms of element ratio.
According to the experimental results, in the final stage where the silicide is formed by the second heating, the decrease in the penetration distance of the silicide is maximum at metal: silicon = 2: 1, and the penetration distance is 3/4 of the conventional distance.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described for an n-channel MOS FET using cobalt as a transition metal.
[0027]
2 (a) to (c), FIGS. 3 (d) to (F), and FIGS. 4 (g) to (i) are explanatory diagrams of the embodiment of the present invention.
In FIG. 2A, a field oxide film 202 is formed on a p-Si substrate 201, and a gate oxide film 203 having a thickness of 50 mm is formed on the element formation region by thermal oxidation.
[0028]
Next, a polysilicon film 204 having a phosphorus concentration of 10 ²⁰ cm ⁻³ or more, for example, 1 × 10 ²¹ cm ⁻³ is deposited on the entire surface of the substrate, and a thermal oxide film 205 is formed on the surface by heating.
In FIG. 2B, a gate electrode G is formed by using a photolithography technique, and arsenic (As) is ion-implanted to form a source region 206 and a drain region 207.
[0029]
In FIG. 2C, a silicon dioxide (SiO ₂ ) film 208 is deposited on the entire surface of the substrate by vapor deposition (CVD).
In FIG. 3D, the SiO ₂ film 208 is etched so as to remain only on the side surface of the gate electrode by anisotropic etching such as reactive ion etching (RIE) method or sputter n-type method.
[0030]
In FIG. 3 (e), after the surface is cleaned by acid treatment, the oxide films 203 and 205 on the polysilicon film 204, the source region 206, and the drain region 207 of the gate electrode are removed, and a vacuum evaporation method or a sputtering method is used. As a result, a cobalt film 209 having a thickness of 100 mm is deposited on the entire surface of the substrate.
[0031]
In FIG. 3 (f), a silicon film 210 is deposited on the entire surface of the substrate. The thickness of the silicon film 210 is made smaller than 1/2 of the element ratio with cobalt. Since the density of cobalt is 8.9 g / cm ³ and the atomic weight is 58.93, it is 0.151 mol / cm ³ . Moreover, since the density of silicon is 82.33 g / cm ³ and the atomic weight is 28.09, it is 0.083 mol / cm ³ . Therefore, the thickness of silicon is 91 mm or less, for example 90 mm.
[0032]
In FIG. 4G, the substrate is heated at a temperature of 400 to 900 ° C., for example, 500 ° C. in an argon atmosphere to react the metal and silicon to form a metal silicide layer. Here, the metal silicide layer forms a Co ₂ Si layer 211 having a silicon ratio smaller than cobalt: silicon = 2: 1 on the oxide film, while CoSi having a silicon ratio larger than cobalt: silicon = 2: 1 on silicon. Layer 212 is formed.
[0033]
In FIG. 4 (h), an etchant in which only the Co ₂ Si layer 211 on the oxide film is etched and the CoSi layer 212 on the silicon is not etched, for example, using an etchant of hydrochloric acid: hydrogen peroxide = 3: 1 ₂ Only the Si layer 211 is removed by etching. The etching time is 10 minutes.
[0034]
In FIG. 4 (i), the substrate is heated in an argon atmosphere at a temperature of 400 to 900 ° C., for example, 800 ° C., and the CoSi layer 212 is changed to a silicide CoSi ₂ layer 213 having a higher silicon ratio. The silicide layer.
[0035]
Below, in accordance with the normal MOS FET manufacturing process, the entire surface of the phosphosilicate glass (PSG) film is deposited, the contact hole is formed, the aluminum (Al) wiring is formed, the protective PSG film is deposited, the window for the bonding pad An n-channel MOS FET is manufactured through processes such as opening.
[0036]
In this example, argon is used as an atmosphere for heat treatment, but heat treatment may be performed in nitrogen or in vacuum. However, if a nitrogen atmosphere is used, the silicide surface may be nitrided, which must be taken into account.
[0037]
In this example, the thickness of the metal layer is 100 mm of cobalt and 90 mm of silicon, but it is necessary to select an appropriate combination of thickness depending on the desired cobalt silicide thickness and silicide penetration depth.
[0038]
As a metal for forming the metal silicide, titanium, nickel, vanadium, tungsten, molybdenum, zirconium, platinum, or the like can be used in addition to the example of the embodiment.
[0039]
In the embodiment, the metal film and the silicon film are stacked one by one. However, the element ratio of the metal and silicon may be 2/1 or less as a whole by stacking a plurality of layers.
In addition, it goes without saying that the silicon layer in the embodiment includes a silicon substrate, polysilicon, amorphous, and the like.
[0040]
【The invention's effect】
According to the present invention, when the silicide electrode is formed, the depth of penetration of the silicide is reduced and the resistance can be lowered, so that the device can be highly integrated and increased in speed.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of the principle of the present invention. FIG. 2 is an explanatory diagram of an embodiment of the present invention (1).
FIG. 3 is an explanatory diagram of an embodiment of the present invention (2)
FIG. 4 is an explanatory diagram of an embodiment of the present invention (3).
FIG. 5 is an explanatory diagram of Conventional Example 1 (1)
FIG. 6 is an explanatory diagram of Conventional Example 1 (2)
FIG. 7 is an explanatory diagram of Conventional Example 2 [Explanation of symbols]
101 Semiconductor substrate
101A Oxide covered part
101B Silicon exposed part
102 Metal film
103 silicon film
104 Silicide layer with low silicon ratio
105 Silicide layer with high silicon ratio
106 Silicide layer with higher silicon ratio
201 p-Si substrate
202 Field oxide film
203 Gate oxide film
204 Polysilicon film
205 Thermal oxide film
206 Source area
207 Drain region
208 SiO ₂ film
209 Cobalt film
210 Silicon film
211 Cobalt silicide (Co ₂ Si) layer
212 Cobalt silicide (CoSi) layer
213 Cobalt silicide (CoSi ₂ ) layer

Claims (4)

Forming an insulating film having a region where the silicon layer is exposed on a substrate having a silicon layer;
A second step of depositing a metal film on the substrate including the exposed insulating film;
A third step of depositing a silicon film on the metal film with an element ratio such that the silicon ratio is smaller than metal: silicon = 2: 1;
The silicon substrate is heated to form a metal silicide layer with a large silicon ratio in a region where the silicon is exposed, and a metal silicide layer with a small silicon ratio is formed in a region covered with the silicon oxide film. Process,
And a fifth step of selectively removing the metal silicide layer having a small silicon ratio. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the second and third steps are performed a plurality of times. 2. The method of manufacturing a semiconductor device according to claim 1, wherein after the fourth step, heating is performed at a temperature higher than that of the fourth step. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the metal film is a transition metal film.

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