JP3633935B2 - Video display device to suppress line flicker by adaptive deinterlacing. - Google Patents

Description

The present invention relates to the suppression of line luminance flicker in video display devices.
BACKGROUND OF THE INVENTION In a current broadcasting television apparatus, a screen or a frame is composed of two fields that are generated and transmitted continuously in time. This image scanning and display method is called interlaced scanning. Interlaced scanning has various advantages, one of which is the removal of flicker in a large area image obtained by displaying each image twice per screen. However, the two fields may be shifted in time due to occurrence, and are surely shifted in time due to transmission, resulting in artifacts during vertical movement in the displayed image. For example, an edge of vertical movement is drawn by a line from one field or a part thereof. Therefore, the edge of vertical movement is represented by a signal that appears once per screen or frame. However, due to the decay of the light emission of the display illuminant, the edge loses brightness before emitting light again in the next frame. Accordingly, since the interlace processing cannot increase the image display rate with respect to the edge line more than the visual recognition rate of human beings, an edge that defines a line-like luminance flicker is generated at the screen rate. .
It is well known that visible edges or line flicker can be reduced by adaptive modulation of the vertical deflection field. However, a deflection amplifier used for such adaptive modulation needs to use two control signals. The first signal determines the magnitude of the modulation, and the second signal controls the bridge structure for determining the direction of deflection. The amplifier for adaptive modulation of the vertical deflection field is preferably simplified to respond to a single control signal representing both magnitude and direction.
SUMMARY OF THE INVENTION A video display device consists of a CRT having a scanning electron beam representing a raster. The electron beam is deflected by complementary deflection means. The video display device is connected to the display video source, detects the flicker-induced signal in the display video source, and is necessary for the displacement signal having a magnitude proportional to the amplitude of the flicker-induced signal from the display video source and the compensation of the flicker. Means for generating a direction signal representative of a given direction. The video display device is coupled to the displacement signal and the direction signal to generate an analog signal, and to apply the analog signal to the complementary deflection means for deflecting the electron beam by an amount related to the displacement signal. And a means for coupling.
[Brief description of the drawings]
FIG. 1 is a block diagram of an apparatus according to the arrangement of the present invention.
FIG. 2 is a circuit diagram of an embodiment of the present invention.
3A and 3B are diagrams showing details of the configuration of the auxiliary coil for modulation of the vertical deflection field shown in FIGS. 1 and 2. FIG.
DETAILED DESCRIPTION OF THE INVENTION In a video display device, edge or line flicker is achieved by adaptive adjustment of vertical deflection such that edge information is moved on the surface of the cathode ray tube towards the object on which the edge defines. Will be reduced. In addition, adaptive adjustments or dynamic de-interlacing may be proportional to the video level or edge strength, so that a flickering edge with respect to a bright area is displaced to touch that area. And is actually mixed with the area. For low brightness regions, the edge placement displacement required to reduce flicker visibility may be smaller. Such complementary modulation can be achieved, for example, by electrostatic or electromagnetic means such as an auxiliary coil attached to the neck of the cathode ray tube.
FIG. 1 is a block diagram of a line flicker reduction apparatus according to the arrangement of the present invention. Composite video signal V is coupled to analog / digital converter 100. The converter 100 samples the composite video signal V at 12.5 MHz, for example. The sample is quantized into an 8-bit word a + that appears as a parallel signal at the output of the converter 100. Since the digitized signal is delayed and reconverted to an analog signal for a CRT display, 8-bit quantization is chosen to maintain the quality of the video signal. The sample rate of the converter 100 is selected based on the required video display quality and for circuit convenience with respect to clock frequency generation, ease of filtering, and the like. The composite video signal is also coupled to the synchronizer 150. Although not shown, the synchronization device includes a synchronization signal separator, a synchronization signal generator, and a phase locked clock generator. The synchronization signal generator is locked to a separate input video synchronization signal, for example an integrated circuit of model number SAA1043. The synchronizer 150 outputs various timing signals coupled to the entire apparatus shown in FIG.
The 8-bit parallel digital video signal word a + from the converter 100 is coupled to an 8-bit digital delay 30 having a horizontal period or a delay time of 1H. The video path of the display device requires a one line delay in order to display the video symmetrically with respect to flicker correction. The 1H delayed video sample a is coupled to a digital to analog converter 700 which generates an analog value for each of the 8-bit digital input words. Therefore, the output of the converter 700 is a composite video signal v that substantially matches the original composite input signal V but is delayed by one horizontal period. It is well known that prior to sampling in an analog / digital converter, a low pass filter is required to limit the bandwidth of the input signal in proportion to the sampling frequency. Similarly, following digital conversion to analog signal format, the low pass filter has the advantage of removing the sample frequency component from the reproduced signal. The composite video signal v delayed by one television line is coupled to the decoder 800, which separates the various signal components from the composite signal and provides an appropriate drive signal for display on the cathode ray tube. Generate from. For example, in FIG. 1, the red, green, and blue signals are coupled to the CRT for display.
A 4-bit digital video signal has sufficient quantization accuracy for flicker detection and correction signal generation. Accordingly, the 8-bit digital video signal a + is rounded to a 4-bit signal A +. Here, the 4 bits indicate the most significant 4 bits in the original 8-bit word a +. The rounded 4-bit digital signal A + is coupled to flicker detection logic and digital signal generator 200. The 8-bit digital video signal a delayed by one horizontal period is similarly rounded to 4 bits to generate a signal A. Signal A is coupled to flicker detection logic and digital signal generator 200 and a 4-bit digital delay 400 having a delay of one horizontal period. The output signal A- from the delay 400 is coupled to a flicker detection logic and digital signal generator 200 and a 4-bit digital delay 500 having a delay of approximately one field period. One field period represents, for example, 312 horizontal line periods in a 625 line device. The 4-bit digital signal B +, which is the output from delay unit 500, is coupled to generator 200 and digital delay unit 600. A digital delay 600 having a delay of one horizontal period outputs an output signal B-, which is coupled to the generator 200.
Generator 200 is a flicker detection and correction signal generator, used to detect edge flicker induced signals, extract an adjusted vertical displacement signal, and determine the direction of the adjusted displacement, ie upward or downward 5 digital video signals are received. A detailed description of the operation of the generator 200 is described in US Pat. No. 4,888,529 to Madsen et al. However, a brief description will be given below. In order to detect an edge flicker-inducing signal, each pixel includes a preceding pixel, that is, a pixel having the same horizontal position but one line period ahead, and a subsequent pixel, that is, a pixel delayed by one horizontal period. Compared vertically. Thus, the digital signal A represents the top and bottom to be compared with adjacent pixels and the reference pixel in the previous field. Signal A + represents a pixel one line after the reference pixel, and signal A- represents a pixel one line before. The signal B + represents the position of the reference pixel one field before, and the signal B- represents a pixel one line preceding the reference pixel of the previous field. The adjustment direction is determined by comparison with the pixels B + and B− from the previous field of the reference pixel A, thereby obtaining a 1-bit displacement direction signal. Algorithms are used that determine the magnitude of the vertical displacement proportional to the value of the amplitude of the video signal making up the blinking edge. This size determination algorithm is described in the cited document. The function of the generator 200 is obtained by a field programmable gate array semiconductor device such as XC3030PC68.
The output signal from the generator 200 consists of a single bit direction signal D and a 4-bit displacement signal S, which are coupled to the drive circuit 900 of the present invention. The drive circuit 900 includes a digital / analog converter 910 and a deflection drive amplifier 920. At the input of D / A 910, a 1-bit direction signal D is combined with a 4-bit magnitude signal S to generate a 5-bit signal word M. The 1-bit direction signal D represents the most significant bit in the 5-bit word M. As will be described below, the digital / analog converter 910 generates a unipolar output signal Up for each 5-bit input word. The output signal Up is coupled to a deflection driver amplifier 920 that generates a complementary deflection signal ΔV. The complementary deflection signal ΔV is coupled to deflection means 950 attached to the cathode ray tube CRT.
One embodiment of the drive circuit 900 of the present invention shown in FIG. 1 is shown in FIG. The digital / analog converter 910 includes an integrated circuit U1 such as a model number BT106, for example. The digital / analog converter has an internal reference connected to a bandgap reference device Z1 that is powered from a 5 volt power supply and generates a voltage of 1.2 volts. The clock pulse signal is coupled to a D / A converter that determines the timing of the function of the converter. Capacitors C4 and C5 provide power supply decoupling. The integrated circuit U1 is an 8-bit converter, in which only 5 data input bits are used, and the least significant 3 bits are grounded. Data inputs D3-D6 are coupled to a 4-bit displacement signal S from detector and digital signal generator 200. The fifth data input bit D7 is coupled to the 1-bit up / down signal D from the generator 200. The digital / analog converter U1 generates an output current at Iout according to the value of the input data word M. Since converter U1 is connected between ground and a +5 volt power supply, the output signal of the D / A is represented by a unipolar direct current.
The current from the output Iout is coupled to the resistor R1 to generate a DC voltage signal Up having a single pole and one range of voltage polarity from zero to a positive value. The output signal of Iout is a direct current with a special constant value defined by the word M and held for one clock cycle. In the next clock cycle, a new word M is converted and the current in Iout is advanced to a new value. Therefore, the output signal of Iout is considered to be a continuous DC current step that changes rapidly at the clock pulse rate and is kept constant between clock pulses. The value of the current generated for each digital input bit is set using the variable resistor Rv. The variable resistor Rv is adjusted using a data word M, all set to logical 1, to generate a 1 volt output signal across resistor R1.
The signal Up is a unipolar DC voltage having a voltage value in the range between zero and 1 volt. A specific value is set by the value of the input data word M. Since the data word M has 5 bits, the output voltage signal Up has one of 32 possible values. However, since the signal M is assembled from two data words, the output voltage signal Up may be considered to have a feasible range of two DC values. For example, if input data bit D7 matches a logical 0, data bits D0-D3 may represent a DC voltage having 15 possible values. Similarly, if data bit D7 matches a logical one, data bits D3-D6 still have 15 possible values and represent a DC voltage with an offset in DC value. The fifteen possible values are actually superimposed on the value generated when data bit D7 is a logical one. When stationary, i.e., when there is no vertical displacement, data bit D7 is a logical 1 and data bits D3-D6 are a logical 0, which causes a direct current having a value of 0.5 volts. Voltage Up occurs. Unipolar DC voltage Up has a value in the first range when data bit D7 is logically low, and has a value in the second range when data bit D7 is logically high. Can be considered.
The unipolar voltage Up is coupled to the junction of the resistors R3, R4 and R7 of the drive amplifier 920 via the capacitor C1 so as to become an AC signal Bp. The resistors R3 and R4 are connected in series between the emitter terminal of the NPN transistor Q1 and the ground. Here, the resistor R4 is connected to the emitter, and the resistor R3 is grounded. The resistor R7 connects the junction point of the capacitor C1 and the resistors R3 and R4 to the base terminal of the NPN transistor Q3. The emitter terminal of the transistor Q3 is grounded via the resistor R8, and the collector terminal is connected to the junction point between the capacitor C3 and the collector terminal of the PNP transistor Q2.
The base terminal of transistor Q1 is connected to a bias network consisting of three diodes D1, D2 and D3 connected in series to ground. The anode of the diode D1 is connected to the base of the transistor Q1, and the cathode of the diode D1 is connected to the anode of the diode D2. The cathode of the diode D2 is connected to the anode of the diode D3, and the cathode is grounded. The base terminal of transistor Q1 is decoupled to ground by capacitor C2, and is further coupled to a +80 volt power supply via resistor R2. The collector terminal of the transistor Q1 is connected to a +80 volt power supply via a pair of resistors R5 and R6 connected in series. The resistor R5 is connected to the collector of the transistor Q1, and the resistor R6 is connected to the power source. The junction point of the resistor is connected to the base terminal of the transistor Q2. The emitter terminal of transistor Q2 is coupled to a +80 volt power supply via resistor R9. The collector junction of transistors Q2 and Q3 is biased to approximately half of the supply voltage by a voltage divider formed by resistors R10 and R11. Resistor R10 is connected to a +80 volt power supply and is connected in series with grounded resistor R11. Thus, the junction of the resistor is at a potential of about 40 volts applied to capacitor C3. In a static state, i.e., when there is no vertical displacement, both transistors are off, so a bias potential is required on the collectors of transistors Q2 and Q3. Without the bias, the potential on capacitor C3 is the collector leakage. It is determined by factors such as current.
Capacitor C3 couples the vertical displacement signal ΔV from transistors Q2 and Q3 to a complementary deflection stage 950. For example, the deflection stage 950 includes a winding pair Ly connected in series to the ground and coupled in parallel with the damping resistor R12. Winding Ly can be manufactured as a flexible coil adapted to the neck of the cathode ray tube to produce a complementary vertical deflection of the scanning electron beam.
FIG. 3A shows a complementary deflection winding Ly. FIG. 3B shows the adaptation of the winding Ly to modulate the vertical deflection field to the neck of the cathode ray tube and the position of the neck portion of the cathode ray tube. Each winding Ly is made of a 0.18 mm enameled copper wire wound 15 times. The two windings are connected in series and generate an inductance of 48 microhenries when placed under the deflection yoke. The winding has a 3 ohm DC resistance at 29kV EHT and a deflection sensitivity of 10-12.5mm / ampere.
In the drive amplifier 920, the pair of complementary transistors Q2 and Q3 operates as a current source to charge and discharge the coupling capacitor C3. Transistors Q2 and Q3 are biased by transistor Q1 to be essentially non-conductive. The base of transistor Q1 is biased to a positive potential of approximately 2.1 volts from a +80 volt power supply due to current flowing to ground through resistor R2 and series connected diodes D1, D2 and D3. . Thus, the emitter of transistor Q1 is at a potential of approximately 1.4 volts, and this value is divided by resistors R3 and R4 to generate approximately 0.7 volts at the base of transistor Q3. Since the resistor R3 is the same as the resistor R6 and the resistor R8 is the same as the resistor R9, the currents flowing through the transistors Q2 and Q3 have the same magnitude but opposite polarities. Since the base of transistor Q1 is decoupled to ground by capacitor C2, transistor Q1 functions as an in-phase or common base amplifier.
The coupling capacitor C1 has an advantage of removing a direct current component from the unipolar signal Up, and thereby obtaining an alternating current bipolar signal Bp. The alternating bipolar signal Bp is coupled to the base of the transistor Q3 via the resistor R7 and to the emitter of the transistor Q1 via the resistor R4. The bipolar signal Bp generated after the capacitor C1 represents the change in the value of the data word M coupled to the digital / analog converter U1. As described above, a change in the logical value of the data bit D7 causes a significant change or advance in the value of the signal Up, and hence the value of the AC signal Bp. The AC signal Bp is determined symmetrically with respect to the DC potential determined at the junction of the resistors R3 and R4. Thus, the positive deviation of signal Bp turns on transistor Q3, removing charge from capacitor C3 and statically biasing to 40 volts. Thus, by generating a current in the deflection stage, a complementary vertical deflection of the electron beam can be obtained. However, the positive excursion of signal Bp coupled to the emitter of transistor Q1 keeps transistor Q2 nonconductive. When signal Bp swings in the negative direction, transistor Q3 is no longer conducting and transistor Q1 is becoming more conductive, which turns on transistor Q2 and discharges capacitor C3. Therefore, opposite polarity currents are circulated through the deflection stage, which results in oppositely oriented vertical electron beam deflection. When the signal Up changes from 0.5 volts to 1 volt, a current of approximately 100 milliamperes flows through the transistor Q3, and when the signal Up changes from 0.5 volts to 0 volts, a current of approximately 100 milliamperes is generated at the transistor Q2. To do.
The drive circuit 900 provides a simplified drive amplifier that couples between the digital control signals D and S and a complementary deflection stage. The drive circuit 900 eliminates the need for a unipolar drive amplifier coupled to a directional switch controlled by a digital signal D in response to a conventional signal S. The digital control words D and S are advantageously combined as a digital word M that is converted to produce an analog signal Up having various values of unipolarity. The unipolar signal is coupled by a capacitor C1 that removes the DC component in the unipolar signal to generate an AC signal Bp. The alternating signal changes in a bipolar manner, ie oscillates in the positive and negative directions with respect to the bias potential in response to the data word M. The bias potential is such that the current source of the pair of complementary transistors is non-conductive in the quiescent state. A positive change in signal Bp turns on one current source that charges the electrostatic charge of the capacitor coupled to the deflection stage. Similarly, a negative change in signal Bp turns on the second current source and turns off the first current source, thereby creating an opposite current flow in the deflection coupling the capacitor. Thus, the drive amplifier 920 of the present invention obtains a bidirectional deflection current flow in the deflection winding in response to a unidirectional, unipolar control signal obtained from a digital signal by digital / analog conversion.

Claims (2)

A CRT using an interlaced scanning electron beam representing the raster;
Complementary vertical deflection means (950) for the electron beam;
A vertical digital compensation displacement of a magnitude related to the amplitude value of the display video signal connected to the display video signal source, detecting a flicker induced state in the display video signal and forming a blinking edge from the display video signal a signal (S), means for generating a de-digital direction signal (D) representing the direction required for the compensation of flicker and (200),
Having an input for receiving the vertical digital compensation displacement signal and said digital direction signal, means having an output for generating an analog compensation signal only unipolar (Up) having a range of first and second amplitude value (910 Wherein each of the amplitude value ranges represents a deflection direction of the electron beam ;
For deflecting the electron beam in a direction which is determined by the amount related to the by digital direction signal (D) and the vertical Digitally Le compensating displacement signal (S), the analog to該補complete specific vertical deflection means (950) Means for providing a compensation signal (920);
A video display device comprising: A CRT using an interlaced scanning electron beam representing the raster;
Complementary vertical deflection means (950) for the electron beam;
Means (200) for generating a digital signal (M) for complementary vertical deflection from the input signal in response to the input signal;
Receiving the digital signal and having only a single pole having a first amplitude value range representing a deflection in the first direction of the electron beam and a second amplitude value range representing a deflection in the opposite direction of the electron beam; Means 910 for generating an analog signal (Up) of
In response to the analog signal, for deflecting the electron beams in the vertical direction of the first or second in the first range or the second amplitude value Ji each response,該補complete specific vertical deflection means ( 950) driving means (920);
A video display device comprising:

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