JP3633412B2 - Battery pack control device and battery pack - Google Patents

Battery pack control device and battery pack Download PDF

Info

Publication number
JP3633412B2
JP3633412B2 JP37408499A JP37408499A JP3633412B2 JP 3633412 B2 JP3633412 B2 JP 3633412B2 JP 37408499 A JP37408499 A JP 37408499A JP 37408499 A JP37408499 A JP 37408499A JP 3633412 B2 JP3633412 B2 JP 3633412B2
Authority
JP
Japan
Prior art keywords
battery
voltage
secondary batteries
battery voltage
internal resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP37408499A
Other languages
Japanese (ja)
Other versions
JP2001190030A (en
Inventor
健司 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Kobe Electric Machinery Co Ltd
Original Assignee
Shin Kobe Electric Machinery Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Kobe Electric Machinery Co Ltd filed Critical Shin Kobe Electric Machinery Co Ltd
Priority to JP37408499A priority Critical patent/JP3633412B2/en
Publication of JP2001190030A publication Critical patent/JP2001190030A/en
Application granted granted Critical
Publication of JP3633412B2 publication Critical patent/JP3633412B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10Energy storage using batteries

Landscapes

  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Secondary Cells (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は組電池制御装置及びバッテリパックに係り、特に、複数個の二次電池を直列に接続した組電池を制御する組電池制御装置、並びに、該制御装置及び組電池を備えたバッテリパックに関する。
【0002】
【従来の技術】
例えば電気自動車等には、二次電池(単電池)を必要な容量に相当する分だけ複数個直列に接続した組電池が使用されている。このような組電池は、複数個の二次電池を用いるので、信頼性を確保することが重要である。すなわち、組電池を構成する二次電池のうちの何れかが過充電や過放電等によりその機能が低下すると、組電池全体としての機能も低下することになる。また、組電池を構成する各二次電池には製造時のバラツキがあり、更に、組電池として二次電池を使用した場合、温度分布が均一でないこと等により、充電受入性や放電容量が異なってくる。
【0003】
このため、放電深度0%(満充電)からの放電容量には各二次電池にバラツキが生じ、組電池としての放電容量が減少する。すなわち、放電時には放電容量の小さくなった二次電池は早く放電を終了して過放電状態となり、過放電となった二次電池が他の二次電池の負荷となって、すべての二次電池の放電深度が100%にならないうちに電圧が低下し、組電池としては放電終了となってしまう。逆に充電時には、放電時に放電深度100%にならなかった二次電池が先に放電深度0%に達して電圧が上昇し充電が終了してしまうが、放電時には過放電となった二次電池は放電深度0%にならないままで充電が終了するので、各二次電池の放電容量の差が広がる。従って、充放電を繰り返すと過放電となった二次電池は常に充電不足となるので、バラツキが大きくなって組電池全体としての放電容量が減少する。
【0004】
このように複数個の二次電池を直列に接続した組電池では、箇々の二次電池間にバラツキがあり、組電池全体として放電容量が低下するという問題や特定の二次電池が特に劣化するという問題があり、また過充電や過放電によって発熱する場合がある。
【0005】
上記問題に対処するために、組電池を構成する箇々の二次電池毎に電池電圧を検出する電圧検出手段を備え、検出した電圧が充電終止電圧になると充電を終了するようにしたものがある。また、組電池を構成する各二次電池毎に並列に電圧検出手段と二次電池を迂回して充電電流を流すためのバイパス回路とを設け、検出した電圧が充電終止電圧となった二次電池に対し、その二次電池のバイパス回路に充電電流をバイパスさせるようにしたものがある。
【0006】
【発明が解決しようとする課題】
しかし、前者においては、組電池を構成する複数の二次電池のうち充電終止電圧に達した二次電池があると充電を停止させるので、過充電になるおそれはなくなるが、各二次電池間のバラツキを解消させることはできない。また、後者においては、電池電圧によってのみ充電電流をバイパスさせているが、実際には、各二次電池間に内部抵抗のバラツキがあり、特に充電電流が大きい場合には各内部抵抗の差が小さくても、内部抵抗に依存して端子電圧が上昇し充電終止電圧に達するので、内部抵抗の小さい電池に対して高い充電状態が得られない。これは内部抵抗の大きい二次電池の充電状態にバラツキを生じさせ、各二次電池が一様に充分に充電されること、換言すれば、組電池全体がフル充電されることを阻害する。
【0007】
このように電池間にバラツキが生じた電池を充電するために、特開平第6−165399号公報には直列接続された電池の充電技術が開示されている。この技術によれば、直列接続された各二次電池の電圧を検出する電圧検出手段を有し、充電停止電圧になるとスイッチにより二次電池を迂回するバイパス回路が形成され、バイパス回路を介して他の二次電池に対して充電がなされる。
【0008】
しかしながら、上記公報の技術では、充電停止電圧に達した時点で充電が箇々に停止するので、直列接続された電池間で充電停止の時間が異なってくる。また、内部抵抗の高い電池は早く充電停止電圧に達するので、満充電となる前に充電が停止してしまう場合が生ずる。
【0009】
本発明は上記事案に鑑み、組電池を構成する二次電池の内部抵抗のバラツキに拘わらず、各二次電池を均等かつ充分に充電することができる組電池制御装置及びバッテリパックを提供することを課題とする。
【0010】
【課題を解決するための手段】
上記課題を解決するために、本発明は、複数個の二次電池を直列に接続した組電池を制御する組電池制御装置において、前記複数個の二次電池の各々の内部抵抗を検出する内部抵抗検出手段と、前記組電池の充放電状態を検出する状態検出手段と、前記複数個の二次電池の各々にスイッチを介して並列に接続され、抵抗値の異なる複数の直列接続された抵抗と、該複数の抵抗にそれぞれ並列に接続されたスイッチとを有し、前記スイッチをオン又はオフ状態として前記二次電池に流れる充電電流をバイパスさせる電池電圧バランス回路と、前記状態検出手段で検出された前記組電池の充放電状態と、前記内部抵抗検出手段で検出された前記二次電池の各々の内部抵抗値とに基づいて、前記二次電池の各々の電池電圧が等しくなるように前記電池電圧バランス回路のスイッチのオン、オフ条件を決定する制御手段と、を備え、前記制御手段は、充放電休止時に前記内部抵抗検出手段により検出された前記二次電池の各々の内部抵抗値の差から前記スイッチのオン、オフ条件を決定し、前記電池電圧バランス回路は前記制御手段により充放電休止時に決定されたスイッチのオン、オフ条件に従って次回充電時に前記二次電池の各々の電池電圧が等しくなるように前記二次電池に流れる充電電流をバイパスさせることを特徴とする。
【0011】
本発明では、複数個の二次電池の各々にスイッチを介して並列に接続され、抵抗値の異なる複数の直列接続された抵抗と、該複数の抵抗にそれぞれ並列に接続されたスイッチとを有し、スイッチをオン又はオフ状態として二次電池に流れる充電電流をバイパスさせる電池電圧バランス回路を備えている。状態検知手段により組電池の充放電状態が検出される。制御手段は、この状態検出手段で検出された充放電休止時に内部抵抗検出手段で検出された各二次電池の内部抵抗値の差から各二次電池の電池電圧が等しくなるように電池電圧バランス回路のスイッチのオン、オフ条件を決定し、電池電圧バランス回路は制御手段により充放電休止時に決定されたスイッチのオン、オフ条件に従って次回充電時に二次電池の各々の電池電圧が等しくなるように二次電池に流れる充電電流をバイパスさせる発明によれば、充放電休止時の各二次電池の内部抵抗にバラツキがあっても、このバラツキに応じて充電時に二次電池の充電電流をバイパスさせるので、二次電池各々を満充電となるまで充電することができ、組電池全体としての放電容量を高く維持することができると共に、電池電圧バランス回路は各二次電池の内部抵抗に応じてきめ細かく調整することができ二次電池間の電池電圧の均等性を高いレベルで確保することができる
【0012】
本発明において、各二次電池の電池電圧を均等とし電池電圧のバラツキを解消するために、二次電池の各々の電池電圧を検出する電池電圧検出手段を更に備え、制御手段が、次回充電時における二次電池の各々の電池電圧の差が予め定められた設定値以上のときに、電池電圧バランス回路に二次電池に流れる充放電電流のバイパスを許容するようにしてもよい。また、二次電池の各々の電池電圧を検出する電池電圧検出手段を更に備え、制御手段は、前回の充電時における二次電池の各々の電池電圧と次回充電時における二次電池の各々の電池電圧との差として表される電圧変化量が予め定められた設定値以上のときに、電池電圧バランス回路に二次電池に流れる充放電電流のバイパスを許容するようにしてもよい。
【0013】
た、電池電圧バランス回路を、制御基板上に分離して実装するようにすれば、大電流が流れる電池電圧バランス回路と微弱電流が流れる他の回路とは離隔されるので、ノイズによる組電池制御装置の誤作動を防止することができる。
【0014】
そして、上記態様の組電池制御装置及び組電池を備えてバッテリパックとすれば、特定の二次電池の劣化や組電池全体としての放電容量の低下、ノイズによる誤作動等のない、信頼性の高いバッテリパックを得ることができる。
【0015】
【発明の実施の形態】
以下、図面を参照して本発明が適用可能なバッテリパックの実施の形態について説明する。
【0016】
(構成)
図1に示すように、本実施形態のバッテリパック10は、複数個の二次電池としてのリチウムイオン電池(以下、単電池という。)51、52、・・・、5mが直列に接続された組電池5とこの組電池5を制御する組電池制御装置とで構成されている。
【0017】
組電池用制御装置はマイクロコンピュータ(以下、マイコンという。)1を備えている。マイコン1は演算処理を行うCPU、CPUが実行するプログラム及び後述する予め設定された差を表す所定値等を格納したROM、CPUのワークエリアとして働くRAM及び外部との入出力信号のポートとなる入出力インターフェース等を含んで構成されている。
【0018】
また、組電池制御装置は、単電池51のプラス側と組電池5のプラス端子との間に挿入され、組電池5の充電、放電又は休止状態を検出して組電池5の状態をマイコン1に出力する充放電判別部2を備えている。充放電判別部2は、例えば、シャント(分路)抵抗等により組電池5を流れる電流方向を検出し、組電池5が充電状態にあるときにはデフォルト値1、休止状態にあるときはデフォルト値0、放電状態にあるときはデフォルト値−1を、それぞれマイコン1へ出力する。
【0019】
更に、組電池制御装置は、単電池51、52、・・・、5mと各々並列に接続され、各単電池の充電電流等をバイパスさせるバランス回路31、32、・・・、3mを備えている。図2に示すように、バランス回路31は、マイコン1からの信号によりオン・オフ制御が可能なFETQ1〜Q5及び抵抗値がそれぞれR、2R、4R、8Rの4本のバイパス抵抗で構成されており、FETQ1を除き各バイパス抵抗がFETQ2〜Q5のソース・ドレイン間に挿入されている。なお、バランス回路32、・・・3mもバランス回路31と同一の回路構成である。
【0020】
また、図1に示すように、組電池制御装置は、各単電池51、52、・・・、5mに接続されこれらの単電池個々の電圧を検出してマイコン1に出力する電池電圧検出部4を備えている。電池電圧検出部4は、オペアンプ及び抵抗を有する複数の差動増幅回路を含んで構成されている。更に、組電池制御装置は、各単電池51、52、・・・、5mに接続されこれらの単電池個々の内部抵抗をマイコン1に出力する内部抵抗検出部6を備えている。内部抵抗検出部6は、例えば、インバータにより交流電流を発生させ、この交流電流を各単電池51、52、・・・、5m毎に通電して、その際の電圧値及び電流値を検出し、それらの値から内部抵抗を演算してマイコン1に出力する回路で構成することができる。なお、図1に示すバッテリパック10のプラス端子、単電池5mのマイナス側に接続されたマイナス端子は充電器又は負荷に接続される。
【0021】
図3に示すように、組電池制御装置は制御基板7に実装されている。制御基板7は、バランス回路31、32、・・・、3mが実装され大電流が流れるバランス回路実装部7Aと、このバランス回路実装部7Aから所定間隔隔てられ、バランス回路31、32、・・・、3m以外のマイコン1、充放電判別部2、電池電圧検出部4、内部抵抗検出部6が実装され微少信号電流が流れる検出・制御回路実装部7Bとに分けて実装・配線されている。また、バランス回路31、32、・・・、3mに接続されるリードをまとめるバイパス用コネクタ8とそれ以外に単電池51、52、・・・、5mに接続される検出・制御用リードの検出用コネクタ9とは制御基板7上で離隔されている。
【0022】
(動作)
次に、フローチャートを参照して本実施形態のバッテリパック10の動作について説明する。マイコン1に電源が投入されると、マイコン1のCPUはROMに格納されたプログラムに従って、RAMのワークエリアを初期化しROMに格納された所定値を読み出してRAMに移行する初期処理を行い、組電池制御処理ルーチンの実行を開始する。
【0023】
図4に示すように、この組電池制御処理ルーチンでは、まずステップST1で充放電判別部2からのデフォルト値を取り込んでRAMに格納し、次のステップST2において取り込んだデフォルト値から組電池5が休止状態か否かを判断する。肯定判断のときはステップST4で後述する休止処理サブルーチンを実行し、否定判断のときは次のステップST3で組電池5が充電状態か否かを判断する。ステップST3での判断が肯定のときは、次のステップST5において後述する充電処理サブルーチンを実行し、ステップST3での判断が否定のときは、ステップST6において各単電池51、52、・・・、5mが過放電状態にならないように監視する等の別処理が実行される。ステップST4、ST5又はST6での処理が終了すると、ステップST1に戻り、以上の組電池制御処理ルーチンが繰り返される。
【0024】
図5に示すように、休止処理サブルーチンでは、まずステップST41においてステップST1で格納した前回のデフォルト値と今回のデフォルト値とから組電池5が放電休止状態か否かを判断し、否定判断のときはステップST45へ進み、肯定判断のときはステップST42で各単電池51、52、・・・、5m毎の内部抵抗を内部抵抗検出部6に検出・出力させ、内部抵抗値を取り込む。なお、この内部抵抗値取込では、バランス回路31、32、・・・、3m、及び、電池電圧検出部4がそれぞれ単電池51、52、・・・、5mに並列に挿入されていることから、内部抵抗検出部6の内部抵抗検出に先だって、図2に示したFETQ1をオフとすると共に、電池電圧検出部4内の図示を省略した例えばFET等のスイッチ素子もオフとする。次にステップ43では、取り込んだ内部抵抗値に予め設定した差以上の差があるか否かを判断し、否定判断のときはステップST45へ進み、肯定判断のときは次のステップST44においてバイパス電流を設定してRAMに格納する。
【0025】
これらステップST43、ST44での処理についてより具体的に説明すれば、図7に示すように、例えば、3個の単電池A、B及びCを直列に接続した組電池を放電したときには、それぞれの内部抵抗は放電終了時に高くなる。そこで、単電池Aを次回充電時のバイパス電流を予め設定してこの設定されたバイパス電流に従って充電されるようにし(図6のST57参照)、内部抵抗差により充電時に電池電圧が早く上昇しないようにする。従って、ステップST43では、例えば、単電池Aの内部抵抗の差が他の単電池B又はCより5mΩ以上大きくなった場合に、次回充電時のバイパス電流を設定する。
【0026】
バイパス電流は、内部抵抗差と、充電電流によって設定される。例えば、充電電流が1A、内部抵抗差が5mΩとすると、内部抵抗差による電圧差は1A×5mΩ=5mVとなる。ステップST44では、この5mVの電圧上昇を抑えるように予測し、補正すべき単電池に対応するバランス回路3のバイパス抵抗のセット情報をRAMに記憶する。図2に示したように、バイパス抵抗値はマイコンからの出力信号によりFETで構成されるスイッチの切り替えで種々の値を採ることが可能であるので、バランス回路31、32、・・・、3mで調整可能なバイパス電流の電流値も種々の値を採ることができる。
【0027】
図5のステップST45では電池電圧検出部4から出力される各単電池51、52、・・・、5mの電圧値を取り込み、次のステップST46において各単電池51、52、・・・、5mの電圧値間に予め設定された差以上の差があるか否かを判断し、否定判断のときは休止処理サブルーチンを終了してステップST1へ戻り、肯定判断のときは次のステップST47において、バランス回路3のバイパス抵抗をセットして、各単電池51、52、・・・、5mの電圧値が等しくなるまで、開放電圧値の高い単電池を放電させ、休止処理サブルーチンを終了してステップST1へ戻る。
【0028】
図6に示すように、充電処理サブルーチンでは、まずステップST51で電池電圧検出部4から出力される各単電池51、52、・・・、5mの電圧値を取り込んでRAMに格納する。次に、ステップST52において取り込んだ各電池電圧値間に予め設定された差以上の差があるか否かを判断し、肯定判断のときはステップST57へ進み、否定判断のときは次のステップST53において電圧変化量を演算する。この電圧変化量演算では、前回RAMに格納した電池電圧値と今回RAMに格納した電池電圧値との差を演算する。次にステップST54では、ステップST53で演算した差が予め設定された差以上か否かを判断することにより、電池電圧変化量に有意差があるか否かを判定し、肯定判定のときはステップST57へ進み、否定判定のときはステップST55において、ステップST44でRAMに格納したバランス回路3のバイパス抵抗のセット情報を読み出して、次のステップ56においてバランス回路3によるバイパスが必要か否かをバイパス抵抗のセット情報から判断する。このステップST56での判断は、例えば、FETQ1のオン(例えば、1)・オフ(例えば、0)情報から判定することができる。ステップST56での判断が、否定のときは充電処理サブルーチンを終了してステップST1へ戻り、肯定のときはステップST57においてバランス回路3により充電電流の一部をバイパスさせ内部抵抗により生ずる電池電圧差をなくし各単電池を均等に満充電とさせ、充電処理サブルーチンを終了してステップST1へ戻る。
【0029】
(作用等)
本実施形態のバッテリパック10によれば、充電時に単電池51、52、・・・、5mの電圧差と電圧変化量差とが予め設定された差以上の差がある場合にバランス回路3により調整対象となる単電池の充電電流の一部をバイパスさせるようにしたので(ST51〜ST54、ST57)、単電池51、52、・・・、5mの電池電圧を均等にしバラツキをなくすことができることから、組電池を構成する単電池51、52、・・・、5mを満充電とすることができる。図8は2個の単電池C、Dを直列に接続し、本実施形態の組電池制御装置を用い充電したもの(実施例)と(図8(B)参照)、そうでないもの(比較例)と(図8(A)参照)を比較したものである。電圧差及び電圧変化量の差はそれぞれ40mV及び8mVとした。図8(A)(B)を比較して明らかなように、本実施形態の組電池制御装置を用いることにより、実施例の単電池C、D間の電池電圧(セル電圧)は均等となり、比較例の単電池C、Dの電池電圧には電圧差が維持されている。これは、図8(B)に示すように、実施例の単電池C、D間には電圧差40mV以上及び(/又は)電池電圧変化量差8mV以上があるので、単電池Cに並列に挿入されたバランス回路3が作動しバランス回路3にバイパス電流I1が流れる。この結果、電池Cの充電電流は(I−I1)となり単電池Dを流れる充電電流Iより減少するので、単電池Cの電池電圧V1は単電池Dの電池電圧V2に徐々に等しくなり満充電前に一致するためである。
【0030】
また、バッテリパック10によれば、充放電休止時に単電池51、52、・・・、5m間の電圧差が予め設定された差以上のときに電池電圧をバランス回路3により調整して開放電圧が等しくなるようにしたので(ST45〜ST47)、特定の単電池に負荷が集中して発熱したり劣化することを防止することができる。
【0031】
更に、バッテリパック10によれば、放電休止時に単電池51、52、・・・、5mの内部抵抗値を取り込んで予め設定された差以上の差があるときにバイパス電流値を設定するバイパス抵抗を決定し(ST42〜ST44)、次回充電時に設定された電流値をバランス回路3で充電電流の一部をバイパスするようにしたので(ST55〜ST57)、箇々の単電池51、52、・・・、5mを満充電となるまで均等に充電できると共に、組電池5の放電容量を高く維持することができる。
【0032】
そして、バッテリパック10によれば、制御基板7をバランス回路実装部7Aと検出・制御回路実装部7Bとに分けて信号回路とパワー回路とを分割し、また各単電池へのリードも大電流が流れるパワー線と、電圧検出等のための信号線(検出・制御用リード)をそれぞれ別にして、共通インピーダンスを作らないようにしたので、誤作動を生ずることが防止される。
【0033】
なお、本実施形態では、本発明を適用したバッテリパックの一例のみを示したが、本発明は本例に限定されることなく、上述した特許請求の範囲において種々の態様を採ることができることは論を待たない。
【0034】
【発明の効果】
以上説明したように、本発明によれば、充放電休止時の各二次電池の内部抵抗にバラツキがあっても、このバラツキに応じて充電時に二次電池の充電電流をバイパスさせるので、二次電池各々を満充電となるまで充電することができ、組電池全体としての放電容量を高く維持することができると共に、電池電圧バランス回路は各二次電池の内部抵抗に応じてきめ細かく調整することができ二次電池間の電池電圧の均等性を高いレベルで確保することができる、という効果をえることができる。
【0035】
また、第2態様によれば、放電終了時の各二次電池の内部抵抗にバラツキがあっても、このバラツキに応じて充電時に二次電池の充電電流をバイパスさせるので、二次電池各々を満充電となるまで充電することができ、組電池全体としての放電容量を高く維持することができる、という効果を得ることができる。
【0036】
更に、第3態様によれば、各二次電池の内部抵抗及び充電電流の違いにより放電休止時の開放電池電圧にバラツキが生ずる場合でも、開放電池電圧を等しくすることができるので、特定の二次電池が負荷となったり発熱・劣化したりすることを防止することができる、という効果を得ることができる。
【図面の簡単な説明】
【図1】本発明が適用可能な実施形態のバッテリパックのブロック回路図である。
【図2】実施形態のバッテリパックのバランス回路の回路図である。
【図3】実施形態のバッテリパックの制御基板を模式的に示す実装図である。
【図4】実施形態のバッテリパックの組電池制御処理ルーチンを示すフローチャートである。
【図5】組電池制御処理ルーチンのステップST4の休止処理サブルーチンの詳細を示すフローチャートである。
【図6】組電池制御処理ルーチンのステップST5の充電処理サブルーチンの詳細を示すフローチャートである。
【図7】単電池3個を直列に接続したときの各電池の内部抵抗値を示すグラフである。
【図8】単電池2個を直列に接続したときの充電時間に対するセル電圧、充電電流の関係を示すグラフであり、(A)はバランス回路を有しない比較例のバッテリパックの試験結果であり、(B)はバランス回路を有する実施例のバッテリパックの試験結果である。
【符号の説明】
1 マイコン(制御手段
2 充放電判別部(状態検出手段)
31…3m バランス回路(電池電圧バランス回路)
4 電池電圧検出部(電池電圧検出手段)
5 組電池
51…5m 単電池(二次電池)
6 内部抵抗検出部(内部抵抗検出手段)
7 制御基板
7A バランス回路実装部
10 バッテリパック
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an assembled battery control device and a battery pack, and more particularly to an assembled battery control device that controls an assembled battery in which a plurality of secondary batteries are connected in series, and a battery pack including the control device and the assembled battery. .
[0002]
[Prior art]
For example, in an electric vehicle or the like, an assembled battery in which a plurality of secondary batteries (single batteries) are connected in series corresponding to a required capacity is used. Since such an assembled battery uses a plurality of secondary batteries, it is important to ensure reliability. That is, when any of the secondary batteries constituting the assembled battery has its function lowered due to overcharge or overdischarge, the function of the assembled battery as a whole is also lowered. In addition, each secondary battery constituting the assembled battery has variations at the time of manufacture, and when a secondary battery is used as the assembled battery, the charge acceptance and discharge capacity are different due to non-uniform temperature distribution etc. Come.
[0003]
For this reason, the discharge capacity from a discharge depth of 0% (full charge) varies in each secondary battery, and the discharge capacity as an assembled battery decreases. That is, at the time of discharging, the secondary battery having a small discharge capacity ends discharging quickly and becomes overdischarged, and the secondary battery that has become overdischarged becomes the load of other secondary batteries, and all the secondary batteries Before the depth of discharge reaches 100%, the voltage drops, and the assembled battery ends discharging. Conversely, when charging, the secondary battery that did not reach the discharge depth of 100% at the time of discharge first reaches the discharge depth of 0%, the voltage rises and the charging ends, but the secondary battery that is overdischarged at the time of discharge. Since the charging ends without reaching the discharge depth of 0%, the difference in the discharge capacity of each secondary battery widens. Therefore, if charging / discharging is repeated, the overcharged secondary battery is always insufficiently charged, so that the variation becomes large and the discharge capacity of the assembled battery as a whole decreases.
[0004]
In the assembled battery in which a plurality of secondary batteries are connected in series in this way, there are variations between the secondary batteries, and the problem that the discharge capacity is reduced as a whole assembled battery and the particular secondary battery is particularly deteriorated. In addition, there is a case where heat is generated due to overcharge or overdischarge.
[0005]
In order to deal with the above problem, there is a voltage detection means for detecting the battery voltage for each secondary battery constituting the assembled battery, and charging is terminated when the detected voltage reaches the charge end voltage. . In addition, for each secondary battery constituting the assembled battery, a voltage detection means and a bypass circuit for bypassing the secondary battery to flow the charging current are provided in parallel, and the detected voltage becomes the charge end voltage. Some batteries have a secondary battery bypass circuit that bypasses the charging current.
[0006]
[Problems to be solved by the invention]
However, in the former case, if there is a secondary battery that has reached the end-of-charge voltage among a plurality of secondary batteries constituting the assembled battery, charging is stopped, so there is no risk of overcharging. This variation cannot be eliminated. In the latter case, the charging current is bypassed only by the battery voltage. However, in reality, there is a variation in the internal resistance between the secondary batteries. Even if it is small, the terminal voltage increases depending on the internal resistance and reaches the end-of-charge voltage, so that a high charge state cannot be obtained for a battery having a low internal resistance. This causes variations in the charged state of the secondary battery having a large internal resistance, and inhibits each secondary battery from being fully and uniformly charged, in other words, preventing the entire assembled battery from being fully charged.
[0007]
In order to charge a battery in which variations occur between the batteries as described above, Japanese Patent Application Laid-Open No. 6-165399 discloses a charging technique for batteries connected in series. According to this technology, there is a voltage detection means for detecting the voltage of each secondary battery connected in series, and when the charge stop voltage is reached, a bypass circuit that bypasses the secondary battery is formed by a switch, The other secondary battery is charged.
[0008]
However, in the technique of the above publication, since charging is stopped at every point when the charging stop voltage is reached, the time for stopping charging differs among batteries connected in series. In addition, since a battery having a high internal resistance quickly reaches the charge stop voltage, charging may stop before the battery is fully charged.
[0009]
In view of the above-described case, the present invention provides an assembled battery control device and a battery pack that can charge each secondary battery equally and sufficiently regardless of variations in internal resistance of the secondary batteries constituting the assembled battery. Is an issue.
[0010]
[Means for Solving the Problems]
In order to solve the above problems, the present onset Ming, the battery pack controller for controlling an assembled battery obtained by connecting a plurality of secondary batteries in series, to detect the internal resistance of each of the plurality of secondary batteries Internal resistance detection means, state detection means for detecting the charge / discharge state of the assembled battery, and a plurality of secondary batteries connected in parallel via a switch, and connected in series with a plurality of resistance values A battery voltage balance circuit that includes a resistor and a switch connected in parallel to each of the plurality of resistors, and bypasses a charging current flowing through the secondary battery by turning the switch on or off, and the state detection unit. Based on the detected charge / discharge state of the assembled battery and the internal resistance value of each of the secondary batteries detected by the internal resistance detecting means, the battery voltages of the secondary batteries are made equal. The power Control means for determining ON / OFF conditions of the switch of the voltage balance circuit, and the control means is a difference in internal resistance value of each of the secondary batteries detected by the internal resistance detection means during charging / discharging suspension. The on / off condition of the switch is determined from the battery voltage balance circuit, and the battery voltage of each of the secondary batteries is equal at the next charging according to the on / off condition of the switch determined by the control means when charging / discharging is stopped. Thus, the charging current flowing in the secondary battery is bypassed.
[0011]
In the present invention, each of the plurality of secondary batteries is connected in parallel through a switch, and has a plurality of series-connected resistors having different resistance values, and a switch connected in parallel to each of the plurality of resistors. And a battery voltage balance circuit that bypasses the charging current flowing through the secondary battery by turning the switch on or off. The state detection means detects the charge / discharge state of the assembled battery. The control means balances the battery voltage so that the battery voltage of each secondary battery becomes equal from the difference in the internal resistance value of each secondary battery detected by the internal resistance detection means during the charging / discharging pause detected by this state detection means. The battery voltage balance circuit determines that the battery voltage of each of the secondary batteries is equal at the next charging according to the switch on / off condition determined during charging / discharging suspension by the control means. The charging current flowing in the secondary battery is bypassed . According to the present invention , even if there is a variation in the internal resistance of each secondary battery during charging / discharging suspension , the charging current of the secondary battery is bypassed during charging according to this variation, so that each secondary battery is fully charged. Can be charged, and the discharge capacity of the assembled battery as a whole can be kept high , and the battery voltage balance circuit can be finely adjusted according to the internal resistance of each secondary battery. The battery voltage uniformity can be ensured at a high level .
[0012]
In the present invention, in order to equalize the battery voltage of each secondary battery and eliminate the variation in battery voltage, the battery further includes a battery voltage detection means for detecting each battery voltage of the secondary battery, and the control means is used for the next charging. When the difference between the battery voltages of the secondary batteries is equal to or greater than a predetermined set value, the battery voltage balance circuit may be allowed to bypass the charge / discharge current flowing through the secondary battery. In addition, the battery voltage detecting means for detecting the battery voltage of each of the secondary batteries is further provided, and the control means includes the battery voltage of each of the secondary batteries at the previous charging time and each of the secondary batteries at the next charging time. When the voltage change amount expressed as a difference from the voltage is equal to or larger than a predetermined set value, the battery voltage balance circuit may be allowed to bypass the charge / discharge current flowing through the secondary battery.
[0013]
The Also, the battery voltage balance circuit, if to implement separated on a control board, since the other circuit battery voltage balance circuit and weak current which a large current flows through are separated, the battery pack due to noise It is possible to prevent malfunction of the control device.
[0014]
If the battery pack is provided with the assembled battery control device and the assembled battery of the above aspect, the reliability of the secondary battery is not deteriorated, the discharge capacity of the assembled battery as a whole is reduced, the malfunction is not caused by noise, and the like. A high battery pack can be obtained.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of a battery pack to which the present invention can be applied will be described with reference to the drawings.
[0016]
(Constitution)
As shown in FIG. 1, in the battery pack 10 of this embodiment, a plurality of lithium ion batteries (hereinafter referred to as single cells) 51, 52,..., 5m as secondary batteries are connected in series. The battery pack 5 includes a battery pack 5 and a battery pack controller that controls the battery pack 5.
[0017]
The battery pack control device includes a microcomputer (hereinafter referred to as a microcomputer) 1. The microcomputer 1 is a CPU that performs arithmetic processing, a program that is executed by the CPU, a ROM that stores predetermined values that represent preset differences, which will be described later, a RAM that serves as a work area for the CPU, and an input / output signal port to the outside. It includes an input / output interface and the like.
[0018]
The assembled battery control device is inserted between the plus side of the unit cell 51 and the plus terminal of the assembled battery 5, detects the charging, discharging, or resting state of the assembled battery 5 and changes the state of the assembled battery 5 to the microcomputer 1. The charging / discharging discrimination | determination part 2 output to is provided. The charge / discharge discriminating unit 2 detects the direction of the current flowing through the assembled battery 5 using, for example, a shunt (shunt) resistance, and the like. When the assembled battery 5 is in a charged state, the default value is 1; When in a discharging state, the default value -1 is output to the microcomputer 1 respectively.
[0019]
Further, the battery pack control device includes balance circuits 31, 32,..., 3m that are connected in parallel to the single cells 51, 52,. Yes. As shown in FIG. 2, the balance circuit 31 includes FETs Q <b> 1 to Q <b> 5 that can be turned on / off by a signal from the microcomputer 1 and four bypass resistors whose resistance values are R, 2R, 4R, and 8R, respectively. Each bypass resistor except for the FET Q1 is inserted between the source and drain of the FETs Q2 to Q5. The balance circuit 32,..., 3m has the same circuit configuration as the balance circuit 31.
[0020]
As shown in FIG. 1, the battery pack control device is connected to each single cell 51, 52,..., 5 m and detects the voltage of each single cell and outputs it to the microcomputer 1. 4 is provided. The battery voltage detection unit 4 includes a plurality of differential amplifier circuits having operational amplifiers and resistors. Further, the battery pack control device includes an internal resistance detection unit 6 that is connected to each of the single cells 51, 52,..., 5m and outputs the internal resistance of each single cell to the microcomputer 1. The internal resistance detector 6 generates an alternating current by, for example, an inverter, energizes the alternating current for each unit cell 51, 52,..., 5m, and detects a voltage value and a current value at that time. The circuit can calculate the internal resistance from these values and output it to the microcomputer 1. The positive terminal of the battery pack 10 shown in FIG. 1 and the negative terminal connected to the negative side of the unit cell 5m are connected to a charger or a load.
[0021]
As shown in FIG. 3, the assembled battery control device is mounted on the control board 7. The control board 7 has a balance circuit mounting portion 7A on which the balance circuits 31, 32,..., 3m are mounted and a large current flows, and a predetermined distance from the balance circuit mounting portion 7A. -The microcomputer 1 other than 3 m, the charge / discharge discriminator 2, the battery voltage detector 4, and the internal resistance detector 6 are mounted and wired separately to the detection / control circuit mounting portion 7B through which a minute signal current flows. . Further, the bypass connector 8 that collects leads connected to the balance circuits 31, 32,..., 3m, and the detection / control leads connected to the single cells 51, 52,. The connector 9 is separated on the control board 7.
[0022]
(Operation)
Next, the operation of the battery pack 10 of this embodiment will be described with reference to a flowchart. When the microcomputer 1 is turned on, the CPU of the microcomputer 1 initializes the RAM work area according to a program stored in the ROM, reads a predetermined value stored in the ROM, and performs an initial process for transferring to the RAM. The execution of the battery control processing routine is started.
[0023]
As shown in FIG. 4, in this assembled battery control processing routine, first, in step ST1, the default value from the charge / discharge determination unit 2 is fetched and stored in the RAM, and the assembled battery 5 is loaded from the default value fetched in the next step ST2. It is determined whether or not it is in a dormant state. If the determination is affirmative, a suspension processing subroutine, which will be described later, is executed in step ST4. If the determination is negative, whether or not the assembled battery 5 is in a charged state is determined in the next step ST3. When the determination at step ST3 is affirmative, a charge processing subroutine described later is executed at the next step ST5, and when the determination at step ST3 is negative, the single cells 51, 52,. Another process such as monitoring so that 5 m is not overdischarged is executed. When the process in step ST4, ST5 or ST6 ends, the process returns to step ST1 and the above assembled battery control process routine is repeated.
[0024]
As shown in FIG. 5, in the suspension processing subroutine, first, in step ST41, it is determined whether or not the assembled battery 5 is in a discharge suspension state from the previous default value and the current default value stored in step ST1, and when negative determination is made. Advances to step ST45, and when an affirmative determination is made, in step ST42, the internal resistance of each of the cells 51, 52,... In addition, in this internal resistance value taking-in, the balance circuits 31, 32,..., 3m and the battery voltage detection unit 4 are inserted in parallel to the single cells 51, 52,. Therefore, prior to the detection of the internal resistance of the internal resistance detector 6, the FET Q1 shown in FIG. 2 is turned off, and the switch element such as an FET (not shown) in the battery voltage detector 4 is also turned off. Next, in step 43, it is determined whether or not the captured internal resistance value has a difference greater than a preset difference. If the determination is negative, the process proceeds to step ST45. If the determination is affirmative, the bypass current is determined in the next step ST44. Is stored in the RAM.
[0025]
More specifically, the processing in these steps ST43 and ST44 will be described. As shown in FIG. 7, for example, when an assembled battery in which three unit cells A, B and C are connected in series is discharged, The internal resistance becomes high at the end of discharge. Therefore, the cell A is charged in accordance with the set bypass current in advance by setting a bypass current at the next charging (see ST57 in FIG. 6), so that the battery voltage does not rise quickly during charging due to the internal resistance difference. To. Therefore, in step ST43, for example, when the difference in internal resistance of the single battery A is 5 mΩ or more larger than that of the other single battery B or C, the bypass current for the next charge is set.
[0026]
The bypass current is set by the internal resistance difference and the charging current. For example, if the charging current is 1 A and the internal resistance difference is 5 mΩ, the voltage difference due to the internal resistance difference is 1 A × 5 mΩ = 5 mV. In step ST44, it is predicted that the voltage increase of 5 mV is suppressed, and the bypass resistor set information of the balance circuit 3 corresponding to the unit cell to be corrected is stored in the RAM. As shown in FIG. 2, since the bypass resistance value can take various values by switching the switch composed of FETs according to the output signal from the microcomputer, the balance circuits 31, 32,..., 3m The current value of the bypass current that can be adjusted with can also take various values.
[0027]
In step ST45 of FIG. 5, the voltage values of the individual cells 51, 52,..., 5m output from the battery voltage detector 4 are captured, and in the next step ST46, the individual cells 51, 52,. It is determined whether or not there is a difference greater than or equal to a preset difference between the voltage values. When a negative determination is made, the pause processing subroutine is terminated and the process returns to step ST1. When an affirmative determination is made, in the next step ST47, The bypass resistor of the balance circuit 3 is set, and the cells having a high open-circuit voltage value are discharged until the voltage values of the respective cells 51, 52,... Return to ST1.
[0028]
As shown in FIG. 6, in the charging process subroutine, first, in step ST51, the voltage values of the individual cells 51, 52,..., 5m output from the battery voltage detection unit 4 are captured and stored in the RAM. Next, it is determined whether or not there is a difference greater than a preset difference between the battery voltage values captured in step ST52. If the determination is affirmative, the process proceeds to step ST57. If the determination is negative, the next step ST53 is performed. The voltage change amount is calculated at. In this voltage change amount calculation, the difference between the battery voltage value stored in the previous RAM and the battery voltage value stored in the current RAM is calculated. Next, in step ST54, it is determined whether or not there is a significant difference in the battery voltage change amount by determining whether or not the difference calculated in step ST53 is greater than or equal to a preset difference. The process proceeds to ST57, and in the case of negative determination, in step ST55, the set information of the bypass resistor of the balance circuit 3 stored in the RAM in step ST44 is read, and whether or not bypass by the balance circuit 3 is necessary is bypassed in the next step 56 Judgment from resistance set information. The determination at this step ST56 can be made from, for example, on (eg, 1) / off (eg, 0) information of the FET Q1. If the determination in step ST56 is negative, the charging process subroutine is terminated and the process returns to step ST1. If the determination is positive, in step ST57, a part of the charging current is bypassed by the balance circuit 3 and the battery voltage difference caused by the internal resistance is determined. All the cells are completely charged fully, the charging process subroutine is terminated, and the process returns to step ST1.
[0029]
(Action etc.)
According to the battery pack 10 of the present embodiment, the balance circuit 3 causes the voltage difference between the single cells 51, 52,..., 5m and the voltage change amount difference to be greater than or equal to a preset difference during charging. Since part of the charging current of the unit cell to be adjusted is bypassed (ST51 to ST54, ST57), the cell voltages of the unit cells 51, 52,... Therefore, the single cells 51, 52,..., 5m constituting the assembled battery can be fully charged. In FIG. 8, two unit cells C and D are connected in series and charged using the battery pack control device of this embodiment (Example) (see FIG. 8B), and not (Comparative Example). ) And (see FIG. 8A). The difference between the voltage difference and the voltage change amount was 40 mV and 8 mV, respectively. As is clear by comparing FIGS. 8A and 8B, the battery voltage (cell voltage) between the single cells C and D of the example is equalized by using the assembled battery control device of this embodiment. A voltage difference is maintained between the battery voltages of the cells C and D of the comparative example. This is because, as shown in FIG. 8B, there is a voltage difference of 40 mV or more and / or a battery voltage change amount difference of 8 mV or more between the unit cells C and D of the embodiment. The inserted balance circuit 3 operates and a bypass current I1 flows through the balance circuit 3. As a result, the charging current of the battery C becomes (I-I1) and decreases from the charging current I flowing through the cell D, so that the battery voltage V1 of the cell C gradually becomes equal to the battery voltage V2 of the cell D and fully charged. This is because it matches before.
[0030]
Moreover, according to the battery pack 10, when the voltage difference between the single cells 51, 52,... Are equal (ST45 to ST47), it is possible to prevent the load from concentrating on a specific unit cell to generate heat or deteriorate.
[0031]
Furthermore, according to the battery pack 10, the bypass resistance that sets the bypass current value when the internal resistance value of the single cells 51, 52,... (ST42 to ST44), and the current value set at the next charging is bypassed by a part of the charging current by the balance circuit 3 (ST55 to ST57), so that the single cells 51, 52,. -5 m can be charged evenly until it is fully charged, and the discharge capacity of the assembled battery 5 can be kept high.
[0032]
According to the battery pack 10, the control circuit board 7 is divided into the balance circuit mounting portion 7A and the detection / control circuit mounting portion 7B to divide the signal circuit and the power circuit. Since a power line through which the current flows and a signal line (detection / control lead) for voltage detection and the like are separated from each other so as not to create a common impedance, it is possible to prevent malfunction.
[0033]
In the present embodiment, only one example of the battery pack to which the present invention is applied is shown. However, the present invention is not limited to the present example, and various aspects can be adopted in the above-described claims. Don't wait for the argument.
[0034]
【The invention's effect】
As described above, according to this onset bright, even if there are variations in the internal resistance of the secondary battery during charge and discharge quiescent, so to bypass charging current of the secondary battery during charging in accordance with this variation, Each secondary battery can be charged until it is fully charged, the discharge capacity of the assembled battery as a whole can be maintained high, and the battery voltage balance circuit is finely adjusted according to the internal resistance of each secondary battery. Therefore, it is possible to obtain the effect that the uniformity of the battery voltage between the secondary batteries can be secured at a high level .
[0035]
Further, according to the second aspect, even if there is a variation in the internal resistance of each secondary battery at the end of the discharge, the charging current of the secondary battery is bypassed during charging according to this variation. The battery can be charged until it is fully charged, and the effect that the discharge capacity of the assembled battery as a whole can be maintained high can be obtained.
[0036]
Furthermore, according to the third aspect, the open battery voltage can be made equal even when there is a variation in the open battery voltage during the discharge pause due to the difference in internal resistance and charging current of each secondary battery. It is possible to obtain an effect that the secondary battery can be prevented from becoming a load, heat generation and deterioration.
[Brief description of the drawings]
FIG. 1 is a block circuit diagram of a battery pack according to an embodiment to which the present invention is applicable.
FIG. 2 is a circuit diagram of a balance circuit of the battery pack according to the embodiment.
FIG. 3 is a mounting diagram schematically showing a control board of the battery pack of the embodiment.
FIG. 4 is a flowchart showing an assembled battery control processing routine of the battery pack according to the embodiment.
FIG. 5 is a flowchart showing details of a suspension processing subroutine of step ST4 of the assembled battery control processing routine.
FIG. 6 is a flowchart showing details of a charging processing subroutine of step ST5 of the assembled battery control processing routine.
FIG. 7 is a graph showing the internal resistance value of each battery when three unit cells are connected in series.
FIG. 8 is a graph showing the relationship between the cell voltage and the charging current with respect to the charging time when two single cells are connected in series, and (A) is a test result of a comparative battery pack having no balance circuit. , (B) are test results of the battery pack of the example having a balance circuit.
[Explanation of symbols]
1 Microcomputer ( control means )
2 Charging / discharging discrimination unit (state detection means)
31 ... 3m balance circuit (battery voltage balance circuit)
4 Battery voltage detector (battery voltage detection means)
5 batteries 51 ... 5m single battery (secondary battery)
6 Internal resistance detector (internal resistance detector)
7 Control board 7A Balance circuit mounting part 10 Battery pack

Claims (6)

複数個の二次電池を直列に接続した組電池を制御する組電池制御装置において、
前記複数個の二次電池の各々の内部抵抗を検出する内部抵抗検出手段と、
前記組電池の充放電状態を検出する状態検出手段と、
前記複数個の二次電池の各々にスイッチを介して並列に接続され、抵抗値の異なる複数の直列接続された抵抗と、該複数の抵抗にそれぞれ並列に接続されたスイッチとを有し、前記スイッチをオン又はオフ状態として前記二次電池に流れる充電電流をバイパスさせる電池電圧バランス回路と、
前記状態検出手段で検出された前記組電池の充放電状態と、前記内部抵抗検出手段で検出された前記二次電池の各々の内部抵抗値とに基づいて、前記二次電池の各々の電池電圧が等しくなるように前記電池電圧バランス回路のスイッチのオン、オフ条件を決定する制御手段と、
を備え、前記制御手段は、充放電休止時に前記内部抵抗検出手段により検出された前記二次電池の各々の内部抵抗値の差から前記スイッチのオン、オフ条件を決定し、前記電池電圧バランス回路は前記制御手段により充放電休止時に決定されたスイッチのオン、オフ条件に従って次回充電時に前記二次電池の各々の電池電圧が等しくなるように前記二次電池に流れる充電電流をバイパスさせることを特徴とする組電池制御装置。
In an assembled battery control device for controlling an assembled battery in which a plurality of secondary batteries are connected in series,
Internal resistance detecting means for detecting internal resistance of each of the plurality of secondary batteries;
State detecting means for detecting a charge / discharge state of the assembled battery;
Each of the plurality of secondary batteries is connected in parallel via a switch, and has a plurality of series-connected resistors having different resistance values, and a switch connected in parallel to each of the plurality of resistors, A battery voltage balance circuit that bypasses the charging current flowing through the secondary battery with the switch turned on or off ; and
Based on the charge / discharge state of the assembled battery detected by the state detection means and the internal resistance value of each of the secondary batteries detected by the internal resistance detection means, the battery voltage of each of the secondary batteries Control means for determining the on / off condition of the switch of the battery voltage balance circuit so that
The control means determines an on / off condition of the switch from a difference in internal resistance value of each of the secondary batteries detected by the internal resistance detection means during charge / discharge suspension, and the battery voltage balance circuit Is characterized in that the charging current flowing through the secondary battery is bypassed so that the battery voltage of each of the secondary batteries becomes equal at the next charging according to the on / off condition of the switch determined by the control means when charging / discharging is stopped. An assembled battery control device.
前記二次電池の各々の電池電圧を検出する電池電圧検出手段を更に備え、前記制御手段は、前記次回充電時における前記二次電池の各々の電池電圧の差が予め定められた設定値以上のときに、前記電池電圧バランス回路に前記二次電池に流れる充放電電流のバイパスを許容することを特徴とする請求項1に記載の組電池制御回路。Battery voltage detection means for detecting the battery voltage of each of the secondary batteries is further provided, and the control means is configured such that a difference between the battery voltages of the secondary batteries at the next charging is equal to or greater than a predetermined set value. 2. The assembled battery control circuit according to claim 1, wherein the battery voltage balance circuit is allowed to bypass a charge / discharge current flowing through the secondary battery. 3. 前記二次電池の各々の電池電圧を検出する電池電圧検出手段を更に備え、前記制御手段は、前回の充電時における前記二次電池の各々の電池電圧と前記次回充電時における前記二次電池の各々の電池電圧との差として表される電圧変化量が予め定められた設定値以上のときに、前記電池電圧バランス回路に前記二次電池に流れる充放電電流のバイパスを許容することを特徴とする請求項1に記載の組電池制御回路。Battery voltage detection means for detecting the battery voltage of each of the secondary batteries is further provided, and the control means includes the battery voltage of each of the secondary batteries at the previous charging time and the voltage of the secondary battery at the next charging time. When the amount of voltage change expressed as a difference from each battery voltage is equal to or greater than a predetermined set value, the battery voltage balance circuit is allowed to bypass a charge / discharge current flowing through the secondary battery. The assembled battery control circuit according to claim 1. 前記制御回路は前記スイッチのオン、オフ条件を記憶するメモリを有することを特徴とする請求項1乃至請求項3のいずれか1項に記載の組電池制御回路。4. The assembled battery control circuit according to claim 1, wherein the control circuit includes a memory that stores an on / off condition of the switch. 5. 前記電池電圧バランス回路は、制御基板上に分離されて実装されことを特徴とする請求項1乃至請求項4のいずれか1項に記載の組電池制御装置。The battery voltage balance circuit, the battery pack controlling apparatus according to any one of claims 1 to 4, characterized in that it is mounted to be separated on a control board. 請求項1乃至請求項6のいずれか1項に記載の組電池制御装置及び組電池を備えたことを特徴とするバッテリパック。A battery pack comprising the assembled battery control device and the assembled battery according to any one of claims 1 to 6.
JP37408499A 1999-12-28 1999-12-28 Battery pack control device and battery pack Expired - Fee Related JP3633412B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP37408499A JP3633412B2 (en) 1999-12-28 1999-12-28 Battery pack control device and battery pack

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP37408499A JP3633412B2 (en) 1999-12-28 1999-12-28 Battery pack control device and battery pack

Publications (2)

Publication Number Publication Date
JP2001190030A JP2001190030A (en) 2001-07-10
JP3633412B2 true JP3633412B2 (en) 2005-03-30

Family

ID=18503234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP37408499A Expired - Fee Related JP3633412B2 (en) 1999-12-28 1999-12-28 Battery pack control device and battery pack

Country Status (1)

Country Link
JP (1) JP3633412B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8120319B2 (en) 2006-12-14 2012-02-21 Panasonic Corporation Set battery control method and set battery control circuit as well as charging circuit and battery pack having the set battery control circuit

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7198866B2 (en) 2002-07-09 2007-04-03 Nissan Motor Co., Ltd. Cell assembly
JP4448111B2 (en) * 2006-07-31 2010-04-07 日立ビークルエナジー株式会社 Power system
US7782013B2 (en) * 2007-04-17 2010-08-24 Chun-Chieh Chang Rechargeable battery assembly and method for recharging same
JP5131533B2 (en) * 2008-03-25 2013-01-30 マツダ株式会社 Battery charge / discharge control method and charge / discharge control apparatus
JP5022316B2 (en) * 2008-07-04 2012-09-12 本田技研工業株式会社 Secondary battery device
KR100995816B1 (en) 2008-07-15 2010-11-23 엘에스엠트론 주식회사 Energy storage device module
JP5955507B2 (en) * 2011-02-14 2016-07-20 トヨタ自動車株式会社 Voltage detection circuit and voltage detection device for power storage device, and vehicle equipped with the same
WO2013128834A1 (en) * 2012-02-28 2013-09-06 日本電気株式会社 Storage battery device, storage battery control device, and storage battery control method
US8901888B1 (en) 2013-07-16 2014-12-02 Christopher V. Beckman Batteries for optimizing output and charge balance with adjustable, exportable and addressable characteristics

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8120319B2 (en) 2006-12-14 2012-02-21 Panasonic Corporation Set battery control method and set battery control circuit as well as charging circuit and battery pack having the set battery control circuit

Also Published As

Publication number Publication date
JP2001190030A (en) 2001-07-10

Similar Documents

Publication Publication Date Title
US6850041B2 (en) Battery pack used as power source for portable device
US7408325B2 (en) Battery charging method
US6271645B1 (en) Method for balancing battery pack energy levels
US9438059B2 (en) Battery control apparatus and battery control method
JP3676134B2 (en) Charge / discharge control method
EP2418751B1 (en) Battery charger and battery charging method
JP2000092732A (en) Method for judging scattering of battery pack and battery device
JP7199021B2 (en) Management device, power storage system
JPH1032936A (en) Control system and method for power supply
JP4542675B2 (en) Voltage correction device for battery pack for electric vehicle
JP3797254B2 (en) Secondary battery capacity adjustment method
JP3633412B2 (en) Battery pack control device and battery pack
JP3669234B2 (en) Charge control device for battery pack
JP3610823B2 (en) Module battery control device, module battery unit, and module battery control method
JP4738730B2 (en) Battery pack and battery pack
JP4129109B2 (en) Charge control apparatus and method
JP2003257501A (en) Secondary battery residual capacity meter
JPH104636A (en) Method for charging lithium cell
JPH09200968A (en) Charge controller for battery set
JP3458740B2 (en) Battery charging and discharging devices
JPH1155866A (en) Battery charger
JPH09308126A (en) Charger
JP2003061254A (en) Voltage detector for battery pack
KR20220141599A (en) Method for equalizing SOC of battery pack in electric vehicle
JPH06333604A (en) Electric equipment for judging type of pack battery

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20040524

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040608

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040805

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20041207

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20041220

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090107

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090107

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100107

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110107

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110107

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120107

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120107

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130107

Year of fee payment: 8

LAPS Cancellation because of no payment of annual fees