JP3633333B2 - Manufacturing method of semiconductor chip - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is used, for example, in a semiconductor sensor that forms a flow sensor or the like by performing micromachining processing using anisotropic etching on a silicon substrate, and separately divides a plurality of semiconductor chips formed on the substrate. The present invention relates to a method of manufacturing a semiconductor chip in which a cutting groove is formed by anisotropic etching.
[0002]
[Prior art]
The semiconductor chip manufacturing method described above is disclosed in, for example, Japanese Patent Laid-Open No. 7-83707. In a conventional manufacturing method, when forming a flow sensor circuit in a semiconductor chip region on a silicon substrate by micromachining using anisotropic etching, a dicing V groove is formed around the semiconductor chip by the anisotropic etching. Form at the same time. An insulating film is formed on the silicon substrate, and the V groove is formed by anisotropically etching the silicon substrate from the V groove forming opening formed in the insulating film.
[0003]
[Problems to be solved by the invention]
By the way, when the V-groove is formed so as to surround the entire circumference of the semiconductor chip region as shown in FIG. 21A, the degree of erosion due to anisotropic etching is larger in the four corner portions C1 of the rectangular region than in other portions. As shown in the B1-B1 ′ sectional view of FIG. 21B, the silicon substrate below the insulating film is eroded. As a result, a gap is formed between the insulating film and the silicon substrate at the four corners, and there is a possibility that the insulating film at the four corners may be chipped when dicing along the V-groove. Further, since elements (peripheral elements and circuit elements) and wiring cannot be formed at the four corners where such erosion occurs, it is necessary to increase the chip area accordingly.
[0004]
On the other hand, in order to avoid excessive erosion of the silicon substrate at the four corners as described above, one V-groove is made a discontinuous groove so that the V-grooves do not intersect at the four corners as shown in FIG. There is. However, so-called chipping, that is, chipping at a portion where the V-groove becomes discontinuous during dicing, tends to occur. Further, since the cutting resistance changes at the discontinuous portion, the dicing blade is damaged, and the blade is easily cracked or chipped. 22 (b) is a plan view of the semiconductor chip after dicing, and FIG. 22 (c) is a view taken along arrow B2 in FIG. 22 (b). Since there are discontinuous portions in the V groove, protrusions are formed at the four corner portions C2 of the chip. It is formed and tends to cause chipping (for example, chipping during handling) in the process after dicing.
[0005]
An object of the present invention is to provide a semiconductor chip manufacturing method in which chipping is unlikely to occur during dicing or handling.
[0006]
[Means for Solving the Problems]
The description will be given in association with FIG. 7 showing the embodiment of the invention.
(1) Describing in association with FIG. 7, the invention of claim 1 collects functional structures (4a to 4c, 5, 6a, 6b) in each of a plurality of rectangular chip regions S2 on the substrate 2. And an etching rate by anisotropic etching, which is applied to a method for manufacturing a semiconductor chip, and a step of forming a cutting groove 2b by anisotropic etching on a substrate 2 between adjacent chip regions S2. Is formed on the substrate 2 at least at the four corners of the peripheral edge of the chip region S2, and an insulating film 103 is formed so as to cover the chip region S2 and the erosion prevention layer 101 for each chip region. , an etching opening by the insulating film 103 between the adjacent chip regions S2, forming the cutting grooves 2b performing anisotropic etching from the etching opening 105 a. Therefore, when anisotropic etching is performed, the etching amount of the erosion prevention layer 101 in the chip region S2 can be suppressed smaller than the etching amount of the substrate 2 in the groove forming portion.
(2) The invention of claim 2 is the method of manufacturing a semiconductor chip according to claim 1, wherein the substrate 2 is a silicon substrate, and the erosion prevention layer 101 is a boron diffusion layer obtained by doping the silicon substrate 2 with boron (B). It is. Since the boron diffusion layer 101 has a much slower etching rate with the silicon etchant than the silicon substrate 2, erosion of the chip region S 2 due to anisotropic etching is prevented by the boron diffusion layer 101.
(3) The invention of claim 3 is the semiconductor chip manufacturing method according to claim 1 or 2, wherein the functional structure in the chip region S2 is a sensor circuit such as a flow sensor, an infrared sensor, or a pressure sensor. is there.
[0007]
【The invention's effect】
According to the first to third aspects of the invention, the erosion prevention layer formed at least at the four corners of the rectangular chip region has an etching amount smaller than that of the substrate when anisotropic etching is performed. Erosion of the lower portion of the insulating film formed on the substrate in the chip region where the layer is formed can be suppressed, and chipping during dicing and handling can be reduced.
In particular, in the invention of claim 2, since the boron diffusion layer having a very small etching amount is formed as the erosion prevention layer, erosion due to etching can be prevented by the boron diffusion layer, and the lower part of the insulating film is eroded and the insulating film is eroded. Does not remain in a bowl shape, and chipping during dicing or handling can be prevented.
[0008]
In the section of the means for solving the above-described problems for explaining the configuration of the present invention, the drawings of the embodiments of the invention are used for easy understanding of the present invention. The form is not limited.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to FIGS.
-First embodiment-
1A and 1B are diagrams for explaining the operation of the semiconductor sensor chip. FIG. 1A is a plan view of the semiconductor sensor chip, and FIG. 1B is a cross-sectional view taken along the line DD ′ of FIG. A semiconductor sensor chip 1 shown in FIG. 1 is formed by forming a flow rate sensor circuit for detecting a minute flow rate of a fluid on a silicon substrate 2, and the sensor circuit is formed by using micromachining. Insulating films 103 and 104 made of silicon nitride (Si ₃ N ₄ ) or the like are formed on the silicon substrate 2, and the insulating films 103 and 104 are disposed above the recess 2 a formed in the silicon substrate 2 at the center of the chip. Cross-linked beams 4a, 4b, and 4c are formed. A heating element 5 is formed on the central beam 4a, and a resistance temperature detector 6a is formed on the beam 4b and a resistance temperature detector 6b is formed on the beam 4c so as to sandwich the heating element 5. The heating element 5 and the resistance temperature detectors 6a and 6b are connected to a controller (not shown). Reference numeral 101 denotes a boron diffusion layer formed on the silicon substrate 2, which will be described in detail later.
[0010]
The heating element 5 and the resistance temperature detectors 6a and 6b are respectively formed on the independent beams 4a to 4c, and the recesses 2 are formed below the beams 4a to 4c. Is almost separated. If this sensor chip is installed in the atmosphere, for example, and the heating element 5 is controlled to a temperature Th higher than the ambient temperature, the temperature Ta, Tb of the resistance temperature detectors 6a, 6b when there is no air flow near the chip surface. Are equal. FIG. 1C is a diagram conceptually showing the temperature Th of the heating element 5 and the temperatures Ta and Tb of the resistance temperature detectors 6a and 6b, and the vertical axis shows the temperature T.
[0011]
When an atmospheric flow as shown by an arrow E in FIG. 1B occurs, the resistance temperature detector 6a located upstream with respect to the heating element 5 is cooled by the atmosphere, and the temperature changes from Ta to Ta ′ (= Ta− ΔTa). On the other hand, the temperature sensing resistor 6b located downstream of the heating element 5 is accelerated by the air flow from the heating element 5, and the temperature rises from Tb to Tb ′ (= Tb + ΔTb). As a result, a temperature difference depending on the flow rate of the atmosphere occurs between the resistance temperature detectors 6a and 6b. Since this temperature difference is detected as a change in the resistance value of the resistance temperature detectors 6a and 6b, for example, the temperature difference can be converted into a voltage by incorporating the resistance temperature detectors 6a and 6b into a Wheatstone bridge circuit. A voltage output corresponding to the flow rate is obtained.
[0012]
When the semiconductor sensor chip 1 shown in FIG. 1 is manufactured, a plurality of semiconductor sensor chips 1 are collectively formed on the silicon wafer W as shown in FIG. Each semiconductor sensor chip 1 is separated by a non-pattern region (hereinafter referred to as a V-groove formation region) 10, and is individually separated by cutting the silicon substrate wafer W along the V-groove formation region 10 using a dicing apparatus. The semiconductor sensor chip 1 is divided.
[0013]
Next, the manufacturing procedure of the semiconductor sensor chip 1 will be described with reference to FIGS. 3 to 8, (a) is a plan view of the semiconductor sensor, and (b) is a cross-sectional view taken along line AA ′ of (a). First, as shown in FIG. 3, a silicon substrate 2 whose front and back surfaces are (100) planes of silicon crystal is prepared, and a resist pattern 100 is formed on one surface of the silicon substrate 2 by photolithography. The resist pattern 100 includes patterns 100A and 100B in which a photoresist layer is formed and a pattern 100C in which a photoresist layer is not formed. The pattern 100A and the pattern 100C are formed in the chip region of the semiconductor sensor chip 1 described above, and a circuit of the semiconductor sensor or the like is formed in a region of the pattern 100A where the photoresist layer is formed (hereinafter referred to as a circuit formation region). On the other hand, the pattern 100B is formed in the V-groove formation region 10.
[0014]
Next, using the resist pattern 100 of FIG. 3 as a mask, boron (B) is introduced into the silicon substrate 2 from the opening pattern 100C by ion implantation. At this time, the dose of boron is set to a high concentration of about 5 × 10 ^{15 to} 6 × 10 ¹⁶ (cm ⁻² ). Thereafter, the resist pattern 100 on the silicon substrate 2 is removed by a method using oxygen plasma, hot sulfuric acid, or the like, and annealing is performed at 950 ° C. for about 30 minutes to activate the introduced boron. A boron diffusion layer 101 is formed. As shown in FIG. 4, the boron diffusion layer 101 is formed so as to surround each circuit formation region S.
[0015]
When the boron diffusion layer 101 is formed on the silicon substrate 2, as shown in FIG. 5, silicon nitride (Si ₃ N ₄ ) having corrosion resistance against a silicon etchant (such as hydrazine or potassium hydroxide (KOH)). And the like are formed on both the front and back surfaces of the silicon substrate 2 by a low pressure CVD method, a plasma CVD method, or the like. Next, a thin film of metal (for example, platinum) is formed by sputtering on the insulating film 103 on the side of the silicon substrate 2 on which the boron diffusion layer 101 is formed, and this metal film is formed by photolithography, sputter etching, or the like. The heating element 5 and the resistance temperature detectors 6a and 6b are formed in a pattern shape.
[0016]
Thereafter, as shown in FIG. 6, an insulating film 104 such as silicon nitride (Si ₃ N ₄ ) for protecting the surface of the semiconductor sensor is covered with the heating element 5 and the resistance thermometers 6a and 6b of the silicon substrate 2. The insulating films 103 and 104 are partially etched by plasma etching or the like to form anisotropic etching openings 105A, 105B, and 105C. The opening 105A is formed on the V groove forming region 10 between the boron diffusion layers 101 formed so as to surround the chip forming region S, and the triangular opening 105B sandwiches the heating element 5 and the resistance temperature detectors 6a and 6b. The slit-shaped opening 105C is formed between the heating element 5 and the resistance temperature detectors 6a and 6b. In FIG. 6, S2 indicates a chip region surrounded by the V-groove formation region 10, and the sensor circuit and the boron diffusion layer 101 are formed in the chip region S2.
[0017]
Next, when the silicon substrate 2 is anisotropically etched with a silicon etchant such as hydrazine or potassium hydroxide (KOH), the silicon substrate 2 is etched into a V-groove shape at the opening 105A as shown in FIG. A groove 2b is formed. On the other hand, the silicon substrate 2 anisotropically etched from the two triangular openings 105B and the slit-shaped openings 105C is etched as shown in the DD ′ cross-sectional view of FIG. 1 to form a recess 2a. As a result, the heating elements 5 and the resistance temperature detectors 6a and 6b are provided to form beams 4a, 4b and 4c which are separated from each other. Since the lower surfaces of the beams 4 a to 4 c are separated from the silicon substrate 2, they are thermally separated from the silicon substrate 2.
[0018]
Finally, the semiconductor sensor chip 1 as shown in FIG. 8 is obtained by dicing along the V-groove 2a formed in the silicon substrate 2 and dividing the semiconductor sensor chip. By the way, as shown in FIG. 6B, a boron diffusion layer 101 having an extremely low anisotropic etching rate compared to the silicon substrate 2 is formed on both sides of the V groove forming region 10 exposed in the opening 105A. Since it is formed as an erosion prevention layer, anisotropic etching from the opening 105A is blocked by the boron diffusion layer 101 and does not proceed to the circuit formation region S. Therefore, as can be seen by comparing FIG. 8B and FIG. 21B, according to the manufacturing method of the present embodiment, the difference between the four corners of the semiconductor sensor chip 1 that bites into the lower part of the insulating film 103 is obtained. No erosion caused by isotropic etching. As a result, it is possible to prevent chipping at the four corners during dicing to be divided into each semiconductor sensor chip and during subsequent processing.
[0019]
-Second Embodiment-
FIGS. 9 to 11 are diagrams for explaining a second embodiment of the manufacturing method according to the present invention, and FIGS. 9 and 10 are diagrams corresponding to FIGS. 3 and 4 of the first embodiment. In the step shown in FIG. 9, a resist pattern 200 is formed by photolithography on one surface of the silicon substrate 2 whose front and back surfaces are the (100) planes of silicon crystals. S2 indicates a region where the semiconductor sensor chip 1 (see FIG. 2 described above) is formed on the silicon substrate 2, and rectangular opening patterns 200A where no photoresist is formed are formed at the four corners of the chip region S2. 9B is a cross-sectional view taken along the line FF ′ of FIG.
[0020]
Next, using the resist pattern 200 of FIG. 9 as a mask, boron is introduced into the silicon substrate 2 from the opening pattern 200A by ion implantation. The dose of boron at this time is set to about 5 × 10 ^{15 to} 6 × 10 ¹⁶ (cm ⁻² ), which is the same as in the first embodiment. Thereafter, the resist pattern 200 on the silicon substrate 2 is removed by a method using oxygen plasma, hot sulfuric acid, or the like, and annealing is performed at 950 ° C. for about 30 minutes to activate the introduced boron to obtain a high concentration. The boron diffusion layers 201 are formed at the four corners of the chip region S2 as shown in FIG.
[0021]
Subsequent steps (such as formation of a sensor circuit and a V-groove) are the same as those in the first embodiment described above, and thus description thereof is omitted in this embodiment. FIG. 11 shows one obtained by dividing a plurality of semiconductor sensor chips 1 formed on a silicon substrate 2 into individual semiconductor sensor chips 1, and (b) shows an F of (a). It is -F 'sectional drawing. In the present embodiment, since the high-concentration boron diffusion layers 201 are formed at the four corners of the chip region S2, the semiconductor sensor chip 1 bites into the lower portion of the insulating film 103 in the same manner as in the first embodiment. Erosion due to anisotropic etching does not occur. As a result, it is possible to prevent chipping at the four corners during dicing to be divided into the respective semiconductor sensor chips 1 and handling in the subsequent process.
[0022]
Further, in the present embodiment, since the boron diffusion layer 201 is formed only at the four corner portions where erosion due to etching is significant in the chip region S2, the circuit formation region is made larger than that in the first embodiment described above. Can do.
[0023]
-Third embodiment-
In the first and second embodiments described above, the case where the manufacturing method according to the present invention is applied to the flow sensor has been described. However, the present embodiment is applied to the manufacture of an infrared sensor. 12A is a plan view of the infrared sensor chip 30, and FIG. 12B is a cross-sectional view taken along line HH ′ of FIG. A recess 20a is formed at the center of the silicon substrate 20, and diaphragms M supported by four beams P are formed above the recess 20a. Each beam P is formed with N-type polycrystalline silicon 304 and P-type polycrystalline silicon 305 constituting the thermocouple TC, and an infrared absorber 312 for converting infrared light into heat is formed on the diaphragm M. Since the diaphragm M is thermally separated from the silicon substrate 20, a temperature difference is generated between the hot spot Q1 on the diaphragm M side and the cold spot Q2 on the silicon substrate 20 side, and electromotive forces are generated in the four thermocouples TC. Occur. The thermocouples TC are connected in series by an aluminum wiring 309, and the infrared ray irradiated to the infrared absorber 312 is converted into an electric signal by taking out an electromotive force as a voltage output through the aluminum wiring 309.
[0024]
Next, a manufacturing procedure of the infrared sensor chip shown in FIG. 12 will be described with reference to FIGS. 13 to 20, (a) is a plan view of the infrared sensor, and (b) is a cross-sectional view taken along line HH ′ of (a). First, as shown in FIG. 13, a defect layer 301 is formed by implanting silicon ions by photolithography and ion implantation into the central portion of the chip region S3 on the silicon substrate 20 whose front and back surfaces are the (100) planes of silicon crystal. . Next, an insulating film 302 such as silicon nitride (Si ₃ N ₄ ) having corrosion resistance against the silicon etching solution is formed on the silicon substrate surface on which the defect layer 301 is formed by a low pressure CVD method or the like. Thereafter, a pattern of the insulating film 302 as shown in FIG. 13 is formed by using photolithography, reactive ion etching, or the like.
[0025]
In the next step, a polycrystalline silicon film is formed on the insulating film 302 by low pressure CVD or the like, and the polycrystalline silicon is patterned by photolithography and reactive ion etching to form a polycrystalline silicon pattern as shown in FIG. 303 (303A, 303B) is formed. Thereafter, phosphorus or arsenic is introduced into the polycrystalline silicon pattern 303A and boron is introduced into the polycrystalline silicon pattern 303B by photolithography and ion implantation to form N-type polycrystalline silicon 304 and P-type polycrystalline silicon 305 (FIG. 15).
[0026]
FIG. 15 is a diagram showing a case where N-type polycrystalline silicon 304 and P-type polycrystalline silicon 305 are formed in this order. The resist pattern 306 which is a mask when boron ions are implanted into the polycrystalline silicon pattern 303B includes An opening pattern 306A that exposes the crystalline silicon pattern 303B and an opening pattern 306B at the edge of the chip region S3 are formed. For this reason, boron is also introduced into the silicon substrate 20 exposed in the opening pattern 306B, and a high-concentration boron diffusion layer 307 is formed. After that, as shown in FIG. 16, an interlayer insulating film 308 such as phosphorous glass is formed by atmospheric pressure CVD or the like and, for example, annealing is performed at 950 ° C. for about 30 minutes to activate the impurities.
[0027]
Next, after forming contact holes in the interlayer insulating film 308 for connecting each of the polycrystalline silicons 304 and 305 and the aluminum wiring, an aluminum film is formed by sputtering or the like, and the aluminum film is patterned to obtain a pattern shown in FIG. An aluminum wiring 309 as shown in FIG. After that, as shown in FIG. 18, a final protective film 310 such as a silicon nitride film is formed on the interlayer insulating film 308 and the aluminum wiring 309 by plasma CDV or the like, and a recess 20a (FIG. 12) is formed on the silicon substrate 20 and will be described later. Anisotropic etching openings 311A (L-shaped openings) and 311B for forming V grooves to be formed are formed in the protective film 310.
[0028]
Then, the silicon substrate 20 is anisotropically etched with a silicon etchant such as hydrazine or potassium hydroxide (KOH) to form the recesses 20a and the V-grooves 20b as shown in FIG. As a result, diaphragms M supported by the four beams P are formed above the recess 20a. An infrared absorber 312 as shown in FIG. 20 is formed by forming an infrared absorption film (for example, a film made of gold black) on the membrane M and performing patterning. When a plurality of infrared sensors are collectively formed on the silicon substrate 20 in this way, dicing is performed along the V-groove 20b formed by anisotropic etching, and individual infrared sensors as shown in FIG. The sensor chip 30 is divided.
[0029]
Also in the present embodiment, since the boron diffusion layer 307 similar to that of the first embodiment is formed, the boron diffusion layer 307 functions as a stopper when performing anisotropic etching through the opening 311B, and an infrared sensor. In the four corners of the chip 30, no erosion occurs in the lower part of the insulating film 302. As a result, chipping during dicing and handling can be prevented. In this embodiment, the boron diffusion layer 307 is formed on the entire circumference of the chip. However, the boron diffusion layer 307 may be provided only at the four corners as in the second embodiment described above.
[0030]
In the embodiment described above, a boron diffusion layer is formed as an anisotropic etching stopper when forming the V-groove. However, a diffusion layer doped with arsenic (As), phosphorus (P), or the like in addition to boron is used. Even if it is used, the same effect can be obtained. In addition, the sensor circuit formed on the chip includes a pressure sensor in addition to the above-described flow rate sensor and infrared sensor. Furthermore, a method of manufacturing a semiconductor chip in which a plurality of semiconductor chips are collectively formed on a silicon substrate, a V-groove is formed between the chips, and then diced to be divided into individual semiconductor chips. The manufacturing method according to the present invention can be applied not only to the semiconductor sensor such as the flow sensor and the infrared sensor described above in the machining process but also to a semiconductor chip on which a general integrated circuit is formed.
[0031]
In the correspondence between the elements of the embodiment described above and the elements of the claims, the heating element 5 formed on the beams 4a to 4c, the flow sensor composed of the resistance thermometers 6a and 6b, and the membrane M The infrared sensor composed of the infrared absorber 312 formed above and the thermocouple TC formed in the beam P portion corresponds to a functional structure, the V grooves 2b and 20b serve as cutting grooves, and the boron diffusion layer 101. , 201, 307 constitute an erosion prevention layer.
[Brief description of the drawings]
1A and 1B are diagrams for explaining the operation of a semiconductor sensor chip, in which FIG. 1A is a plan view of the semiconductor sensor chip, FIG. 1B is a sectional view taken along the line DD ′ of FIG. The figure which shows notionally the temperature of the resistance temperature detectors 6a and 6b.
FIG. 2 is a plan view of a silicon wafer W on which a plurality of semiconductor sensor chips 1 are formed.
3A and 3B are diagrams illustrating a manufacturing procedure of the semiconductor sensor chip 1, wherein FIG. 3A is a plan view of the semiconductor sensor, and FIG. 3B is a cross-sectional view taken along line AA ′ of FIG.
4A and 4B are diagrams for explaining the procedure following FIG. 3, wherein FIG. 4A is a plan view of the semiconductor sensor, and FIG. 4B is a cross-sectional view taken along line AA ′ of FIG.
5A and 5B are diagrams for explaining the procedure following FIG. 4, in which FIG. 5A is a plan view of the semiconductor sensor, and FIG. 5B is a cross-sectional view taken along line AA ′ of FIG.
6A and 6B are diagrams for explaining a procedure following FIG. 5, in which FIG. 6A is a plan view of the semiconductor sensor, and FIG. 6B is a cross-sectional view taken along line AA ′ of FIG.
7A and 7B are diagrams for explaining a procedure following FIG. 6, in which FIG. 7A is a plan view of the semiconductor sensor, and FIG. 7B is a cross-sectional view taken along line AA ′ of FIG.
8A and 8B are diagrams for explaining a procedure following FIG. 7, in which FIG. 8A is a plan view of the semiconductor sensor, and FIG. 8B is a cross-sectional view taken along line AA ′ of FIG.
FIGS. 9A and 9B are diagrams for explaining a second embodiment of a manufacturing method according to the present invention and showing a manufacturing procedure of a semiconductor sensor chip; FIG. 9A is a plan view of the semiconductor sensor, and FIG. FF 'sectional drawing of (a).
10A and 10B are diagrams for explaining the procedure following FIG. 9, in which FIG. 10A is a plan view of the semiconductor sensor, and FIG. 10B is a cross-sectional view taken along line FF ′ of FIG.
11A and 11B are diagrams showing the semiconductor sensor chip 1 divided individually, where FIG. 11A is a plan view and FIG. 11B is a cross-sectional view taken along line FF ′ of FIG.
12A and 12B are diagrams for explaining a third embodiment of the manufacturing method according to the present invention, in which FIG. 12A is a plan view of an infrared sensor chip 30 and FIG. 12B is a cross-sectional view taken along line HH ′ of FIG.
13A and 13B are diagrams for explaining a manufacturing procedure of the infrared sensor chip 30, wherein FIG. 13A is a plan view of the sensor, and FIG. 13B is a cross-sectional view taken along line HH ′ of FIG.
14A and 14B are diagrams for explaining the procedure following FIG. 13, in which FIG. 14A is a plan view of the sensor, and FIG.
15A and 15B are diagrams for explaining the procedure following FIG. 14, in which FIG. 15A is a plan view of the sensor, and FIG.
16A and 16B are diagrams for explaining the procedure following FIG. 15, in which FIG. 16A is a plan view of the sensor, and FIG.
FIGS. 17A and 17B are diagrams for explaining the procedure following FIG. 16, in which FIG. 17A is a plan view of the sensor, and FIG.
18A and 18B are diagrams for explaining the procedure following FIG. 17, in which FIG. 18A is a plan view of the sensor, and FIG.
FIGS. 19A and 19B are diagrams for explaining the procedure following FIG. 18, in which FIG. 19A is a plan view of the sensor, and FIG.
20A and 20B are diagrams for explaining the procedure following FIG. 19, in which FIG. 20A is a plan view of the sensor, and FIG.
21A and 21B are diagrams for explaining an example of chipping of a semiconductor chip, in which FIG. 21A is a plan view of a silicon substrate on which a semiconductor chip is formed, and FIG. 21B is a cross-sectional view along B1-B1 ′ in FIG.
22A and 22B are diagrams for explaining another example of chipping of a semiconductor chip, in which FIG. 22A is a plan view of a silicon substrate on which the semiconductor chip is formed, FIG. 22B is a plan view of the semiconductor chip, and FIG. B2 arrow directional view.
[Explanation of symbols]
1 Semiconductor sensor chip 2, 20 Silicon substrate 2a, 20a Recess 2b, 20b V groove 5 Heating element 6a, 6b Resistance temperature detector 101, 201, 307 Boron diffusion layer 103, 104, 302, 308 Insulating film 312 Infrared absorber S2 , S3 Chip area

Claims (3)

Forming a functional structure at a time in each of a plurality of rectangular chip regions on the substrate; and forming a cutting groove by anisotropic etching on the substrate between adjacent chip regions. In a method for manufacturing a semiconductor chip,
An erosion prevention layer having an etching rate by anisotropic etching smaller than that of the substrate is formed on the substrate at least at the four corners of the peripheral edge of the chip region, and the chip region and the erosion prevention layer are covered for each chip region. An insulating film is formed, an opening for etching by the insulating film is formed between adjacent chip regions, and the cutting groove is formed by performing the anisotropic etching from the opening for etching. A method for manufacturing a semiconductor chip. In the manufacturing method of the semiconductor chip according to claim 1,
The method of manufacturing a semiconductor chip, wherein the substrate is a silicon substrate, and the erosion prevention layer is a boron diffusion layer in which boron (B) is doped on the silicon substrate. In the manufacturing method of the semiconductor chip according to claim 1 or 2,
The semiconductor chip manufacturing method, wherein the functional structure in the chip region is a sensor circuit such as a flow rate sensor, an infrared sensor, or a pressure sensor.

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