JP3632443B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a memory that requires refresh, that is, a dynamic random access memory (hereinafter abbreviated as DRAM) and a logic circuit are integrated into one chip.
[0002]
[Prior art]
In a DRAM in which a memory cell is formed by a capacitor, data held in the memory cell as charges is lost due to a leak current after a certain period of time. Therefore, in order to rewrite and maintain the data held in the memory cell, it is necessary to perform a refresh operation. In the refresh operation in the DRAM, in a memory matrix constituted by a plurality of rows and columns of memory cells, a row line (word line) for one row is selected and then all memory cells on the word line are read / written. This is realized by sequentially performing the amplification / rewriting operation on all the word lines.
[0003]
The refresh operation of the DRAM includes a refresh operation that is interrupted during a random access operation such as reading / writing data to / from a memory cell, and a period in which the DRAM is not in a random access operation but in a data holding mode, for example, during a backup period by a battery And a refresh operation performed.
[0004]
There are two methods for the former, that is, the refresh operation performed by interrupting the access operation. One is a RAS only refresh method in which a refresh row address is given from an external refresh address counter and refresh is performed during a period from when the row address strobe signal / RAS is raised to when it is raised. The other is an auto-refresh method in which a refresh request signal is given from the outside and the row address is switched from the external address to a refresh address counter built in the DRAM to perform refresh. Currently, as an auto-refresh method, the column address strobe signal / CAS and the row address strobe signal / RAS are set to the low level “L” in this order, and the refresh is performed after the row address strobe signal / RAS is lowered and raised. CAS before RAS refresh (hereinafter abbreviated as CBR refresh) is a standard specification.
[0005]
For the refresh operation in the latter, that is, the data holding mode, a control signal is externally applied by performing refresh using the output of the built-in refresh address counter as a row address in response to a refresh request signal automatically generated by an internal timer. There is a self-refresh method in which refresh is continuously performed at a constant cycle without giving. At present, as a self-refresh method, CBR self-refresh operation is started by keeping both the row address strobe signal / RAS and the column address strobe signal / CAS at “L” for 100 μsec or more. It has become.
[0006]
[Problems to be solved by the invention]
However, according to the above-described conventional configuration, since the signal for checking the self-refresh circuit that generates the refresh request signal at the time of self-refresh is not output to the external terminal, in order to detect a defect of the self-refresh circuit, After writing data into the memory, enter the self-refresh mode, and if you do not refresh, wait more than the time that the data held in the memory cell leaks and is lost, then read the data in the memory cell and the data is lost The test of whether or not it has been done, the problem that the test time becomes long, the pulse width of the refresh request signal cannot be checked, and the refresh cycle at the time of self-refresh cannot be checked, so the refresh cycle can be optimized by trimming Previous issues and problems Pulse width or refresh cycle has had a problem that it is impossible to make the pulse width or period by trimming at the time of non-standard in the standard. In view of the above-described conventional problems, the present invention is a memory device that requires refresh, that is, a semiconductor device in which a DRAM and a logic circuit are integrated on a single chip, and the self-refresh circuit can be tested in a short time. It is an object to provide a semiconductor device capable of optimizing a self-refresh cycle by trimming and repairing a defective product.
[0007]
[Means for Solving the Problems]
In order to solve this problem, a semiconductor device of the present invention supplies a memory having a memory cell that needs to be refreshed to store data, and an oscillation clock having a certain period when a self-refresh control signal is input. Oscillating means for performing, and on the basis of the oscillation clock, signal generating means for supplying an internal self-refresh control signal for refreshing the memory cells; A logic gate circuit that supplies a row selection control signal based on the internal self-refresh control signal during a self-refresh test and supplies the row selection control signal based on an input from an external input terminal during a data read test from a memory A row selection circuit for activating a word line selected by a row address in response to the row selection control signal; Above Row selection control signal Is provided with a signal output means for outputting to the external terminal, so that the refresh cycle at the time of self-refresh can be checked.
[0008]
As a result, the self-refresh circuit can be tested in a short time, and a semiconductor device capable of optimizing the self-refresh cycle by trimming and repairing defective products can be realized.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor device according to the first embodiment of the present invention will be described below with reference to the drawings.
[0010]
FIG. 1 shows a configuration of a semiconductor device according to the first embodiment of the present invention.
In FIG. 1, a memory cell and peripheral circuit 3 are a memory array composed of a plurality of memory cells and a block composed of the peripheral circuit, a logic unit 4 is a block composed of a microcomputer or logic, and a refresh counter 224 is , Counter circuits for generating row addresses at the time of refreshing, 210-214, 230, 231 are inverter circuits, 215-218 are D flip-flops (hereinafter abbreviated as DFF), and selectors 201-208, 229 have S inputs In the case of “H”, the B input is selected. The row address latch 225, the column address latch 226, and the byte address latch 227 are circuits that latch an input signal at the rising edge of the clock (2) when the EN input is “H”. The test decode circuit 228 is a circuit that decodes a plurality of external test input terminals and determines the test mode of the DRAM 2.
[0011]
FIG. 2 is a configuration diagram of the memory cell array and the peripheral circuit 3 of FIG. The memory cells M01 to MN2m are storage elements for storing 1-bit data in the capacitor. The memory cell array 300 is a storage unit having memory cells M01 to MN2m of N rows × 2m columns. The memory cell array 300 reads and writes data by using word lines WL1 to N as N row selection lines and bit lines (1) to 2m and / bit lines (1) to 2m as bit pairs of 2m pairs. Is executed. The row selection circuit 301 is row selection means for receiving a row selection control signal, selecting a word line WL based on the received row address, and applying a pulse to the selected word line WL. The sense amplifiers SA1 to 2m are amplifying means for amplifying a minute voltage difference between the bit lines and / or the bit lines, and the Pch transistors T01 to T0 (2m) and T11 to T1 (2m) correspond to the row selection control signal. Switching means for precharging each bit line and / bit line by applying a precharge voltage to the bit line and / bit line. Pch transistors T21 to T2 (2m) are switching means for equalizing each bit line / bit line in accordance with a row selection control signal. Nch transfer gates TG01 to TG0 (2m) and TG11 to TG1 (2m) connect the bit lines and / bit lines amplified by the sense amplifiers to the main bit lines and / main bit lines of the main amplifiers MA0 to MA. Switching means.
[0012]
FIG. 3 is a detailed explanatory diagram of the self-refresh circuit 250 of FIG.
In FIG. 3, an oscillation circuit 251 is an oscillation means for supplying a clock CLK1 when the received self-refresh control signal is “H”. The two frequency dividers 268, 269, and 270 are frequency dividing means for sequentially dividing the received clock CLK1 and supplying the divided clocks CLK2, CLK4, and CLK8, respectively. The selector 271 selects the divided clock CLK8 when the clock selection signal is “H”, and selects the divided clock CLK8 when the clock selection signal is “L”. Selection means for supplying a signal CKO. The one-shot pulse generation circuit 274 is pulse generation means for generating a set pulse SETP having a predetermined pulse width in response to the rising edge of the received frequency-divided signal CKO. The set reset circuit 275 is a signal generating means for supplying a self-refresh signal SRO according to the received set pulse SETP and reset pulse RSTP.
[0013]
The first delay circuit 276 is a delay means for supplying a reset pulse RSTP obtained by delaying the received internal self-refresh signal for a predetermined time to the reset terminal of the set reset circuit 275.
[0014]
Hereinafter, an operation during a data read test of the DRAM 2 built in the semiconductor device 1 according to the first embodiment will be described. During the test, a signal is input from the external input terminal and the DRAM 2 is tested alone.
[0015]
First, an input signal selection operation during a data read test will be described with reference to FIG. In FIG. 1, when the data read test mode is set by the external test input terminal, the DRAM test signal is set to the high level by the test decode circuit 228, so the selector 201 to the selector 208 select the B input. . Therefore, the external input terminal (1) is input to the clock (2), the external input terminal (2) is input to the / self-refresh control signal (2), and the / auto-refresh control signal (2) is input to the / auto-refresh control signal (2). The external input terminal (3) is input, the external input terminal (4) is input to the / row selection control signal (2), and the external input terminal (5) is input to the / column selection control signal (2). The external input terminal (6) is input to the / write control signal (2), and the external input terminal (7) is input to both the row address 2 and the column address (2).
[0016]
Here, both the row address (2) and the column address (2) are input from the external input terminal (7) as the DRAM address input, but this is shared in order to reduce the number of external terminals during the test. A signal in which a row address and a column address are multiplexed is applied to an external input terminal (7), and is separated into a row address and a column address in the DRAM 2.
[0017]
A read operation during a test of the DRAM 2 will be described with reference to timing charts of FIGS. 1, 2, and 4.
[0018]
The read operation in the page mode during the data read test of the DRAM 2 will be described with reference to the timing chart of FIG. 4 and FIGS. Since the / self-refresh control signal (2) is at a high level at time t0 in FIG. 4, the internal self-refresh control signal that is the output of the self-refresh circuit is a low level and the / auto-refresh control signal (2). The signal internal auto refresh control signal synchronized with the clock (2) by the DFF 215 in FIG. 1 is the Low level, and the signal row selection control signal (2) synchronized with the clock (2) by the DFF 216 in FIG. Since the control signal is at the low level, the row selection control signal that is the output of the OR circuit 222 is at the low level, and the Pch transistors T01 to T0 (2m), T11 to T1 (2m), and T21 to T2 (2m) are ON. The bit lines (1) to 2m and the / bit lines (1) to 2m are precharged to 1/2 Vdd, Is Koraizu.
[0019]
When the row selection control signal (2) falls from the high level to the low level at time t1 in FIG. 4, the row selection control signal rises from the low level to the high level, and the Pch transistors T01 to T0 (2m), T11 to T1. (2m), T21 to T2 (2m) are turned OFF, precharging and equalization of the bit lines (1) to 2m and / bit lines (1) to 2m are stopped, and at the rising edge of the clock (2) at time t1 Since the latch enable signal of the row address latch 225, which is the output signal of the inverter 214, is at a high level, the row address latch 225 latches the row address (2) with the clock (2) and outputs the row address. Since the internal self-refresh control signal and the internal auto-refresh control signal are at the low level, the output of the NOR circuit 221 / the internal refresh control signal is at the high level, and the row address (3) that is the B input of the selector 229 is selected. And output to the row address.
[0020]
In FIG. 2, in the row selection circuit 301, since the row selection control signal is at the high level, the row line WLn selected by the row address is at the high level, and the sense amplifier is enabled by the delay circuit (2) -303 from time t1. Delayed to High level, the sense amplifiers SA1 to SA2m are activated, and the data of the memory cells connected to WLn are read to the bit lines (1) to 2m and / bit lines (1) to 2m. The differential amplification is performed by the sense amplifiers SA1 to SA2m.
[0021]
Since the internal refresh control signal is at the high level, the row selection control signal is at the high level. In this embodiment, the row address (0), which is one bit in the row address, is set to the low level. As shown in FIG. 4, the gate enable (0), which is the output of, becomes the high level after the delay time of the delay circuit (3) -304 from the rise of the row selection control signal, and is the output of the AND circuit 307. Since the gate enable (1) is at the low level, the odd-numbered transistors TG01, TG11, TG03, TG13, TG05, TG15... TG0 (2m-1), TG1 (2m-1) are turned on. The outputs of the odd-numbered sense amplifiers S1, S3, S5... S (2m−1) are input to the main amplifiers MA1 to MAm, When the voltage difference between the main bit line and / or the main bit line, which is the output of the amplifier, becomes large, differential amplification of the main amplifiers MA1 to MAm starts, and as shown in FIG. 4, the main amplifiers MA1 to MAm Thus, MOUT1 to MOUTm are output.
[0022]
At time t2, since the row selection control signal (2) and the column selection control signal (2) are both at the low level, the outputs of the inverters 211 and 212 in FIG. 1 are at the high level, so that the output of the AND gate 219 is at the high level. Therefore, the column address latch 226 is latch enabled, and at time t2, the column address (2) is latched at the rising edge of the clock, and the column address is output. Similarly, the byte address latch 227 latches the byte address (1) at the rising edge of the clock and outputs the byte address. As shown in FIG. 2, in the column selection circuit 302, the 8k-bit data output signal selected by the column address (3) from the m-bit data of MOUT1 to MOUTm is output to the data selection circuit 308 to select the data. The circuit 308 selects 8-bit test data from the 8-kbit data output signal according to the byte address, and outputs it as test data (7: 0). Of the test data (7: 0), the test data (7: 1) is output to the selector 309, and the test data (0) is output to the selector 312. Since the DRAM test signal is at the high level, the output of the inverter 314 is at the low level, so that the test data (7: 1) that is the A input to the selector 309 is output to the tristate buffer 310. At time t2, since the / row selection control signal (2) and the / column selection control signal (2) are at a low level and the / write control signal 2 is at a high level, the AND circuit 220 is at a high level. And the clock (2), the timing generation circuit 223 sets the output control signal to High level at the timing shown in FIG. Since the output control signal is at the high level and the output of the inverter 314 is at the low level, the IO control signal (1) which is the output of the OR circuit 315 is at the high level, and the test data (7: 1) is input to the external input / output terminal (7 1).
[0023]
Since the self-test signal is at the low level, the selector 312 outputs the test data (0) as the A input to the selector 313. Since the output of the inverter 314 becomes a low level, the selector 313 outputs the test data (0) that is the output of the selector 312 that is the A input to the tristate buffer 317. As described above, since the IO control signal (1) is at the high level and the self test signal is at the low level, the IO control signal (0), which is the output of the OR circuit 316, is at the high level. It is output to the input / output terminal (0). The test data (7: 0) is output to the external input / output terminal (7: 0) at the timing shown in FIG.
[0024]
At times t3, t4, and t5, as in the case of time t2, at the rising edge of the clock (2), the / row selection control signal (2) and the / column selection control signal (2) are both at the low level, and / write enable Since the signal is at the high level, the data of the memory cells selected by the latched column address and byte address are sequentially transferred to the external input / output terminals (as shown in the timing chart of FIG. 7: 0). At time t6, because the / row selection control signal (2) and the / column selection control signal (2) are at a high level, the output of the AND circuit 220 is at a low level, so that the output control signal is at a low level, and the IO control signal Since (0) and (1) are at a low level, the output of the external input / output terminal (7: 0) becomes high impedance.
[0025]
Next, an operation during a self test for testing the self refresh operation will be described below. First, the operation of the self-refresh circuit of FIG. 3 will be described using the timing chart of FIG.
[0026]
In the period from time 0 to t0, the / row selection control signal (2) and the / auto-refresh control signal (2) are initialized to "H" by the external input terminal, and the / self-refresh control signal (2) is set. When supplied at "H", the self-refresh control signal becomes "H" and one input of the NAND circuit 257 becomes "L", so that the output signal S4 is "H" and the PMOS transistor 254 is The signal S1, which is the input of the inverter 11, is turned "H". Therefore, the signals S0 and S3 at both ends of the oscillation capacitors 259 and 260 are forcibly initialized to “H”, that is, the power supply voltage Vdd, and the oscillation is stopped. Further, since the self-refresh control signal is “L”, the divided clocks CLK2, CLK4, and CLK8, which are the outputs of the frequency dividers 268, 269, and 270, are all initialized to “L”.
[0027]
Here, at time t0, when the self-refresh control signal is supplied to "H" by the external input terminal (2), the DRAM 2 enters the self-refresh mode. In this case, since the potential of the signal S3 at time t0 is “H”, the self-refresh control signal, which is one input of the NAND circuit 257, becomes “H” at time t0, which is the output of the NAND circuit 257. The signal S4 becomes “L”. For this reason, the oscillation clock CLK1 that is the output of the inverter 267 rises from "L" to "H", and the frequency-divided clocks CLK2, CLK4, and CLK8 that are the outputs of the two-frequency dividers 268, 269, and 270 are "L". It rises from "" to "H". Therefore, when the self-refresh control signal rises from “L” to “H” at time t0, in a state where the fuse 273 is not cut, the S input of the selector 271 is “H”, so that CLK4 is selected and CKO is set to CKO. Is output. The one-shot pulse generation circuit 274 generates one set pulse SETP in response to the received rising edge of the divided clock CLK4 and sets the set reset circuit 275. The set reset circuit 275 is reset by the reset pulse RSTP in which the generated set pulse SETP is delayed by the delay circuit 1-276. As a result, the set / reset circuit 275 supplies a self-row selection control signal having a predetermined pulse width equal to the delay time of the delay circuit (1) -276. Thereafter, the set reset circuit 275 supplies the internal self-refresh control signal in the cycle of the divided clock CLK4 in accordance with the received set pulse SETP.
[0028]
In FIG. 1, since the / auto refresh control signal (2) and the / row selection control signal (2) are initially set to “H”, the outputs of the DFF 215 and DFF 216 become “L”, so that the OR circuit 222 Of these three inputs, two inputs are “L”. Therefore, the OR circuit 222 supplies the internal self-refresh control signal as it is as a row selection control signal. As described above, since the internal self-refresh control signal becomes “H” at time t0, the DRAM 2 starts the first refresh operation. When the row selection control signal becomes “H”, the DRAM 2 in FIG. 3 operates as follows. That is, “H” is applied to the word line WLn selected by the row address (address value A) which is the output of the refresh counter 224, and all the memory cells MN1 to MN2m on the word line WLn are selected, and 2m pairs The data of each of the memory cells MN1 to MN2m is read as a minute signal to the bit line / bit line. The minute signal is differentially amplified by 2m sense amplifiers SA1 to SA2m, and data is rewritten to each memory cell 80 by the amplified signal. As a result, a refresh operation is performed on one word line WLn.
[0029]
Hereinafter, the operation of the oscillation circuit 251 will be described with reference to FIG. In the oscillation circuit 251 in FIG. 3, the PMOS transistor 254 is turned off at time t0 in FIG. 3, so that the signal C1 is disconnected from the power supply voltage Vdd and the signal S4 becomes “L”. Capacitors C1 and C2 start discharging. Therefore, the signal level of the signal S0 decreases according to the time constant RC of the oscillation resistor R1 (resistance value R) and the oscillation capacitors C1 and C2 (total capacitance C) from the power supply voltage Vdd, and at time t1, the inverter 255 It becomes equal to the threshold voltage Vth. That is, at time t1, the signal S2 that is the output of the inverter 255 is inverted from “L” to “H”, and the signal S3 that is the output of the inverter 256 is inverted from “H” to “L”. As a result, the signal level of the signal S0 changes to -Vth, and the signal S4, which is the output of the NAND circuit 14, is inverted from "L" to "H", that is, Vdd. Therefore, the oscillation capacitors C1 and C2 start charging from time t1. The signal level of the signal S0 increases according to the time constant RC and becomes the threshold voltage Vth at time t2, so that the signal S2 that is the output of the inverter 255 is the output of the inverter 256 from “H” to “L”. The signal S3 is inverted from “L” to “H”. As a result, the signal level of the signal S0 changes to Vdd + Vth, and the signal S4 that is the output of the NAND circuit 257 is inverted from "H" to "L", that is, 0V. Accordingly, the oscillation capacitor C1 starts discharging from time t2. Here, as shown in FIG. 5, the signal level of the signal S1 is clamped at a potential obtained by adding the forward voltage Vf of the protection diodes 252 and 253 to the signal level of the signal S0.
[0030]
The oscillation circuit 10 repeats the oscillation operation as described above, and supplies the oscillation clock CLK1 at a cycle determined according to the time constant RC as shown in FIG. Therefore, the frequency-divided clock CLK4 output from the frequency divider 269 rises at time t3 after the period T1 has elapsed since the oscillation circuit 10 started oscillating at time t1. Therefore, at time t3, the one-shot pulse generation circuit 274 sets the set reset circuit 275 and the internal self-refresh control signal that is the output of the set reset circuit 275 rises. Thereby, DRAM 2 starts the second refresh operation at time t3 by the internal self-refresh control signal, that is, the row selection control signal. At this time, as shown in FIG. 5, the count value of the refresh counter 224 is counted up from A at time t0 to A + 1, and the refresh operation for the word line Wn + 1 is performed. Thereafter, at time t4 after the elapse of period T2 from time t3, the frequency-divided clock CLK4 output from the frequency divider 269 rises, and the third refresh operation is started by the row selection control signal as described above. Thereafter, the refresh operation is repeated at intervals of T2 from time t4 until the self-refresh control signal is set to “L” by the external input terminal (2). During the self-test, as described above, the internal self-refresh control signal is output as the row selection control signal and the row selection control signal is output to the external input / output terminal (0). explain. In FIG. 2, the row selection control signal is input to the selector 312. Since the self test signal is “H”, the row selection control signal is output by the selector 312 and input to the selector 313. Since the DRAM test signal is "H", the A input is selected by the selector 313, so the row selection control signal is input to the tristate buffer 317, and the self test signal is "H", so that the IO control signal (1 ) Becomes “H”, and the row selection control signal is output to the external input / output terminal (0).
[0031]
As described above, according to the present embodiment, as described with reference to FIG. 2, if the semiconductor device 1 is set to the self-refresh test mode of the DRAM 2 by the external test input terminal, the row selection signal is sent to the external input / output terminal ( 0), the self-refresh cycle is measured by the signal of the external input / output terminal (0) during the self-refresh test. Within the repairable range, defective products can be repaired by the following method, and the self-refresh circuit 250 can be tested in a short time.
[0032]
When the self-refresh period is longer than the standard, the period can be within the standard by shortening the self-refresh period by cutting the fuse 264 of FIG. 3 to shorten the oscillation period of CLK1. When the self-refresh cycle is shorter than the standard, the fuse 265 or the fuse 266 in FIG. 3 is cut to increase the oscillation cycle of CLK1, thereby increasing the self-refresh cycle, or the fuse 273 is cut. By setting the S input of the selector 271 to “L” and selecting CLK8, the self refresh cycle can be lengthened to select one of the methods, and the refresh cycle can be within the standard. Even when the self-refresh cycle is within the standard, the cycle setting can be trimmed to the maximum of the standard so that the current value during self-refresh is minimized. Further, by measuring the pulse width with the signal of the external input / output terminal (0) during the self-refresh test, if the pulse width is in a range that cannot be repaired by trimming, it is determined as a defective product. 3, the delay value of the first delay circuit 276 is relieved by trimming.
[0033]
As described with reference to FIG. 2, the external input / output terminal (0) that outputs the test data 0 during the data read test of the DRAM 2 has a circuit configuration that outputs a row selection control signal during the self-refresh test. ) And the row selection control signal also serve as the external input / output terminal (0), thereby reducing the number of external terminals during the DRAM test.
[0034]
【The invention's effect】
According to the present invention, a semiconductor device in which a memory and a logic circuit are integrated into one chip, and when an self-refresh control signal is input, an oscillation means for supplying an oscillation clock having a constant period; A signal generating means for supplying an internal self-refresh control signal for refreshing the memory cell based on the oscillation clock; A logic gate circuit that supplies a row selection control signal based on the internal self-refresh control signal during a self-refresh test and supplies the row selection control signal based on an input from an external input terminal during a data read test from a memory A row selection circuit for activating a word line selected by a row address in response to the row selection control signal; Above Row selection control signal And a signal output means for outputting a signal to an external terminal, so that a self-refresh circuit composed of the oscillation means and the signal generation means can be tested by a method of measuring the period and pulse width of the signal at the external terminal. I made it.
[0035]
As a result, a test of the self-refresh circuit can be performed in a short time, and a semiconductor device capable of optimizing the self-refresh cycle by trimming and repairing defective products can be realized.
[0036]
According to the present invention, the signal output means outputs the test data to the external terminal during the data read test from the memory, and the self-refresh test during the data read test. Row selection control signal By using a circuit configuration that outputs to the external terminal, a self-refresh test can be performed without increasing the DRAM test external terminals.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a semiconductor device according to the present invention.
FIG. 2 is a configuration diagram of a memory cell array and its peripheral circuits in a semiconductor device according to the present invention.
FIG. 3 is a configuration diagram of a self-refresh circuit in a semiconductor device according to the present invention.
FIG. 4 is a read timing chart in a page mode during a DRAM data read test.
FIG. 5 is an operation timing chart during a DRAM self-refresh test.
[Explanation of symbols]
1 Semiconductor device
2 DRAM
3 Memory cell array and peripheral circuit
4 Logic part
201-208, 229 selector
210 to 214, 230, 231 Inverter
215-218 D flip-flop
219 2-input AND circuit
220 3-input AND circuit
221,232 2-input OR circuit
222 3-input OR circuit
223 Timing generation circuit
224 refresh counter
225 row address latch
226 column address latch
227 byte address latch
228 Test decode circuit
250 Self-refresh circuit
251 Oscillator circuit

Claims (2)

A semiconductor device made into one chip,
A memory having memory cells that need to be refreshed to store data;
When a self-refresh control signal is input, an oscillating means for supplying an oscillation clock having a fixed period, and an internal self-refresh control signal for refreshing the memory cell based on the oscillation clock A signal selection means for supplying a row selection control signal based on the internal self-refresh control signal during a self-refresh test, and the row selection control signal based on an input from an external input terminal during a data read test from a memory. A logic gate circuit for supplying the data, a row selection circuit for activating a word line selected by a row address in response to the row selection control signal, and a signal output means for outputting the row selection control signal to an external terminal. A semiconductor device comprising: The semiconductor device according to claim 1,
The signal output means outputs test data to an external terminal during a data read test from a memory, and outputs the row selection control signal to an external terminal during a self-refresh test.

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