JP3629310B2 - Solid-state imaging device - Google Patents

Solid-state imaging device Download PDF

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JP3629310B2
JP3629310B2 JP25236195A JP25236195A JP3629310B2 JP 3629310 B2 JP3629310 B2 JP 3629310B2 JP 25236195 A JP25236195 A JP 25236195A JP 25236195 A JP25236195 A JP 25236195A JP 3629310 B2 JP3629310 B2 JP 3629310B2
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Japan
Prior art keywords
pixel
circuit
output signal
delay circuit
signal
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JP25236195A
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JPH0998346A (en
Inventor
部 信 須
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Description

【0001】
【産業上の利用分野】
本発明は、固体撮像素子の画素欠陥を補正する欠陥補正回路を備えた固体撮像装置に関するものである。
【0002】
【従来の技術】
固体撮像素子の画素欠陥を補正するために様々な方式が考案されている。また、特開昭63−310280号公報においては、画素欠陥長が2画素にまたがる場合にも対応できる方式が提案されている。
【0003】
以下、図3および図4を用いて従来の欠陥補正回路を備えた固体撮像装置について説明する。図3において、撮像素子1から周期Tで撮像信号が出力され、欠陥検出回路12に入力され、信号レベルの高い画素欠陥(白傷)と信号レベルの低い画素欠陥(黒傷)の検出が行なわれる。欠陥検出回路12の入力を画素欠陥と判断した場合は、欠陥時間検出回路13で欠陥が1画素幅か2画素幅か判断される。また、撮像素子1の出力は、遅延回路3、4、5、6でそれぞれ周期Tだけ遅延される。遅延回路3の出力信号と遅延回路5の出力信号は、合成回路14で1:1の比率で加算され、遅延回路4の出力信号を基準として1画素前および1画素後の信号から欠陥補正用の置換信号が作成される。遅延回路3の入力信号と遅延回路5の出力信号は、合成回路15で1:2の比率で加算され、遅延回路4の出力信号を基準として、1画素前および2画素後の信号から欠陥補正用の置換信号が作成される。遅延回路3の出力信号と遅延回路6の出力信号は、合成回路16で2:1の比率で加算され、遅延回路4の出力信号を基準として、2画素前および1画素後の信号から欠陥補正用の置換信号が作成される。遅延回路4の出力に欠陥がない場合は、切換回路17で遅延回路4の出力信号を選択して出力する。遅延回路4の出力に欠陥がある場合は、欠陥時間検出回路13から出力される欠陥補正信号で切換回路17を制御する。欠陥が1画素のみならば、切換回路17は1画素期間だけ合成回路14の出力信号を出力する。欠陥が2画素にまたがる場合は、1画素目で合成回路15の出力信号を出力し、2画素目で合成回路16の出力信号を出力する。
【0004】
以上の動作を図4(a)および(b)のタイミング図を用いて説明する。図4の(a)に欠陥画素が1画素のみの場合を示す。撮像素子1から周期Tで撮像信号が出力され、a4の画素が欠陥画素とすると、欠陥補正信号によりa4の画素は(a3+a5)/2の画素に置換されて出力される。図4の(b)に欠陥画素が2画素のまたがる場合を示す。1画素目の欠陥をa3とすると、欠陥補正信号によりa3の画素は(2*a2+a5)/3の画素に置換され、2画素目の欠陥のa4は(a2+2*a5)/3の画素に置換される。
【0005】
【発明が解決しようとする課題】
しかしながら、上記従来の欠陥補正回路を備えた固定撮像装置では、欠陥画素を検出した後、さらに欠陥画素の長さが1画素なのか2画素なのか必ず判断して補正する必要がある。固体撮像素子で水平方向にn画素(n≧2の自然数)の混合読み出しを行なう場合には、欠陥画素の長さは必ずn画素以上となるとともに、nが大きくなるほど欠陥画素が欠陥の無い画素と混合されるため、欠陥画素が周辺画素と平均化されて欠陥の検出が困難になるという問題があった。
【0006】
本発明は、このような従来の問題を解決するものであり、通常の1画素読み出しの欠陥画素位置情報から固体撮像素子で水平方向にn画素の混合読み出しを行なった場合でも、欠陥画素の位置を判断して欠陥画素の信号成分が混合された画素を欠陥画素の信号成分がない信号を用いて置換することにより、欠陥画素を確実に補正することのできる欠陥補正回路を備えた固体撮像装置を提供することを目的とする。
【0007】
【課題を解決するための手段】
上記目的を達成するために、本発明の撮像装置は、水平方向の1画素単位の読み出し及び2画素単位の読み出しを行なう固体撮像素子と、前記固体撮像素子からの出力信号を遅延する第1の遅延回路と、前記第1の遅延回路からの出力信号を遅延する第2の遅延回路と、前記第2の遅延回路からの出力信号を遅延する第3の遅延回路と、前記第3の遅延回路からの出力信号を遅延する第4の遅延回路と、前記固体撮像素子からの出力信号と前記第1の遅延回路からの出力信号とを切り換える第1の切換回路と、前記第3の遅延回路からの出力信号と前記第4の遅延回路からの出力信号とを切り換える第2の切換回路と、前記第1の切換回路からの出力信号と前記第2の切換回路からの出力信号とを任意の比率で合成する合成回路と、前記第2の遅延回路からの出力信号と前記合成回路からの出力信号とを切り換える第3の切換回路と、前記第2の遅延回路からの出力信号に欠陥がある場合に欠陥補正信号を前記第3の切換回路へ出力する欠陥補正制御回路とを備え、前記固体撮像素子が水平方向の1画素単位の読み出しを行なうときは、前記第1の切換回路で前記第1の遅延回路からの出力信号を選択し、前記第2の切換回路で前記第3の遅延回路からの出力信号を選択し、前記固体撮像素子が水平方向の2画素単位の読み出しを行なうときは、前記第1の切換回路で前記固体撮像素子からの出力信号を選択し、前記第2の切換回路で前記第4の遅延回路からの出力信号を選択し、前記欠陥補正制御回路が欠陥補正信号を出力したときは、前記第3の切換回路で前記合成回路からの出力信号を選択することを特徴とするものである。
【0009】
【作用】
したがって本発明によれば、撮像素子で水平方向のn画素の混合読み出しを行なう時は、通常の1画素読み出しの欠陥画素位置情報から欠陥画素と混合された画素の位置情報を判断して、欠陥画素の信号成分を含む画素をn画素前およびn画素後から作成された欠陥補正用の信号と置換することにより、欠陥画素を確実に補正することができるという作用を有する。
【0010】
【実施例】
以下、本発明の実施例について図1および図2を参照しながら説明する。図1は本発明の一実施例における固体撮像装置の構成を示すブロック図である。図1において、1は周期Tで撮像信号を出力する撮像素子、2は撮像素子の画素欠陥を補正する欠陥補正回路、3、4、5、6は撮像信号を周期T遅延する遅延回路、7、8、10は信号入力のうち任意の1信号を出力するそれぞれ第1、第2、第3の切換回路、9は合成としての加算器、11は撮像素子の画素欠陥に合わせて欠陥補正信号を出力する欠陥補正制御回路である。
【0011】
以下、実施例において、撮像素子1が通常の1画素単位で読み出しを行なう時の欠陥補正回路2の動作について説明する。図1において、撮像素子1から周期Tで撮像信号が出力され、欠陥補正回路2に入力される。欠陥補正回路2では、遅延回路3、4、5、6で撮像信号をそれぞれ周期Tだけ遅延する。第1の切換回路7で遅延回路3の出力信号を、第2の切換回路8で遅延回路5の出力信号を出力する。第1、第2の切換回路7、8の出力信号は、加算器9に入力されて加算され、遅延回路4の出力信号を基準として1画素前および1画素後の信号から欠陥補正用の置換信号が作成される。遅延回路4の出力の欠陥の有無は、あらかじめ欠陥補正制御回路11に設定されており、欠陥がない場合は、欠陥補正制御回路11の制御により、第3の切換回路10で遅延回路4の出力信号を選択して出力する。遅延回路4の出力に欠陥がある場合は、欠陥補正制御回路11から切換回路10へ欠陥補正信号が出力され、第3の切換回路10で加算器9の出力信号つまり欠陥補正用の置換信号を選択して出力することにより撮像素子1の画素欠陥が補正される。
【0012】
以上の動作を図解すると、図2(a)に示すように、撮像素子1からは周期Tで撮像信号が出力され、b4の画素が欠陥画素とすると、欠陥補正信号により、b4の画素は(b3+b5)/2の画素に置換されて出力される。
【0013】
次に撮像素子1が水平方向の2画素混合読み出しを行なう時の欠陥補正回路2の動作について説明する。図1において、撮像素子1から周期Tで撮像信号が出力され、欠陥補正回路2に入力される。欠陥補正回路2では、遅延回路3、4、5、6で撮像信号をそれぞれ周期Tだけ遅延する。第1の切換回路7で欠陥補正回路2の入力信号を、第2の切換回路8で遅延回路6の出力信号を出力する。第1、第2の切換回路7、8の出力信号は、加算器9に入力されて加算され、遅延回路4の出力信号を基準として2画素前および2画素後の信号から欠陥補正用の置換信号が作成される。遅延回路4の出力の欠陥の有無は、通常の1画素読み出しの欠陥画素位置情報から求められ、遅延回路4の出力に欠陥がない場合は、第3の切換回路10で遅延回路4の出力信号を選択して出力する。遅延回路4の出力に欠陥がある場合は、欠陥補正制御回路11から切換回路10へ欠陥補正信号が出力され、切換回路10で加算器9の出力信号つまり欠陥補正用の置換信号を選択して出力することにより撮像素子1の画素欠陥が補正される。
【0014】
以上の動作を図解すると、図2(b)および(c)に示すようになる。撮像素子1内で欠陥画素b4は、水平方向に混合されて読み出されるため、同図(b)の撮像素子出力のように画素b3と混合される場合と、同図(c)の撮像素子出力のように画素b5と混合される場合の2通りの出力が考えられる。通常の1画素単位の読み出しにおける欠陥画素の水平位置はあらかじめ検出されており、また撮像素子1が2画素の混合読み出しを行なう時は、水平方向にどの画素同士が混合されるかあらかじめ決まっているため、容易に求めることができる。一例として水平位置が”1”の画素と水平位置が”2”の画素が混合される場合、水平位置が”m”の画素は、m/2のあまりが0の時は1画素前の画素と混合され、あまりが1の場合は1画素後の画素と混合される。このようにして2画素の混合読み出し時に欠陥画素が前後どちらの画素と混合されるかが求まる。これにより同図(b)の場合、欠陥画素b4は1画素前の画素b3と混合され、これに対応した欠陥補正信号により、b3の画素は(b1+b2)/2+(b5+b6)/2の画素に置換され、b4の画素も(b1+b2)/2+(b5+b6)/2の画素に置換されて出力される。b1とb2およびb5とb6の画素は予め混合されているため、欠陥画素を含む2画素の前後の2画素を1/2ずつ取り込むことにより、b3とb4は同じ信号で置換されたこととなる。同図(c)の場合、欠陥画素b4は1画素後の画素b5と混合され、これに対応した欠陥補正信号により、b4の画素は(b2+b3)/2+(b6+b7)/2の画素に置換され、b5の画素も(b2+b3)/2+(b6+b7)/2の画素に置換されて出力される。b2とb3およびb6とb7の画素は予め混合されているため、欠陥画素を含む2画素の前後の2画素を1/2ずつ取り込むことにより、b4とb5は同じ信号で置換されたこととなる。
【0015】
同様に撮像素子1が水平方向のn画素混合読み出しを行なう時は、あらかじめ検出されている通常の1画素単位の読み出しの欠陥画素の水平位置mからm/nのあまりを求めることで、欠陥画素が前後何画素ずつと混合されるかを求め、n画素前およびn画素後の信号から欠陥補正用の置換信号を作成するとともに、欠陥補正制御回路11の出力信号を混合された画素と対応するようにn画素幅として混合された欠陥画素を置換することにより、n画素の混合読み出しに対応した画素欠陥の補正を行なうことができる。
【0016】
このようにして、撮像素子で水平方向の混合読み出しを行なう撮像装置1においても、通常の1画素単位の読み出しを行なう時は、従来と同様に欠陥画素の1画素前および1画素後から欠陥補正用の置換信号を作成し、n画素の混合読み出しを行なう時は、欠陥画素および欠陥画素と混合された画素をそれぞれのn画素前およびn画素後から欠陥補正用の置換信号を作成するとともに、欠陥補正信号を欠陥画素の混合される方向にn画素幅として混合された欠陥画素を置換することにより完全な補正を行なうことができる。
【0017】
【発明の効果】
本発明は、上記実施例から明らかなように、固体撮像装置で水平方向のn画素の混合読み出しを行なう時は、欠陥画素のn画素前およびn画素後から欠陥補正用の置換信号を作成して欠陥画素および欠陥画素と混合された画素を置換することにより、欠陥画素を確実に補正することができるという利点を有する。
【図面の簡単な説明】
【図1】本発明の一実施例における固体撮像装置の構成を示すブロック図
【図2】本発明の一実施例における固体撮像装置の動作を示すタイミング図
【図3】従来の固体撮像装置の構成を示すブロック図
【図4】従来の固体撮像装置の動作を示すタイミング図
【符号の説明】
1 撮像装置
2 欠陥補正回路
3,4,5,6 遅延回路
7 第1の切換回路
8 第2の切換回路
9 加算器(合成回路)
10 第3の切換回路
11 欠陥補正制御回路
[0001]
[Industrial application fields]
The present invention relates to a solid-state imaging device including a defect correction circuit that corrects a pixel defect of a solid-state imaging device.
[0002]
[Prior art]
Various schemes have been devised for correcting pixel defects in solid-state imaging devices. Japanese Laid-Open Patent Publication No. 63-310280 proposes a method that can cope with a case where the pixel defect length extends over two pixels.
[0003]
Hereinafter, a solid-state imaging device including a conventional defect correction circuit will be described with reference to FIGS. 3 and 4. In FIG. 3, an image pickup signal is output from the image pickup device 1 with a period T and is input to the defect detection circuit 12 to detect a pixel defect having a high signal level (white flaw) and a pixel defect having a low signal level (black flaw). It is. When it is determined that the input of the defect detection circuit 12 is a pixel defect, the defect time detection circuit 13 determines whether the defect is 1 pixel width or 2 pixel width. In addition, the output of the image sensor 1 is delayed by a period T in each of the delay circuits 3, 4, 5, and 6. The output signal of the delay circuit 3 and the output signal of the delay circuit 5 are added at a ratio of 1: 1 by the synthesis circuit 14 and are used for defect correction from the signals one pixel before and one pixel after the output signal of the delay circuit 4 as a reference. Replacement signals are generated. The input signal of the delay circuit 3 and the output signal of the delay circuit 5 are added at a ratio of 1: 2 by the synthesis circuit 15, and defect correction is performed based on the signals before and after two pixels with reference to the output signal of the delay circuit 4. A replacement signal for is created. The output signal of the delay circuit 3 and the output signal of the delay circuit 6 are added at a ratio of 2: 1 by the synthesizing circuit 16, and defect correction is performed from the signals two pixels before and after one pixel on the basis of the output signal of the delay circuit 4. A replacement signal for is created. When the output of the delay circuit 4 is not defective, the switching circuit 17 selects and outputs the output signal of the delay circuit 4. When the output of the delay circuit 4 is defective, the switching circuit 17 is controlled by the defect correction signal output from the defect time detection circuit 13. If the defect is only one pixel, the switching circuit 17 outputs the output signal of the synthesis circuit 14 for one pixel period. When the defect extends over two pixels, the output signal of the synthesis circuit 15 is output at the first pixel, and the output signal of the synthesis circuit 16 is output at the second pixel.
[0004]
The above operation will be described with reference to the timing charts of FIGS. FIG. 4A shows a case where there is only one defective pixel. If an imaging signal is output from the imaging device 1 with a period T and the pixel a4 is a defective pixel, the pixel a4 is replaced with a pixel of (a3 + a5) / 2 by the defect correction signal and output. FIG. 4B shows a case where the defective pixel extends over two pixels. Assuming that the defect of the first pixel is a3, the defect correction signal replaces the pixel of a3 with a pixel of (2 * a2 + a5) / 3, and the defect of the second pixel with a4 is replaced with a pixel of (a2 + 2 * a5) / 3 Is done.
[0005]
[Problems to be solved by the invention]
However, in the fixed imaging device having the above-described conventional defect correction circuit, after detecting a defective pixel, it is necessary to make a correction by determining whether the length of the defective pixel is one pixel or two pixels. In the case of performing mixed readout of n pixels (n ≧ 2 natural number) in the horizontal direction with a solid-state imaging device, the length of the defective pixel is always n pixels or more, and as n increases, the defective pixel has no defect. As a result, the defective pixels are averaged with the peripheral pixels, which makes it difficult to detect the defects.
[0006]
The present invention solves such a conventional problem, and the position of the defective pixel is obtained even when the mixed reading of n pixels in the horizontal direction is performed by the solid-state imaging device from the defective pixel position information of normal one-pixel reading. Solid-state imaging device having a defect correction circuit that can reliably correct a defective pixel by replacing a pixel mixed with the signal component of the defective pixel with a signal having no signal component of the defective pixel The purpose is to provide.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, an imaging apparatus of the present invention includes a solid-state imaging device that performs horizontal readout in units of one pixel and readout in units of two pixels, and a first that delays an output signal from the solid-state imaging device. A delay circuit; a second delay circuit that delays an output signal from the first delay circuit; a third delay circuit that delays an output signal from the second delay circuit; and the third delay circuit. A fourth delay circuit that delays an output signal from the first delay circuit, a first switching circuit that switches an output signal from the solid-state imaging device and an output signal from the first delay circuit, and the third delay circuit. A second switching circuit that switches between the output signal from the first delay circuit and the output signal from the fourth delay circuit, and an arbitrary ratio between the output signal from the first switching circuit and the output signal from the second switching circuit. And a synthesis circuit for synthesizing with the second A third switching circuit for switching an output signal from the delay circuit and an output signal from the synthesis circuit; and a defect correction signal when the output signal from the second delay circuit is defective. And when the solid-state imaging device performs readout in units of pixels in the horizontal direction, the output signal from the first delay circuit is selected by the first switching circuit, When the output signal from the third delay circuit is selected by the second switching circuit and the solid-state imaging device reads out in units of two pixels in the horizontal direction, the solid-state imaging device is used by the first switching circuit. When the output signal from the fourth delay circuit is selected by the second switching circuit and the defect correction control circuit outputs a defect correction signal, the third switching circuit is selected. From the synthesis circuit It is characterized in selecting the force signal.
[0009]
[Action]
Therefore, according to the present invention, when performing horizontal readout of n pixels in the image sensor, the position information of the pixels mixed with the defective pixels is determined from the defective pixel position information of normal one-pixel readout, and the defect is detected. By replacing the pixel including the signal component of the pixel with a defect correction signal generated after n pixels and after n pixels, the defective pixel can be reliably corrected.
[0010]
【Example】
Hereinafter, embodiments of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a solid-state imaging device according to an embodiment of the present invention. In FIG. 1, 1 is an image sensor that outputs an imaging signal at a period T, 2 is a defect correction circuit that corrects a pixel defect of the image sensor, 3, 4, 5, and 6 are delay circuits that delay the imaging signal by a period T, 7 , 8 and 10 are first, second and third switching circuits for outputting any one of the signal inputs, 9 is an adder as a composition, and 11 is a defect correction signal in accordance with a pixel defect of the image sensor. Is a defect correction control circuit that outputs.
[0011]
Hereinafter, in the embodiment, the operation of the defect correction circuit 2 when the image pickup device 1 performs reading in a normal pixel unit will be described. In FIG. 1, an image pickup signal is output from the image pickup device 1 with a period T and is input to the defect correction circuit 2. In the defect correction circuit 2, the imaging signals are delayed by the period T in the delay circuits 3, 4, 5, and 6, respectively. The first switching circuit 7 outputs the output signal of the delay circuit 3, and the second switching circuit 8 outputs the output signal of the delay circuit 5. The output signals of the first and second switching circuits 7 and 8 are input to the adder 9 and added, and the defect correction replacement is performed from the signal before and after one pixel on the basis of the output signal of the delay circuit 4. A signal is created. The presence or absence of a defect in the output of the delay circuit 4 is set in advance in the defect correction control circuit 11. If there is no defect, the output of the delay circuit 4 is output by the third switching circuit 10 under the control of the defect correction control circuit 11. Select and output the signal. If the output of the delay circuit 4 is defective, a defect correction signal is output from the defect correction control circuit 11 to the switching circuit 10, and the third switching circuit 10 outputs an output signal of the adder 9, that is, a defect correction replacement signal. The pixel defect of the image sensor 1 is corrected by selecting and outputting.
[0012]
Explaining the above operation, as shown in FIG. 2A, when the imaging signal is output from the imaging device 1 with a period T and the pixel b4 is a defective pixel, the pixel b4 is ( b3 + b5) / 2 pixels are substituted and output.
[0013]
Next, the operation of the defect correction circuit 2 when the image sensor 1 performs the two-pixel mixed readout in the horizontal direction will be described. In FIG. 1, an image pickup signal is output from the image pickup device 1 with a period T and is input to the defect correction circuit 2. In the defect correction circuit 2, the imaging signals are delayed by the period T in the delay circuits 3, 4, 5, and 6, respectively. The first switching circuit 7 outputs the input signal of the defect correction circuit 2, and the second switching circuit 8 outputs the output signal of the delay circuit 6. The output signals of the first and second switching circuits 7 and 8 are input to the adder 9 and added, and the defect correction replacement is performed from the signals before and after two pixels with reference to the output signal of the delay circuit 4. A signal is created. The presence / absence of a defect in the output of the delay circuit 4 is obtained from defective pixel position information of normal one-pixel readout. If there is no defect in the output of the delay circuit 4, the third switching circuit 10 outputs the output signal of the delay circuit 4 Select to output. When the output of the delay circuit 4 is defective, a defect correction signal is output from the defect correction control circuit 11 to the switching circuit 10, and the switching circuit 10 selects an output signal of the adder 9, that is, a replacement signal for defect correction. By outputting, the pixel defect of the image sensor 1 is corrected.
[0014]
The above operation is illustrated in FIGS. 2B and 2C. Since the defective pixel b4 is mixed and read out in the horizontal direction in the image pickup device 1, the defective pixel b4 is mixed with the pixel b3 like the image pickup device output in FIG. 5B, and the image pickup device output in FIG. As described above, two kinds of outputs when mixed with the pixel b5 are conceivable. The horizontal position of the defective pixel in normal pixel-by-pixel readout is detected in advance, and when the image sensor 1 performs mixed readout of two pixels, it is determined in advance which pixels are mixed in the horizontal direction. Therefore, it can be easily obtained. As an example, when a pixel whose horizontal position is “1” and a pixel whose horizontal position is “2” are mixed, the pixel whose horizontal position is “m” is the pixel one pixel before when m / 2 is too zero. If too much is 1, it is mixed with the pixel after one pixel. In this way, it can be determined whether the defective pixel is mixed with the preceding or subsequent pixel at the time of the mixed reading of the two pixels. As a result, in the case of FIG. 5B, the defective pixel b4 is mixed with the previous pixel b3, and the pixel b3 is changed to the pixel (b1 + b2) / 2 + (b5 + b6) / 2 by the defect correction signal corresponding thereto. The pixel of b4 is also replaced with the pixel of (b1 + b2) / 2 + (b5 + b6) / 2 and output. Since b1 and b2 and b5 and the pixels of b6 are premixed by incorporating two pixels before and after the two pixels including the defective pixel by 1/2, I and be b3 and b4 is substituted by the same signal The In the case of FIG. 6C, the defective pixel b4 is mixed with the pixel b5 after one pixel, and the pixel of b4 is replaced with the pixel of (b2 + b3) / 2 + (b6 + b7) / 2 by the defect correction signal corresponding thereto. , B5 are also replaced with (b2 + b3) / 2 + (b6 + b7) / 2 pixels and output. Since the pixels b2 and b3 and b6 and b7 are premixed by incorporating two pixels before and after the two pixels including the defective pixel by 1/2, I and it b4 and b5 is substituted by the same signal The
[0015]
Similarly, when the image pickup device 1 performs the n-pixel mixed readout in the horizontal direction, the defective pixel is obtained by obtaining the excess of m / n from the horizontal position m of the normal read-out defective pixel in units of one pixel. Is calculated by the number of pixels before and after the pixel, and a replacement signal for defect correction is generated from the signals before and after n pixels, and the output signal of the defect correction control circuit 11 corresponds to the mixed pixel. Thus, by replacing defective pixels mixed as n pixel widths, it is possible to correct pixel defects corresponding to mixed reading of n pixels.
[0016]
In this way, in the image pickup apparatus 1 that performs mixed read in the horizontal direction by the image pickup device, when normal one-pixel unit reading is performed, defect correction is performed from one pixel before and after one defective pixel as in the conventional case. When creating a replacement signal for n pixels and performing a mixed readout of n pixels, a defective signal and a pixel mixed with the defective pixel are created before and after each n pixels, and a defect correction replacement signal is created. A complete correction can be performed by replacing the defective pixel mixed with an n pixel width in the direction in which the defective pixels are mixed in the defect correction signal.
[0017]
【The invention's effect】
As is clear from the above embodiments, the present invention creates a replacement signal for defect correction before and after n pixels of a defective pixel when mixed readout of n pixels in the horizontal direction is performed in a solid-state imaging device. By replacing the defective pixel and the pixel mixed with the defective pixel, there is an advantage that the defective pixel can be reliably corrected.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a solid-state imaging device according to an embodiment of the present invention. FIG. 2 is a timing diagram illustrating an operation of the solid-state imaging device according to an embodiment of the present invention. FIG. 4 is a timing diagram showing the operation of a conventional solid-state imaging device.
DESCRIPTION OF SYMBOLS 1 Image pick-up device 2 Defect correction circuit 3, 4, 5, 6 Delay circuit 7 1st switching circuit 8 2nd switching circuit 9 Adder (synthesis | combination circuit)
10 Third switching circuit 11 Defect correction control circuit

Claims (1)

水平方向の1画素単位の読み出し及び2画素単位の読み出しを行なう固体撮像素子と、前記固体撮像素子からの出力信号を遅延する第1の遅延回路と、前記第1の遅延回路からの出力信号を遅延する第2の遅延回路と、前記第2の遅延回路からの出力信号を遅延する第3の遅延回路と、前記第3の遅延回路からの出力信号を遅延する第4の遅延回路と、前記固体撮像素子からの出力信号と前記第1の遅延回路からの出力信号とを切り換える第1の切換回路と、前記第3の遅延回路からの出力信号と前記第4の遅延回路からの出力信号とを切り換える第2の切換回路と、前記第1の切換回路からの出力信号と前記第2の切換回路からの出力信号とを任意の比率で合成する合成回路と、前記第2の遅延回路からの出力信号と前記合成回路からの出力信号とを切り換える第3の切換回路と、前記第2の遅延回路からの出力信号に欠陥がある場合に欠陥補正信号を前記第3の切換回路へ出力する欠陥補正制御回路とを備え、
前記固体撮像素子が水平方向の1画素単位の読み出しを行なうときは、前記第1の切換回路で前記第1の遅延回路からの出力信号を選択し、前記第2の切換回路で前記第3の遅延回路からの出力信号を選択し、
前記固体撮像素子が水平方向の2画素単位の読み出しを行なうときは、前記第1の切換回路で前記固体撮像素子からの出力信号を選択し、前記第2の切換回路で前記第4の遅延回路からの出力信号を選択し、
前記欠陥補正制御回路が欠陥補正信号を出力したときは、前記第3の切換回路で前記合成回路からの出力信号を選択することを特徴とする固体撮像装置。
A solid-state imaging device that performs horizontal readout in units of one pixel and readout in units of two pixels, a first delay circuit that delays an output signal from the solid-state imaging device, and an output signal from the first delay circuit A second delay circuit that delays; a third delay circuit that delays an output signal from the second delay circuit; a fourth delay circuit that delays an output signal from the third delay circuit; A first switching circuit that switches between an output signal from the solid-state imaging device and an output signal from the first delay circuit; an output signal from the third delay circuit; and an output signal from the fourth delay circuit; A second switching circuit that switches between the output signal from the first switching circuit and the output signal from the second switching circuit at an arbitrary ratio, and from the second delay circuit Output signal and output from the synthesis circuit Includes a third switching circuit for switching a signal, and a defect correction control circuit for outputting a defect correction signal when there is a defect in the output signal from said second delay circuit to the third switching circuit,
When the solid-state imaging device reads out in units of pixels in the horizontal direction, the first switching circuit selects an output signal from the first delay circuit, and the second switching circuit selects the third switching circuit. Select the output signal from the delay circuit,
When the solid-state imaging device reads out in units of two pixels in the horizontal direction, the first switching circuit selects an output signal from the solid-state imaging device, and the second switching circuit selects the fourth delay circuit. Select the output signal from
When the defect correction control circuit outputs a defect correction signal, an output signal from the synthesis circuit is selected by the third switching circuit.
JP25236195A 1995-09-29 1995-09-29 Solid-state imaging device Expired - Fee Related JP3629310B2 (en)

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