JP3627087B2 - Programmable controller and control method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a programmable controller capable of high-speed processing, easy to create a sequence program, divert it to another system, change the system, and the like, and a control method therefor.
[0002]
[Prior art]
FIG. 13 is a system configuration diagram of a high-speed I / O unit using a pattern table described in JP-A No. 64-44509. In the figure, 18 is an I / O bus, 19 is an EPROM, 20 is an input circuit, and 21 is an output circuit.
In this conventional system, a signal from an external absolute encoder (not shown) is received by the input circuit 20 and converted based on the conversion table stored in the memory of the EPROM 19, and the conversion result is output to the output circuit 21. And external devices (not shown) are controlled at high speed. If necessary, the conversion result is sent to the PC control unit via the I / O bus 18. In this way, the signal from the absolute encoder is processed at high speed.
[0003]
FIG. 14 is a block diagram showing another conventional system, and shows a conventional system for moving a belt conveyor forward and backward. In the figure, 22 is a CPU unit, 28 is a forward drive contact, 29 is a motor, 30 is a reverse drive contact, 31 is a belt conveyor, 32 is a forward end sensor, and 33 is a reverse end sensor.
The device names on the sequence programs of the forward operation contact 28 and the reverse operation contact 30 which are output devices, and the forward end sensor 32 and the reverse end sensor 33 which are input devices are Y50, Y51, X0 and X1, respectively. For example, ON / OFF information is stored in the device memory 232 in the CPU unit 22 at addresses specified by Y50, Y51, X0, and X1, respectively.
FIG. 15 is a diagram illustrating a state in which the CPU unit 22 and the like are mounted in a slot provided in a programmable controller (hereinafter referred to as a PC). In the figure, 17 is an input unit having 16 input points, and 34 is an output unit having 16 output points.
[0004]
FIG. 16 is a diagram showing a sequence program represented by a ladder diagram. This sequence program is executed by the CPU unit 22.
In FIG. 16, in step S151, if T0 is not ON, the routine jumps to P0 (step S154) assuming that normal processing is performed. T0 is set when there is a cycle time over.
In step S152, if M0 is already ON in the previous scan, the process jumps to step S154 so that the CHK instruction is not executed again.
In step S153, the CHK instruction is executed if the cycle time over has occurred during the forward / reverse operation, and the failure diagnosis of the operation abnormality detection circuit is performed, and M0 is set if there is a failure.
In step S154, the forward operation is performed under the condition that the conveyor advance command (X4) is turned ON, etc., and Y0 used for failure detection (in this PC, an output device having the same contact number as the contact number of the forward end sensor is set. ) Is turned on.
In step S155, the reverse operation is performed on the condition that the conveyor backward command (X5) is ON, and Y0 is turned OFF.
In step S156, the cycle time check timer is operated, and if the forward end or the reverse end is not reached within the set time, an error is determined and T0 is turned ON.
With the above operation, Y0 is turned on during forward operation and turned off during reverse operation. Also, a failure check of the operation abnormality detection circuit is performed by executing the CHK instruction. When a failure is detected, the device M0 is turned on, and the failure number is stored in the device D0 as a BCD value. The contact (X0) in step S153 does not control the execution of the CHK instruction, but is a contact for setting a check condition. In this PC, the CHK instruction is determined to be described in the step of the pointer P254.
[0005]
In such a conventional PC, it is necessary to create a sequence program that reflects the I / O allocation after determining the allocation of I / O points and the arrangement of units. When changed, it was necessary to change the device name of the sequence program.
[0006]
FIG. 17 is a connection diagram of a conventional network system in which a plurality of PCs are network-connected. In the figure, reference numeral 231 denotes a sequence program memory in which a sequence program executed by the CPU unit 22 is stored, 232 a device memory, 24 a network unit, 25 an I / O unit, and 26 an I / O bus.
In this network system, a plurality of PCs are connected to each other by a coaxial bus 27 via a network unit 24 so that data can be exchanged between the PCs. A command is given to each I / O unit 25 via the / O bus 26. Each PC is provided with an area for storing a shared device (a device that needs to be accessed between PCs) in the device memory 232, and the stored contents of the device memory 232 are periodically refreshed.
[0007]
[Problems to be solved by the invention]
In the conventional system as shown in FIG. 13, for example, high-speed control using a timer or counter, that is, high-speed control depending on the previous state (high-speed control that changes processing contents depending on the on / off state of the timer or the count state of the counter) When it is necessary, it is difficult to deal with, and there are problems in terms of flexibility, versatility, ease of programming, and the like. In addition, there is a problem that a target that can be processed at high speed is limited to a specific function.
[0008]
Further, in the conventional system shown in FIG. 14, all the processing performed by the I / O unit 25 is described in the sequence program executed by the CPU unit 22, so that the device name necessary for the processing performed by the I / O unit 25 is set. It was necessary to create a sequence program with everything properly defined. In addition, when diverting a sequence program from another system, there is a problem that it is necessary to rewrite the device name on the sequence program in accordance with the own system.
In addition, the sequence program executed by the CPU unit 22 is lengthened and the response speed of the PC is hindered.
[0009]
The present invention has been made to solve the above-described problems, and prevents an increase in the scan time of the CPU unit to improve the throughput of the entire system, and the processing speed and response in the I / O unit. The purpose is to prevent a decrease in speed.
[0010]
Another object of the present invention is to facilitate the creation of sequence programs, system changes, and diversion of sequence programs.
[0011]
[Means for Solving the Problems]
A programmable controller according to the present invention is a programmable controller including a PC main unit and a predetermined number of I / O units.
The I / O unit includes a first storage unit that stores device information indicating a state of an input / output device provided for a control target, and a first sequence program in which a storage address of the device information in the first storage unit is described The first control means for controlling the controlled object via the first storage means by repeatedly executing the interface, and the interface exchanged between the PC main body units among the device information whose storage address is described in the first sequence program Second storage means for storing an interface program in which a storage address of device information is described;
The PC main body unit creates a first table indicating the correspondence between the storage address in the first storage means and the storage address in the third storage means for the storage address of the third storage means and the interface device information, and the interface device in the interface program The information storage address is converted into an address in the PC main unit, the second sequence program having the converted interface program and its own sequence program is repeatedly executed, and in addition to predetermined control by the own sequence program, I Second control means for controlling the / O unit via the third storage means,
Based on the first table, the stored contents of the first and third storage means are refreshed so that the stored contents of the first and third storage means become the same for the interface device information. The data is transferred from the unit to the PC main unit.
[0012]
In addition, the I / O unit has fourth storage means for storing the name of its own unit, and the stored contents of the fourth storage means in the I / O unit inserted in each slot are read when the power is turned on. The second table showing the correspondence between the name and the slot number in which the I / O unit is inserted is created by the second control means, and the second control means recognizes the slot number corresponding to the name by the second table. It is what I did.
[0013]
According to the programmable controller control method of the present invention, the first control means stores the first sequence program in which the storage address in the first storage means of the device information indicating the state of the input / output device provided in the control target is described. The storage address in the first storage means of the interface device information that is exchanged between the PC main body units among the device information from the I / O unit that controls the control object via the first storage means by repeatedly executing to the PC main body unit. Is transferred, and the first table showing the correspondence between the storage address in the first storage unit of the I / O unit and the storage address in the third storage unit of the PC main unit is provided for the interface device information. 2 Created by the control means, A step of storing addresses in the I / O unit interface device information in interface program is converted in the storage address in the PC main unit by the second control means,
A second sequence program having the converted interface program and its own sequence program is executed by the second control means so that the contents stored in the first and third storage means are the same for the interface device information based on the first table. In addition, the stored contents of the first and third storage means are refreshed, and the I / O unit is controlled by the interface program via the third storage means in addition to the predetermined control by its sequence program, It is made to have.
[0014]
A stage in which the name of the own unit is stored in the fourth storage means of the I / O unit;
The stored contents of the fourth storage means in the I / O unit inserted in each slot are read, and the second table indicating the correspondence between the name and the slot number in which the I / O unit is inserted is the second control. A stage created by means;
A slot number corresponding to the name based on the second table is recognized by the second control means.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a block diagram of an I / O unit according to an embodiment of the present invention. This I / O unit is mounted in a slot provided in the PC.
In the figure, 1 is an I / O bus, 8 is an I / O unit, 201 is a sequence program memory (denoted as SP memory in the figure) in the I / O unit 8, and a first sequence program, for example, I / O unit A sequence program executed by the O unit 8 is stored. Reference numeral 202 denotes second storage means in the I / O unit 8, for example, an interface sequence program memory (indicated as I / F • SP memory in the figure), which stores an interface sequence program to be transferred to the CPU unit 6. Reference numeral 203 denotes first storage means provided in the I / O unit 8, for example, a device memory. Reference numeral 3 denotes first control means, for example, a control device. 4 is an input circuit, and 5 is an output circuit. The control device 3 repeatedly executes the sequence program stored in the sequence program memory 201. Signal transmission / reception between the I / O unit 8 and the CPU unit 6 is performed via the I / O bus 1.
[0016]
FIG. 2 is a block diagram of a PC main unit, for example, a CPU unit according to the first embodiment of the present invention.
In the figure, 6 is a CPU unit, 701 is a sequence program memory in the CPU unit 6, and stores a sequence program executed by the CPU unit 6. Reference numeral 702 denotes third storage means, for example, a device memory in the CPU unit 6. Reference numeral 703 denotes a scratch memory, and reference numeral 704 denotes second control means such as a control device.
FIG. 3 is a block configuration diagram of a system in which a CPU unit 6 and a plurality of I / O units 8 are connected by an I / O bus 1.
[0017]
Next, an overview of the system shown in FIG. 3 will be described. In this system, first, an interface program, for example, an interface sequence program is read from the interface sequence program memory 202 of the I / O unit 8 and sent to the CPU unit 6. The device number (device number on the I / O unit 8) described in the interface sequence program is converted into a device number on the CPU unit 6. The converted interface sequence program is added to the sequence program of the CPU unit 6 and executed as a part of the sequence program of the CPU unit 6.
Since the I / O unit 8 is a single component, the device number in the interface sequence program stored in the interface sequence program memory 202 of the I / O unit 8 is fixed, and this interface sequence program is loaded into the CPU unit 6. Is automatically converted into a device number in the CPU unit 6 as will be described later.
As described above, since the device number is converted at the time of loading, it is not necessary to convert it at the time of execution of the sequence program, and a decrease in processing speed when a device ON / OFF command is sent to the I / O unit 8 is prevented. The
[0018]
FIG. 4 is a flowchart showing the operation when the CPU unit 6 reads the interface sequence program stored in the memory of the I / O unit 8 when the power is turned on, that is, when loading.
The conversion of the device number at the time of loading is performed when the CPU unit 6 has a total number of occupied points of all slots having a slot number younger than the slot number of the I / O unit 8 (if the unit is mounted, the number of occupied points of the slot is This is performed by adding the number of points occupied by the unit, 16 points if the slot is empty) and the device number in the I / O unit 8.
For example, in a state where a unit occupying 16 points in slot 0 is mounted, when I / O unit 8 is inserted into slot 1, the device of device number 0 of this I / O unit 8 is the CPU unit. The device number in 6 is 10.
[0019]
Next, details of this conversion operation will be described with reference to FIG. In step S301, work variables u_no (slot number) and d_no (numeric part in the device name) are initialized.
In step S302, it is determined whether or not u_no is equal to or greater than the maximum number of units that can be mounted on the PC. If not, the process proceeds to step S303, and if not, the process ends.
In step S303, the card information of the unit installed in the u_no-th slot (the name of its own unit, for example, information including the unit name, slot number, unit type, number of occupied points, etc.) is stored in the fourth storage means of the unit. For example, the card information is read from the card information memory, and the card information is stored in a second table in the CPU unit 6, for example, the slot table 10.
In step S304, it is determined whether or not the unit is actually installed in the slot. If not, the process proceeds to step S308, and if it is installed, the process proceeds to step S305.
In step S305, the configuration is compared with the previous power-on configuration, and if different, the process proceeds to step S306, and if the same, the process proceeds to step S310.
In step S306, the interface sequence program is read from the I / O unit and loaded into the sequence program memory 701 of the CPU unit 6. Note that the sequence program memory 701 has an area of a fixed size for each slot, and is loaded into the area at the time of loading.
In the slot table 10, as shown in FIG. 5, in addition to the card information described above for each slot number, the capacity of the interface sequence program loaded at this time and the sequence in which this interface sequence program is stored in the CPU unit 6 A head address indicating from which address of the program memory 701 is stored is stored.
In step S307, in order to convert the interface device names scattered in the loaded interface sequence program into device numbers on the CPU unit 6, an offset of d_no is added to the device number. At this time, the device name (device name on the I / O unit) before adding the offset to the first table shown in FIG. 6, for example, the symbol table, and the device name after addition (device name on the CPU unit) ) And the slot number. If the I / O unit 8 is an input device, it becomes an output device in the CPU unit 6, and if it is an output device in the I / O unit 8, it becomes an input device in the CPU unit 6. Y is replaced by X with Y.
In step S308, the number of occupied points of the unit is added to d_no, and the process returns to step S302.
When the process proceeds from step S304 to step S309, the contents of the slot field in the slot table are cleared in step S309, and the process proceeds to step S310.
In step S310, 16 points (10 points in hexadecimal notation) are added to d_no as the number of occupied points for empty slots, and the process returns to step S302.
[0020]
When the interface sequence program is loaded from each I / O unit 8 to the CPU unit 6 by the operation shown in FIG. 4, the CPU unit 6 scans the sequence program of the CPU unit 6 itself, and then the respective interface sequence program. The storage address is obtained by referring to the slot table and scanned.
That is, a sequence program in which the sequence program of the CPU unit 6 itself and each interface sequence program are connected becomes a second sequence program, for example, a new sequence program, and is scanned by the CPU unit 6. If a unit name or the like is cleared in the slot number column of the slot table 10, no reading is performed assuming that no unit is installed in the slot.
[0021]
FIG. 7 is an explanatory diagram showing an example of the I / O unit 8 shown in FIG. 1 and a belt conveyor system controlled through the I / O unit 8. In the figure, 11 is a forward drive contact, and 13 is a reverse drive contact.
The device names of the forward operation contact 11 and the reverse operation contact 13 in the I / O unit 8 are Y10 and Y11, respectively. The device names of the forward end sensor 32 and the reverse end sensor 33 in the I / O unit 8 are X00 and X01, respectively. A motor 29 is attached to the belt conveyor 31, and the CPU unit 6 instructs the motor 29 to perform normal rotation / reverse rotation / stop via the I / O unit 8. A forward end sensor 32 is attached in the vicinity of one end (left end in FIG. 7) of the belt conveyor 31, and a reverse end sensor 33 is attached in the vicinity of the other end (right end in FIG. 7). The I / O unit 8 is notified by detecting that the workpiece has reached the forward end or the reverse end.
[0022]
FIG. 8 is a diagram illustrating a state in which the CPU unit 6, the I / O unit 8, and the like are mounted in the slots in the PC.
[0023]
FIG. 9 is a ladder diagram showing an example of an interface sequence program that is loaded from the I / O unit 8 to the CPU unit 6 and executed by the CPU unit 6 in the belt conveyor system shown in FIG. FIG. 9 shows a state after the device name is converted.
Next, the ladder diagram will be described. In FIG. 9, in step 801, if X0 is ON, a command to turn ON the emergency stop output Y7F on the I / O unit 8 is issued to stop the belt conveyor (the device name Y7F is the I / O unit 8). X1F).
In step 802, if X1 is ON, a command to turn ON Y74 (forward command) is issued (device name Y74 is X14 in the I / O unit 8).
In step 803, if X2 is ON, a command to turn ON Y75 (reverse drive command) is issued (device name Y75 is X15 in the I / O unit 8).
In step 804, if X7E is ON, the failure number is transferred from the I / O unit 8 to the CPU unit 6 by the FROM command (the device name X7E is Y1E in the I / O unit 8). This X7E is turned ON when an error occurs (when the cycle time is over).
When Y7F, Y74, and Y75 are turned ON, in the END processing of the sequence program, the slot numbers corresponding to these device names and the device names on the I / O unit 8 are obtained by referring to the symbol table described above, and the device A TO command to turn on the device with the name is executed, and the corresponding device (X1F, X14, X15) of the corresponding I / O unit 8 is turned on. Similarly, in the END processing of the sequence program, the slot number corresponding to X7E and the device number (Y1E) on the I / O unit 8 are obtained from the symbol table, and the I / O unit 8 installed in this slot is obtained. The FROM command for reading the contents of the device with this device name is executed to set the state of X7E. In this way, the interface devices X1F, X14, X15, and X7E are refreshed.
X0, X1, and X2 are on / off controlled in the sequence program of the CPU unit 6 (the portion not including the interface sequence program). These X0, X1, and X2 are set to device names that are not determined as interface devices in the interface sequence program stored in the I / O unit 8.
[0024]
FIG. 10 is a ladder diagram showing an example of a sequence program executed in the I / O unit 8 in the belt conveyor system shown in FIG. In the figure, in the notation of the interface device name, the notation in parentheses shows the notation after the interface sequence program is loaded into the CPU unit 6 and the device name is converted (notation in the CPU unit 8) for reference purposes. .
In the figure, in step S901, if T0 is not ON, the routine jumps to step S905 assuming that normal processing is performed. T0 is set when the cycle time is over.
In step S902, if Y1E is already ON in the previous scan, the process jumps to step S905 in order not to execute the CHK instruction again. When a failure is detected by failure diagnosis using the CHK instruction, Y1E is turned ON. Y1E is a device name in the I / O unit 8 and is X7E in the CPU unit 6.
In step S903, the CHK instruction is executed if the cycle time has exceeded during forward / reverse operation, and Y1E is set when a failure is detected as described above.
In step S904, the failure number is transferred to the CPU unit 8.
In step S905, when X14 is turned on while X15 (reverse command device), X00 (device indicating the state of the forward end sensor), and X1F (emergency stop command device) are turned off, Y10 (indicating forward operation) Device) is turned on, and Y00 used for failure detection is turned on. X14 is a device indicating a conveyor advance command, and the contact point of Y10 is connected in parallel with X14 on the ladder circuit.
In step S906, when X15 is turned on while X14 (forward command device), X01 (device indicating the state of the reverse end sensor), and X1F (emergency stop command device) are turned off, Y11 (reverse operation is being performed). Device) is turned on, and Y00 used for failure detection is turned off. On the ladder circuit, the contact point of Y11 is connected in parallel with X15.
In step S907, if X00 is ON, Y74 is reset. Since Y74 is a forward command, when Y74 is reset, the forward command is reset and the forward movement is stopped.
In step S908, if X01 is ON, Y75 is reset. Since Y75 is a reverse command, when Y75 is reset, the reverse command is reset and the reverse operation is stopped.
In step S909, the cycle time check timer is operated when X00 is OFF and X1F is OFF and Y10 is ON, or when X01 is OFF and X1F is OFF and Y11 is ON. When counting up, T0 is turned ON.
[0025]
Note that step S905 and step S906 in the ladder diagram of FIG. 10 are provided with an emergency stop contact X1F (Y7F) compared to steps S154 and S155 in the ladder diagram of FIG. This is one of the measures necessary for making the I / O unit 8 into one component.
Further, in the ladder diagram of FIG. 10, step S907 and step S908 are added compared to FIG. 16, but these steps are also added as measures necessary for making the I / O unit 8 as one component. Therefore, the output device that is turned on by the forward / reverse command sent from the CPU unit 6 into the I / O unit 8 is turned off.
The fact that the I / O unit 8 can be regarded as one component means that the operator simply inserts the I / O unit 8 into the slot of the PC and sets the slot number, and the CPU unit 6 and the I / O unit 8. This means that the I / O unit 8 can be used with almost no modification.
[0026]
As described above, in the system shown in FIG. 7, the CPU unit 6 issues three commands to the I / O unit 8, that is, conveyor operation permission, forward command, and reverse command. / O unit 8 is received. That is, the I / O unit 8 performs forward, reverse, and stop operations in accordance with instructions from the CPU unit 6. When the cycle time is over, the CPU unit 6 executes the FROM command in the loaded interface sequence program, and the failure number is the CPU unit 6. Configured to be sent to.
[0027]
Compared to the conventional system in which the CPU unit 22 executes the sequence program shown in FIG. 16, in the system shown in FIG. 7, the sequence program is processed by the I / O unit 8 shown in FIG. The sequence program in the CPU unit 6 is not required to perform the processing shown in FIG. 10 because it is divided into the interface portion, so that the scan time of the sequence program executed by the CPU unit 6 is shortened and high-speed processing is performed. It becomes possible.
In addition, compared with the conventional system in which the CPU unit 22 executes the sequence program shown in FIG. 16, in the embodiment of the present invention, it is divided into a part processed by the I / O unit 8 and an interface part as described above. Therefore, when the system is reconstructed, the part that needs to be changed can be easily identified and the program development efficiency can be improved.
That is, the sequence program shown in FIG. 10 is a sequence program specific to the I / O unit 8 and does not need to be changed when a normal system is changed. It is only necessary to change or create the sequence program shown in FIG.
[0028]
Next, a device access method of the I / O unit 8 will be described. FIG. 11 is an explanatory diagram showing signal paths in information exchange between the CPU unit 6 and the I / O unit 8. In the system shown in FIG. 11, each I / O unit 8 is assigned a symbol (unit name) consisting of a numerical value, a symbol, etc., and when accessing the device of the I / O unit 8 from the CPU unit 6, When accessing the device of the I / O unit 8 from this I / O unit, the I / O unit 8 is designated by this symbol. The CPU unit 6 converts this symbol into a slot number in the CPU unit 6 using the slot table 10.
For example, when the symbol of the I / O unit 8a is UNITA and the symbol of the I / O unit 8b is UNITB, when the I / O unit 8a accesses the device X0 of the I / O unit 8b, FIG. 12, the I / O unit 8a designates this device X0 with (UNITB.X0).
In FIG. 5, the mounting position of the I / O unit 8a is slot 5, the symbol of the I / O unit 8a is UNITA, the mounting position of the I / O unit 8b is 6, and the symbol of the I / O unit 8b is A part of the slot table 10 in the case of UNITB is illustrated.
The CPU unit 6 converts the symbol UNITB into a slot number by the slot table 10 and accesses the unit of the corresponding slot.
In this way, the device of the I / O unit 8 can be easily specified regardless of the slot in which the I / O unit 8 is inserted.
[0029]
Next, a supplementary explanation will be given for the conversion shown in FIG. When the I / O unit 8a accesses the device X0 of the I / O unit 8b, first, the I / O unit 8a transmits a message to the CPU unit 6 that the device X0 of the I / O unit 8b is to be turned on. This message has a structure of (symbol of I / O unit 8b + device number on I / O unit 8b + operation code). The operation code is a code indicating “ON”, “OFF” or the like. In this example, the message is, for example, “UNIT.B X0 ON”.
The CPU unit 6 obtains the slot number of the I / O unit 8b from the slot table 10 and sends this message to the unit of this slot. In this way, the message is transferred to the I / O unit 8b.
The I / O unit 8b performs the process indicated by the operation code in the message for the device in the unit specified by the device number in the message. In this example, processing for turning on the device X0 in the I / O unit 8b is performed.
[0030]
As described above, according to the present invention, the I / O unit 8 can be regarded as one component, and in the sequence program in the CPU unit 6, the interface sequence program for operating this component is added to its own sequence program. Just do it. Since the I / O unit 8 performs processing independently by its own sequence program, the CPU sequence program is prevented from being lengthened (the scan time is prevented from being lengthened) and the PC can be operated at high speed. . In addition, when changing or constructing a system, or when diverting a sequence program of another system, the interface sequence program may be modified / created, and the system change or construction or the sequence program of another system may be diverted. Can be easily done.
[0031]
【The invention's effect】
As described above, the first control unit repeatedly executes the first sequence program in which the storage address in the first storage unit of the device information indicating the state of the input / output device provided in the control target is described. An interface in which a storage address in the first storage means of interface device information that is exchanged between the PC main body units among the device information is described from the I / O unit that controls the controlled object via the first storage means to the PC main body unit. As the program is transferred, the second control means creates a first table showing the correspondence between the storage address in the first storage means of the I / O unit and the storage address in the third storage means of the PC main unit for the interface device information. In the interface program The storage address of the interface device information in the I / O unit is converted to the storage address in the PC main unit by the second control means, and the second sequence program having the converted interface program and its own sequence program is the second control means. The stored contents of the first and third storage means are refreshed so that the stored contents of the first and third storage means become the same for the interface device information based on the first table, and also according to its own sequence program Since the control of the I / O unit by the interface program is performed via the third storage means in addition to the predetermined control, if a sequence program executed by the I / O unit is created for each I / O unit The I / O unit It can be diverted to other programmable controllers as a single component, preventing the addition of additional programs to the sequence program of the PC main unit due to the addition of the I / O unit, preventing difficulty in creating the program, and PC An increase in the scan time of the main body unit is prevented, and a reduction in processing speed of the PC main body unit can be prevented. In addition, there is an effect that the change of the system and the diversion of the sequence program to the other system can be facilitated.
[0032]
Also, the name of the own unit is stored in the fourth storage means of the I / O unit, the stored contents of the fourth storage means in the I / O unit inserted in each slot are read, and the name and I / O are read out. The second table indicating the correspondence with the slot number in which the unit is inserted is created by the second control means, and the slot number corresponding to the name is recognized by the second control means based on the second table. This makes it possible to specify an I / O unit by name on the program, thereby preventing the difficulty of creating a program. In addition, there is an effect that the change of the system and the diversion of the sequence program to the other system can be facilitated.
[Brief description of the drawings]
FIG. 1 is a block configuration diagram of an I / O unit according to a first embodiment of the present invention.
FIG. 2 is a block configuration diagram of a CPU unit according to the first embodiment of the present invention.
FIG. 3 is a system configuration diagram according to Embodiment 1 of the present invention;
FIG. 4 is an operation flowchart of the CPU unit when power is turned on according to the first embodiment of the present invention.
FIG. 5 is an explanatory diagram showing an example of a slot table according to the first embodiment of the present invention.
FIG. 6 is an explanatory diagram showing an example of a symbol table according to Embodiment 1 of the present invention.
FIG. 7 is a block diagram showing a belt conveyor system according to Embodiment 1 of the present invention.
FIG. 8 is an explanatory diagram showing a state in which a CPU unit or the like is mounted in a slot of a PC according to Embodiment 1 of the present invention.
FIG. 9 is a ladder diagram showing an interface sequence program according to the first embodiment of the present invention.
FIG. 10 is a ladder diagram showing a sequence program executed in the I / O unit in the first embodiment of the present invention.
FIG. 11 is a diagram showing signal paths in the first embodiment of the present invention.
FIG. 12 is an explanatory diagram when accessing between I / O units in the first embodiment of the present invention;
FIG. 13 is a block diagram of a conventional I / O unit using a pattern table.
FIG. 14 is a block diagram showing a conventional belt conveyor system.
15 is an explanatory diagram showing a state in which a CPU unit or the like is installed in a slot of a PC in the belt conveyor system shown in FIG.
16 is a ladder diagram of a sequence program executed by a CPU unit in the belt conveyor system shown in FIG.
FIG. 17 is a block diagram of a conventional network in which a plurality of PCs are connected.
[Explanation of symbols]
1 I / O bus
3 Control device
4 Input circuit
5 Output circuit
6 CPU unit
7 Sequence program memory
8 I / O unit
9 Control device
10 Slot table
11 Forward operation contact
12 Motor
13 Reverse operation contact
14 Belt conveyor
15 Advance end sensor
16 Reverse end sensor
17 Input unit

Claims (4)

In a programmable controller having a PC main unit and a predetermined number of I / O units,
The I / O unit includes a first storage unit that stores device information indicating a state of an input / output device provided to a control target, and a first address in which a storage address of the device information in the first storage unit is described. First control means for controlling the control object via the first storage means by repeatedly executing one sequence program, and the PC among the device information whose storage address is described in the first sequence program Second storage means for storing an interface program in which a storage address of interface device information exchanged between the main unit is described;
The PC main unit creates a first table indicating the correspondence between the storage address in the first storage means and the storage address in the third storage means with respect to the storage address of the third storage means and the interface device information, A storage address of the interface device information in the interface program is converted into an address in the PC main unit, and a second sequence program having the converted interface program and its own sequence program is repeatedly executed, and the predetermined sequence by the own sequence program is determined. In addition to the control of the second control means for controlling the I / O unit by the interface program via the third storage means,
Based on the first table, the stored contents of the first and third storage means are refreshed so that the stored contents of the first and third storage means are the same for the interface device information, and the interface is displayed when the power is turned on. A programmable controller, wherein a program is transferred from the I / O unit to the PC main unit. The I / O unit has fourth storage means for storing the name of its own unit, and the stored contents of the fourth storage means in the I / O unit inserted in each slot are read when the power is turned on. The second table indicating the correspondence between the name and the slot number in which the I / O unit is inserted is created by the second control means, and the second control means corresponds to the name by the second table. The programmable controller according to claim 1, wherein the slot number is recognized. When the first control unit repeatedly executes the first sequence program in which the storage address in the first storage unit of the device information indicating the state of the input / output device provided for the control target is described, the first storage unit is executed. An interface program in which the storage address in the first storage means of the interface device information exchanged between the PC main body units among the device information is described from the I / O unit that controls the control object via the PC to the PC main body unit. Is transferred, and the first table indicating the correspondence between the storage address in the first storage means of the I / O unit and the storage address in the third storage means of the PC main unit is second for the interface device information. Created by the control means, The method is converted into a storage address in the PC main unit by the storage address is the second control means in the I / O unit of the interface device information in the scan program,
A second sequence program having the converted interface program and its own sequence program is executed by the second control means, and the contents stored in the first and third storage means for the interface device information based on the first table. The stored contents of the first and third storage means are refreshed so that they are the same, and the I / O unit is controlled by the interface program in addition to the predetermined control by the own sequence program. And a step of performing control via a storage means. Storing the name of the unit in the fourth storage means of the I / O unit;
The stored contents of the fourth storage means in the I / O unit inserted in each slot are read, and the second table showing the correspondence between the name and the slot number in which the I / O unit is inserted Is created by the second control means;
4. The method of controlling a programmable controller according to claim 3, further comprising the step of recognizing the slot number corresponding to the name based on the second table by the second control means.

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