JP3620080B2 - Motion vector detection circuit - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a motion vector detection circuit using a block matching method in, for example, high-efficiency encoding of moving images.
[0002]
[Prior art]
As one of motion vector detection methods, a block matching method is known. The block matching method is a method in which, for example, a macroblock obtains a motion vector using an evaluation function for each (16 × 16) pixel. In general, the sum of absolute differences is used as an evaluation function calculation method. For example, motion vectors are detected in a high-efficiency encoding method that reduces the redundancy of moving image data in the time direction and compresses the data amount.
[0003]
FIG. 11 shows a motion vector detection method using this block matching method. Reference numeral 145 denotes a frame to be processed. The frame 145 to be processed is divided into processing macroblocks 146 of (16 × 16) pixels, and a motion vector is detected for each macroblock. From the reference frame 141, pixel data in a range for searching for a motion vector called a search window 142 is extracted.
[0004]
As a method for calculating a motion vector evaluation function, a sum of absolute differences between a processing macroblock in a search window and a candidate macroblock at the same position as or a position shifted from the processing macroblock is generally used. That is, the difference between pixel values at corresponding positions between macroblocks is obtained, and the sum of absolute values of differences is obtained by accumulating the absolute value of this difference for one macroblock. Instead of absolute differences may be used after accumulating square value sum of the differences as an evaluation function.
[0005]
In FIG. 11, candidate macroblocks 143 indicated by dotted lines are those corresponding to processing macroblocks 146. The candidate macroblock 144 indicated by the solid line has the smallest evaluation function value. A motion vector corresponding to the position of the candidate macroblock 144 is obtained. The example of the motion vector shown in FIG. 11 is expressed as (−2, 4) in the coordinates where the right direction and the downward direction are positive.
[0006]
Next, there is a method of using a sub-sampling pattern in order to reduce the calculation amount of the block matching method. FIG. 12 shows an example of a 1/2 sub-sampling pattern when the macroblock has a size of (16 × 16) pixels. FIG. 13 shows an example of a 1/2 sub-sampling pattern when the macro block has a size of (4 × 4) pixels.
[0007]
White circles and black circles indicate pixels in the first field (# 1), and white squares and black squares indicate pixels in the second field (# 2). When calculating the sum of absolute differences, the sum of absolute differences is calculated only for white circles and white square pixels. If the evaluation function of these 1/2 sub-sampling patterns is used, the amount of calculation can be reduced to 1/2 corresponding to the fact that the number of pixels is halved.
[0008]
A conventional motion vector detection method when the macroblock has a size of (4 × 4) pixels will be described with reference to FIG. As described above, the frame to be processed is divided into processing macroblocks 152 of (4 × 4) pixels, and motion vectors are detected. A candidate macroblock 151 indicated by a dotted line in the frame to be referred to is a position corresponding to the processing macroblock 152.
[0009]
When the evaluation function related to the candidate macroblock 153 indicated by the thick line in the plurality of candidate macroblocks is minimum, a motion vector represented by (1,2) is obtained with the coordinates in the right direction and the downward direction being positive. . Here, a region divided into strips in units of a plurality of pixels (four pixels in FIG. 14) constituting one macroblock in the vertical direction is referred to as a stripe. The upper half stripe of the processed frame shown in FIG. 14 is referred to as a processed stripe MB . Further, the upper half stripe of the frame to be referred to is referred to as an upper stripe SW1, and the lower half stripe is referred to as a lower stripe SW2 .
[0010]
FIG. 15 shows an example of a conventional motion vector detection circuit that realizes the motion vector detection method shown in FIG. In FIG. 15, the data of the upper stripe SW 1 is supplied from the upper stripe input terminal 161 to the selection circuit 166 via the serial / parallel conversion circuit 164. Data of the lower stripe SW2 is supplied from the lower stripe input terminal 162 to the selection circuit 166 via the serial / parallel conversion circuit 165.
[0011]
The output of the selection circuit 166 is supplied to a PE (Processor Element, processing element) circuit 167. Data of the processing macro block MB is supplied from the processing stripe input terminal 163 to the PE circuit 167. The output of the PE circuit 167 is supplied to the output terminal 169 via the minimum value selection circuit 168.
[0012]
This motion vector detection circuit searches for motion vectors of a total of 16 points from 0 to 3 in the horizontal and vertical directions. The 16 selectors in the selection circuit 166 are selectors that select one of the two inputs. The PE circuit 167 calculates the sum of absolute differences for each PE. The minimum value selection circuit 168 selects a motion vector that minimizes the sum of absolute differences calculated by each PE.
[0013]
FIG. 16 shows a circuit configuration of each PE in the PE circuit 167. Reference numeral 171 denotes PE as a whole. Pixel data on the candidate macroblock side is supplied to the subtracter 174 from the input terminal 172. The subtracter 174 is supplied with pixel data on the processing macroblock side from the input terminal 173. The output of the subtracter 174 is supplied to the adder 178 via the absolute value circuit 175.
[0014]
The adder 178 is supplied with the output of the selector 177. The output of the adder 178 is supplied to the output terminal 180 and also supplied to the selector 177 via the delay circuit 179. From the terminal 176, a reset input (all “0” data) is supplied to the selector 177. The adder circuit 178, selector 177, and delay circuit 179 form a sum of absolute differences.
[0015]
FIG. 17 shows an input data sequence for PE0 to PE15 of the PE circuit 167 on the processing macroblock side. FIG. 18 shows an input data sequence for PE0 to PE15 of the PE circuit 167 on the search window side. Data of thick lines 192 and 202 and dotted lines 191 and 201 in FIGS. 17 and 18 correspond to the candidate macroblock 153 and the candidate macroblock 151 shown in FIG. 14, respectively.
[0016]
In the motion vector detection circuit shown in FIG. 15, one PE is responsible for the calculation of the evaluation function of one candidate macroblock. That is, it corresponds to one motion vector. Then, an evaluation function is obtained by performing the sum of absolute differences of each pixel by addition in the time direction.
[0017]
[Problems to be solved by the invention]
In the motion vector detection circuit described above, the absolute difference is applied to the pixels of the numbers of the processing macro blocks (0, 2, 5, 7, 8, 10, 13, 15) of the 1/2 sub-sampling pattern as shown in FIG. No processing for obtaining a value is required.
[0018]
However, since the absolute difference value of each pixel is added in the time direction in order to obtain the evaluation function by the conventional motion vector detection circuit, a selection circuit 166 including 16 selectors even if subsampling is used, There is a problem that a PE circuit 167 including one PE is required, and the circuit scale cannot be reduced. Furthermore, a sub-sampling pattern that can further reduce the amount of calculation and the circuit scale while maintaining the motion vector detection efficiency is desired as compared to the ½ sub-sampling pattern shown in FIGS.
[0019]
Accordingly, an object of the present invention is to provide a motion vector detection circuit capable of reducing the amount of calculation and the circuit scale while maintaining motion vector detection efficiency.
[0020]
[Means for Solving the Problems]
The present invention obtains a difference for each corresponding pixel between a processing block and each of a plurality of candidate blocks in a search window, calculates an absolute value sum or a square value sum of the differences , and calculates a minimum of the absolute value sum or the square value sum . In a motion vector detection circuit that detects a motion vector from a value,
Holding means for holding each pixel data in the processing block required in accordance with the sub-sampling pattern in parallel for one block period;
Parallelizing means for generating pixel data of different candidate blocks required in accordance with the sub-sampling pattern in parallel for each block period;
A plurality of subtracting means to which each pixel data from the holding means is commonly supplied as one input and each pixel data of the parallelized data of the candidate block from the parallelizing means is supplied as the other input;
A summing means for summing up the differences of the outputs of the plurality of subtracting means for each block period , and for obtaining the sum of absolute values or sum of squares of the differences ;
It is a motion vector detection circuit comprising detection means for detecting the minimum value of the sum of absolute values or the sum of square values of differences obtained by the integration means in each block period.
[0021]
[Action]
The motion vector detection circuit searches for motion vectors of a total of 16 points from 0 to 3 in the horizontal and vertical directions. The data of the processing macroblock MB is parallelized in the serial / parallel conversion circuit, and the data is held in the data holding circuit for one macroblock cycle.
[0022]
In the PE circuit, each PE calculates the absolute value of each sampling difference for each time slot (one block period), and the integrating circuit adds the absolute value of 16 samples generated between the processing macroblock and one candidate macroblock. Then, the sum of absolute differences is calculated. In the minimum value selection circuit, a motion vector that minimizes the calculated sum of absolute differences is selected.
[0023]
【Example】
First, an outline of an example of a high-efficiency encoding method using the motion vector detection circuit of the present invention will be described. As an encoding method, a widely known MC-DCT (motion compensation-discrete cosine transform) encoding method will be described as an example.
[0024]
FIG. 1 shows a circuit configuration of the MC-DCT encoding method. The digital image signal is supplied from the input terminal 1 to the motion vector detection circuit 5 and also supplied to the subtracter 2. The subtracter 2 is supplied with the output of the motion compensation circuit 4. The output of the subtracter 2 is supplied to the quantizer 6 via a DCT (discrete cosine transform) circuit 3. The output of the quantizer 6 is supplied to the variable length encoding circuit 11 and also supplied to the inverse quantizer 7. The output of the variable length coding circuit 11 is supplied to the output terminal 12.
[0025]
The output of the inverse quantizer 7 is supplied to the adder 9 via the inverse DCT circuit 8. The adder 9 is supplied with the output of the motion compensation circuit 4. The output of the adder 9 is supplied to the frame memory 10. The output of the frame memory 10 is supplied to the motion compensation circuit 4 and also to the motion vector detection circuit 5. The output (motion vector) of the motion vector detection circuit 5 is supplied to the motion compensation circuit 4 and also supplied to the output terminal 13.
[0026]
In FIG. 1, the subtracter 2 calculates an error between the input image signal and the prediction signal. The prediction signal is obtained by motion compensation from the signal of the previous frame in the frame memory 10 by the motion compensation circuit 4. A motion vector necessary for motion compensation is detected by the motion vector detection circuit 5. In the DCT circuit 3, two-dimensional DCT is performed on a block having a macroblock of about (8 × 8) pixels.
[0027]
The DCT coefficient is quantized by the quantizer 6 to obtain a quantization level. This quantization level is supplied to the variable length coding circuit 11, where the variable length coding circuit 11 performs coding by Huffman coding or the like, and transmits and records it through a buffer memory. A DCT coefficient is obtained by the inverse quantizer 7 and a decoded signal decoded by the inverse DCT circuit 8 is obtained. The locally decoded data is stored in the frame memory 10. The present invention relates to a motion vector detection circuit 5.
[0028]
Next, an embodiment of the present invention will be described. An example of the configuration of a motion vector detection circuit for easy understanding will be described with reference to FIG. As an example, the macro block is (4 × 4) pixels and pixel data is arranged as shown in FIG. In FIG. 2, data 0 to 31 of the upper stripe SW 1 are supplied from the upper stripe input terminal 21 to the selection circuit 27 via the serial / parallel conversion circuit 24. Data 0 to 31 of the lower stripe SW 2 is supplied from the lower stripe input terminal 22 to the selection circuit 27 via the serial / parallel conversion circuit 25.
[0029]
The output of the selection circuit 27 is supplied to the PE circuit 29. Data 0 to 15 of the processing macroblock MB are supplied from the processing stripe input terminal 23 to the PE circuit 29 via the serial / parallel conversion circuit 26 and the data holding circuit 28. The output of the PE circuit 29 is supplied to the output terminal 32 via the integration circuit 30 and the minimum value selection circuit 31.
[0030]
This motion vector detection circuit searches for motion vectors of a total of 16 points from 0 to 3 in the horizontal and vertical directions. The data of the processing macroblock MB is parallelized in the serial / parallel conversion circuit 26, and the data is held in the data holding circuit 28 for one macroblock period. The data holding circuit 28 has 16 holding circuits (SD).
[0031]
In the PE circuit 29, each PE calculates the difference absolute value of each sampling every time slot (one block period), and the integration circuit 30 calculates the difference absolute value of 16 samples generated between the processing macro block and one candidate macro block. And the sum of absolute differences is calculated. The minimum value selection circuit 31 selects a motion vector that minimizes the calculated sum of absolute differences.
[0032]
FIG. 3 shows the circuit configuration of each PE in the PE circuit 29. The circuit configuration of each PE is common to the motion vector detection circuit of one embodiment and other embodiments of the present invention described later. 41 shows PE as a whole. The output of the input terminal 42 is supplied to the subtracter 44. The subtracter 44 is supplied with the output of the input terminal 43. The output of the subtracter 44 is supplied to the output terminal 46 via the absolute value circuit 45.
[0033]
FIG. 4 shows a circuit configuration of each holding circuit in the data holding circuit 28. The circuit configuration of each holding circuit is common to the motion vector detection circuits of one embodiment of the present invention and other embodiments described later. Reference numeral 51 denotes a holding circuit as a whole. The output of the input terminal 52 is supplied to the selector 53. The selector 53 is supplied with the output of the D flip-flop 54. The output of the selector 53 is supplied to the D-flip flop 54 and also supplied to the output terminal 55.
[0034]
FIG. 5 shows an input data sequence for PE0 to PE15 of the PE circuit 29 on the processing macroblock side. FIG. 6 shows an input data sequence for PE0 to PE15 of the PE circuit 29 on the search window side.
[0035]
The data of the thick lines 62 and 72 and the dotted lines 61 and 71 in FIGS. 5 and 6 correspond to the candidate macroblock 153 and the candidate macroblock 151 shown in FIG. 14, respectively. In the motion vector detection circuit shown in FIG. 2, one time slot corresponds to the calculation of the evaluation function of one candidate macroblock, that is, one motion vector. Then, the sum of absolute differences of each pixel is performed by adding each PE.
[0036]
In the conventional motion vector detection circuit, the circuit scale cannot be reduced even if the sub-sampling evaluation function is used. On the other hand, if it is a motion vector detection circuit in which one clock cycle shown in FIG. 2 corresponds to the calculation processing of one motion vector evaluation function, the circuit scale can be reduced using subsampling.
[0037]
One embodiment of the present invention utilizing a 1/2 sub-sampling pattern is shown in FIG. In FIG. 7, the data of the upper stripe SW1 is supplied from the upper stripe input terminal 81 to the serial / parallel conversion circuit 84, and only the pixel data required according to the sub-sampling pattern among the parallelized data is supplied to the selection circuit 87. Is done. Data of the lower stripe SW 2 is supplied from the lower stripe input terminal 82 to the serial / parallel conversion circuit 85, and only necessary pixel data is supplied to the selection circuit 87.
[0038]
The output of the selection circuit 87 is supplied to the PE circuit 89. Data of the processing macroblock MB is supplied from the processing stripe input terminal 83 to the PE circuit 89 via the serial / parallel conversion circuit 86 and the data holding circuit 88. Also in this case, only necessary pixel data is supplied to the data holding circuit 88 and the PE circuit 89 according to the sub-sampling pattern. The output of the PE circuit 89 is supplied to the output terminal 92 via the integration circuit 90 and the minimum value selection circuit 91.
[0039]
Comparing the motion vector detection circuit of one embodiment of the present invention shown in FIG. 7 with the conventional motion vector detection circuit shown in FIG. 15, the selection circuit 87 and the PE circuit 89 have a calculation amount and circuit scale reduced by half. I understand.
[0040]
Next, the motion vector detection circuit so far has been performed on the premise of frame prediction, but a method called field prediction is also known. Frame prediction is a method of detecting a motion vector for each macroblock. On the other hand, in the field prediction, when the macroblock is (16 × 16) pixels in size, each is divided into an odd field macroblock and an even field macroblock each having (8 × 16) pixels, and a motion vector is detected separately. It is a method to do.
[0041]
Another embodiment of the present invention is shown in FIG. In another embodiment, the motion vector detection circuit shown in FIG. 2 is adapted for field / frame prediction. However, subsampling is not used. In FIG. 8, the data of the upper stripe SW 1 is supplied from the upper stripe input terminal 101 to the selection circuit 107 via the serial / parallel conversion circuit 104. The data of the lower stripe SW 2 is supplied from the lower stripe input terminal 102 to the selection circuit 107 via the serial / parallel conversion circuit 105.
[0042]
The output of the selection circuit 107 is supplied to the PE circuit 109. Data of the processing macroblock MB is supplied from the processing stripe input terminal 103 to the PE circuit 109 via the serial / parallel conversion circuit 106 and the data holding circuit 108. The output of the PE circuit 109 is supplied to the integrating circuit 110 and also supplied to the integrating circuit 111.
[0043]
The output of the integrating circuit 110 is supplied to the adder 112 and also supplied to the output terminal 116 via the minimum value selection circuit 113. The output of the integrating circuit 111 is supplied to the adder 112 and also supplied to the output terminal 118 via the minimum value selection circuit 115. The output of the adder 112 is supplied to the output terminal 117 via the minimum value selection circuit 114.
[0044]
Comparing the motion vector detection circuit of another embodiment of the present invention shown in FIG. 8 with the motion vector detection circuit shown in FIG. 2, the integration circuit 30 is integrated with the integration circuit 111 for the first field (# 1) and the second field. It is divided into the integration circuit 110 for (# 2), and the difference absolute value sum for each field is obtained but is different. Further, the sum of absolute differences of two fields can be added by the adder 112, thereby calculating the sum of absolute differences of frame prediction.
[0045]
The field (# 1) minimum value selection circuit 115, the field (# 2) minimum value selection circuit 113, and the frame minimum value selection circuit 114 select field prediction and frame prediction motion vectors, respectively. .
[0046]
The present invention is not limited to one embodiment and other embodiments, and an evaluation function of a 1/4 sub-sampling pattern may be used. In this case, in order to maintain motion vector detection efficiency, a sub-sampling pattern with spatial dispersion is desirable.
[0047]
FIG. 9 shows an example of a 1/4 sub-sampling pattern having scattering within a frame suitable for frame prediction. Although this sub-sampling pattern can reduce the calculation amount of the sum of absolute differences to ¼, the motion vector detection efficiency can be maintained.
[0048]
Further, FIG. 10 shows an example of a 1/4 sub-sampling pattern having scattering in the field suitable for the field prediction. Although this sub-sampling pattern can reduce the calculation amount of the sum of absolute differences to ¼, the motion vector detection efficiency can be maintained. Such various modifications are conceivable.
[0049]
【The invention's effect】
The present invention is applicable to various motion vector detection methods such as field prediction and frame prediction. Further, the present invention makes it possible to further reduce the calculation amount and the circuit scale while maintaining the motion vector detection efficiency from the 1/2 or 1/4 sub-sampling pattern as compared with the prior art.
[Brief description of the drawings]
FIG. 1 is a block diagram of a high-efficiency encoding method for explaining the present invention.
FIG. 2 is a block diagram of a motion vector detection circuit for explaining the present invention.
FIG. 3 is a block diagram of each PE common to one embodiment and another embodiment of the present invention.
FIG. 4 is a block diagram of each holding circuit common to one embodiment and another embodiment of the present invention.
FIG. 5 is a schematic diagram showing an input data sequence of a PE circuit on the processing macroblock side according to the present invention.
FIG. 6 is a schematic diagram showing an input data sequence of a PE circuit on the search window side according to the present invention.
FIG. 7 is a block diagram of a motion vector detection circuit according to an embodiment of the present invention.
FIG. 8 is a block diagram of a motion vector detection circuit corresponding to field / frame prediction according to another embodiment of the present invention.
FIG. 9 is a schematic diagram of a quarter subsampling pattern suitable for frame prediction that can be used in the present invention.
FIG. 10 is a schematic diagram of a quarter subsampling pattern suitable for field prediction that can be used in the present invention.
FIG. 11 is a schematic diagram for explaining a block matching method;
FIG. 12 is a schematic diagram of a ½ sub-sampling pattern when a macro block has a size of (16 × 16) pixels.
FIG. 13 is a schematic diagram of a ½ sub-sampling pattern when a macroblock has a size of (4 × 4) pixels.
FIG. 14 is a schematic diagram for explaining a motion vector detection method when a macroblock has a size of (4 × 4) pixels.
FIG. 15 is a block diagram of a conventional motion vector detection circuit.
FIG. 16 is a block diagram of each PE in a conventional motion vector detection circuit.
FIG. 17 is a schematic diagram showing an input data sequence for explaining a conventional motion vector detection circuit;
FIG. 18 is a schematic diagram showing an input data sequence for explaining a conventional motion vector detection circuit;
[Explanation of symbols]
28, 88, 108 Data holding circuit 30, 90, 110, 111 Integration circuit 31, 91, 113, 114, 115 Minimum value selection circuit 112 Adder

Claims (3)

Calculates the difference in the corresponding each pixel and each of the plurality of candidate blocks in the processing block and the search window, the absolute value sum or square value sum of the difference calculated from the minimum value of the absolute value sum or square value sum the In a motion vector detection circuit configured to detect a motion vector,
Holding means for holding each pixel data in the processing block required in accordance with the sub-sampling pattern in parallel for one block period;
Parallelizing means for generating pixel data of different candidate blocks required in accordance with the sub-sampling pattern in parallel for each block period;
A plurality of subtracting means to which each pixel data from the holding means is commonly supplied as one input and each pixel data of the parallelized data of the candidate block from the parallelizing means is supplied as the other input; ,
A summing means for summing up the differences of the outputs of the plurality of subtracting means for each block period , and for obtaining an absolute value sum or a square value sum of the differences ;
A motion vector detection circuit comprising: detection means for detecting a minimum value among the absolute value sum or the square value sum of the differences obtained by the integration means in each block period. The motion vector detection circuit according to claim 1,
When detecting motion vectors in the field, within the field , when detecting motion vectors within the frame, within the frame, adjacent pixel data used for motion vector detection are in the horizontal and vertical directions. as not continuous in the motion vector detection circuit, characterized by selecting the sub-sampling pattern. Calculates the difference in the corresponding each pixel and each of the plurality of candidate blocks in the processing block and the search window, the absolute value sum or square value sum of the difference calculated from the minimum value of the absolute value sum or square value sum the In a motion vector detection circuit configured to detect a motion vector,
Holding means for holding each pixel data in the processing block in parallel for one block period;
Parallelizing means for generating pixel data of different candidate blocks in parallel for each block period;
Each pixel data of the first field from the holding unit is commonly supplied as one input, and each pixel data of the parallelized data of the first field of the candidate block from the parallelizing unit is supplied to the other A plurality of first subtracting means supplied as input;
Each pixel data of the second field from the holding means is commonly supplied as one input, and each pixel data of the parallel data of the second field of the candidate block from the parallelizing means is supplied to the other A plurality of second subtracting means supplied as input;
A first summing means for summing up the outputs of the plurality of first subtracting means for each block period, and for obtaining an absolute value sum or a square value sum of the differences ;
A second summing means for summing up the outputs of the plurality of second subtracting means for each block period and obtaining the sum of absolute values or sum of squares of the differences ;
The first detecting means for detecting the minimum value of the sum of absolute values or the sum of square values of the differences obtained by the first integrating means in each block period and the second integrating means in each block period. is absolute value sum or square value second detection means and said first integrating means and said second absolute value of each of the difference calculated by the integrating means for detecting a minimum value among the sum of the difference Comprising a third detection means for synthesizing a sum of sums or square values and detecting a minimum value in the sum of absolute values or sum of squares ;
The motion vectors of the first field and the second field are obtained by the first detection means and the second detection means, and the motion vector of the frame is obtained by the third integration means. A motion vector detection circuit.

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