JP3616563B2 - Shared buffer packet switch - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a shared buffer type packet switch, and more particularly to queue management of buffer addresses of packet switch devices and router devices used in a LAN (local area network) or the like.
[0002]
[Prior art]
It is a CSMA / CD (Carrier Sense Multiple Access / Collision Detection) system represented by IEEE 802.3. In a LAN generally referred to as Ethernet, a switch element that constitutes a star connection form (topology), particularly a packet switch device or the like The router device uses a technique for queue management of buffer addresses when switching is performed by buffering packet data.
[0003]
As an example of a conventional technique, a shared buffer type ATM cell switch described in “Shared buffer type ATM switch” of Japanese Patent Laid-Open No. 11-163870 and “ATM cell switch” of Japanese Patent Laid-Open No. 10-32581 is used. There is a technique for managing queues of buffer addresses to achieve this.
[0004]
In the above publication, as a general technique for realizing a shared buffer system in an ATM cell switch, an empty address management queue for managing an empty address of a shared buffer, and a transmission address management for controlling a transmission order for a plurality of transmission channels The basic configuration and operation of the queue is disclosed.
[0005]
First, in order to facilitate understanding by the present invention, a conventional shared buffer type switch element will be briefly described with reference to FIGS.
[0006]
With reference to FIG. 12, the configuration and operation of the entire shared buffer type switch element will be described. The shared buffer packet switch includes transmission / reception control units 6011 to 6014 connected to ports 6051 to 6054, a packet switch element 6001 connected thereto via transmission / reception data buses 6021 to 6024, and buses 6031 and 6041, respectively. The shared buffer memory 6003 and the queue memory 6002 are connected to each other. Each port 6051-6054 accommodates a LAN line. Packet data received from each of the ports 6051 to 6054 is converted into a parallel signal by a transmission / reception control unit, for example, 6011, and passed to the packet switch element 6001 via the parallel signal transmission / reception data bus 6021. The packet switch element 6001 temporarily stores all packet data received from the line in the shared buffer memory 6003. In the case of transmission, the packet data stored in the shared buffer memory 6003 is read out using the memory address stored by the packet switch element 6001 itself, and transmitted / received via a parallel signal transmission / reception data bus, for example, 6022. The data is transmitted to the transmission / reception control unit 6012 and transmitted from the corresponding port 6052 to the LAN line.
[0007]
Next, the configuration and operation of the switch element will be described with reference to FIG. This switch element includes a switch element 7001 connected to reception ports 7011 to 7014 and transmission ports 7015 to 7018, a queue memory 7002, and a shared memory 7003. The queue memory 7002 includes an empty buffer address management circuit unit 7004 and a transmission buffer management circuit unit 7005. The parallel signal transmission / reception data buses 7020 and 7021 that are interfaces with the transmission / reception control units (6011 to 6014 in FIG. 12) described above are switched as one reception data bus 7020 in units of a plurality of reception ports 7011 to 7014. Input to element 7001. In addition, a plurality of transmission ports 7015 to 7018 are output from the switch element 7001 as one transmission data bus 7021.
[0008]
In FIG. 13, the reception data bus 7020 and the transmission data bus 7021 are each one, but there may be a plurality. Further, the reception data bus 7020 and the transmission data bus 7021 may be the same bus. Connection to the shared memory 7003 is made by an address bus 7030 and a data bus 7031 indicating memory addresses.
[0009]
The switch element 7001 stores the empty buffer address management circuit unit 7004 that manages the addresses of empty buffers on the shared memory 7003 and the order of packets to be transmitted in the shared memory 7003 for each transmission port. Each has a transmission buffer management circuit unit 7005 that manages the buffer address.
[0010]
When the switch element 7001 receives packet data from the reception data bus 7020, the switch element 7001 obtains an address of a buffer that can be stored from the empty buffer address management circuit unit 7004, and stores the packet data in the shared memory 7003. At the same time, the buffer address information is sent to the transmission buffer management circuit unit 7005 and registered in the transmission buffer queue of the port to be transmitted. On the transmission side, the packet is read from the shared memory 7003 according to this queue and output to the transmission data bus 7021. At this time, the buffer address of the packet used for reading is returned to the empty buffer address management circuit unit 7004 and used again when storing other received data.
[0011]
From the above, in the case of the shared memory system, the transmission buffer management circuit unit 7005 needs to be able to read packet data stored anywhere on the shared memory. This is because the memory areas that can be managed by the empty buffer address management circuit unit 7004 and the transmission buffer management circuit unit 7005 must be the same. It is also necessary to exchange address information with each other.
[0012]
Also, as an example of a conventional technique for buffer release processing in a multicast packet, there is a technique of multicast buffer address management for realizing a shared buffer type ATM cell switch described in Japanese Patent Laid-Open No. 10-294740.
[0013]
[Problems to be solved by the invention]
The above prior art discloses the basic configuration of the shared buffer empty address management queue and the output control address management queue. For the purpose of increasing the switch capacity of the switch element, when the packet switch element (6001 in FIG. 12) has a building block (building block) configuration in which a plurality of the same devices are stacked, a plurality of shared buffer address control circuit units also exist. As a result, the address management queues are distributed and implemented in parallel. Since these implementation means are not disclosed together, there is a problem that the switch capacity cannot be increased with the conventional technology.
[0014]
As another realization means, when the switching element unit is similarly configured as a building block in which a plurality of the same devices are stacked, and the address control circuit unit of the shared buffer is to be realized by a single device different from this, a switch There is a problem that the types of devices that implement elements increase.
[0015]
In addition to these, the conventional ATM switch is a technology for switching fixed byte length data called a cell, and there is no particular disclosure regarding the technology for switching an Ethernet variable length packet, just like a cell handled by an ATM switch. If it is treated as fixed byte length data, it is necessary to always prepare a buffer that assumes the packet data of the longest byte length of Ethernet, and when switching operation of packet data of short byte length or minimum byte length occurs frequently, There is a problem that the buffer cannot be used efficiently.
[0016]
In addition, in the buffer release processing in the multicast packet shown as a publicly known example, since there is no description about the realization means when the address management queue is distributed and implemented by the building block (building block) configuration, As it is, there is a problem that switching of multicast packets cannot be performed.
[0017]
OBJECT OF THE INVENTION
SUMMARY OF THE INVENTION An object of the present invention is to provide a shared buffer type packet switch in which a shared buffer address control circuit unit can be implemented by a building block (block) configuration in which a plurality of identical devices are stacked.
[0018]
[Means for Solving the Problems]
In order to solve the above-described problem, the shared buffer packet switch according to the present invention employs the following characteristic configuration.
[0019]
(1) In a shared buffer type packet switch in which a control circuit for queue management of buffer addresses is distributed to a plurality of devices.
The free address management queue that manages the free buffer addresses of shared buffers is used by multiple devices. Each one exists, only one of them is operated, and the address information of the free buffer is obtained. A packet switch with a shared buffer system that centrally manages.
[0020]
(2) A used address management queue for managing a chain of unit buffers constituting a packet is present in each distributed device unit, The unit buffer sequence information used by each device in one packet is the same information at the same time. The packet switch of the shared buffer system of (1) managed redundantly.
[0021]
(3) A transmission address management queue for managing the packet transmission order for each transmission channel is provided for each distributed device, Send packet order information independently (1) or (2) shared buffer type packet switch to be managed.
[0022]
(4) When moving transmission packets between arbitrary transmission address management queues, Even when the packet capacity is larger than the unit buffer and stored in a plurality of unit buffers by the transmission address management queue, connection information of unit buffers constituting one packet is managed. Management information can be moved because the device has the same information at the same time. The packet switch of the shared buffer method of (2) which is not performed.
[0023]
(5) Address handshake between free address management queue and transmission address management queue or used address management queue Use the memory address bus when the shared memory data bus is used for time-sharing the enqueue and dequeue address information path. (2) or (3) shared buffer type packet switch to be performed.
[0024]
(6) A multicast management queue that temporarily holds multicast packets is The order of broadcast packets sent by each device (2) or (3) shared buffer type packet switch managed individually.
[0025]
(7) In the multicast packet buffer release process, means for recognizing that all transmissions to the destination managed by the own device have been completed for each distributed device are provided for each device. Receiving the notification of transmission completion of Exist on each device, Free address management queue works Simultaneously running on the same device as (6) The shared buffer type packet switch for performing the buffer release processing.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of a shared buffer packet switch according to the present invention will be described in detail with reference to the drawings.
[0027]
FIG. 2 is a system configuration diagram including a packet switch device 2000 using a shared buffer packet switch according to the present invention and a plurality of LAN segments 2011 to 2014 connected thereto. This network will be briefly described.
[0028]
The packet switch device 2000 configures a star-type LAN topology by concentrating and connecting a plurality of LAN segments 2011 to 2014. The LAN assumed here is a LAN generally referred to as Ethernet of CSMA / CD (Carrier Sense Multiple Access / Collision Detection) typified by IEEE 802.3, or full duplex of 10 Mbps, 100 Mbps or 1 Gbps, or Has half-duplex communication speed.
[0029]
Next, these LAN segments 2011 to 2014 will be described.
[0030]
These LAN segments 2011 to 2014 are units that share a transmission path and a communication band of 10 Mbps, 100 Mbps, or 1 Gbps. The LAN segments 2011, 2013, and 2014 are concentrators (simply called repeater hubs) 2021, 2023, and 2024 that do not have a switching function and have a simple repeater function, and each terminal is also connected in a star shape. . Further, as indicated by the LAN segment 2014, depending on the functions of the repeater hubs 2021, 2023, and 2024, it may be possible to connect a terminal in a partial branch type. In any case, in one segment constituted by these repeater hubs 2021, 2023, and 2024, transmission is performed at all terminals in each segment 2011-2014 and the port of the packet switch device 2000 according to the CSMA / CD system. This is half-duplex communication that shares a path and a communication band.
[0031]
On the other hand, the LAN segment 2012 is often seen in connection to the server device 2022, and can perform full-duplex communication with a one-to-one connection to the port of the packet switch device 2000 without using a repeater hub. It is said that.
[0032]
The frame format of a packet communicated on the LAN has a conventional configuration, and includes DA (Destination-Address), that is, destination address information and SA (Source Address), that is, source address information, as shown in FIG. DATA is a variable length in the information data part. In ordinary Ethernet, the entire packet has a frame length of 64 bytes to 1518 bytes.
[0033]
The packet switch apparatus 2000 receives packet data having this frame format from one LAN segment, for example, 2011, and transfers the packet data to another LAN segment, for example, 2012 based on DA information. It is a device that realizes the operation.
[0034]
Next, the configuration of the packet switch device 2000 of FIG. 2 will be described in detail with reference to FIG.
[0035]
A portion connected to the LAN segments 2011 to 2014 is called a port, and usually has about 8 to 32 ports or more than that in some cases. In the case of the packet switch device 2000 of FIG. 3, there are a total of 16 ports of port # 0 to port #f.
[0036]
The four-port transmission / reception control units 3011 to 3014 exist in units of one or a plurality of ports, and are usually configured with a single device and a control memory that stores network address information. In the example of FIG. 3, the transmission / reception control circuit exists in units of four ports. A packet data transmission / reception operation is realized for the connected LAN line. The main processing is data serial / parallel conversion processing between the LAN line communicated with serial data and the data bus inside the device that performs parallel processing, and the destination information included in the received packet is analyzed and transmitted. This is a process for determining the destination port.
[0037]
The shared memory 3020 is configured by an SRAM (static RAM) or DRAM (dynamic RAM) memory device, and temporarily holds packet data. Packet data is stored in a space called a packet buffer partitioned in advance. The address (address) of the packet buffer is managed by a queue type buffer management circuit of the switch element.
[0038]
The four switching elements 3001 to 3004 are composed of one device and a control memory (queue memory) that performs buffer management. The transmission / reception control units 3011 to 3014 are connected by transmission / reception data buses 3051 to 3054 expanded in parallel. The connection form is that when the bit width of the transmission / reception data bus is txk bits and the number of devices of the switching elements 3001 to 3004 is 4, the transmission / reception data bus 3041 having a t-bit width that is bit-sliced in units of t bits. ˜3044 are connected to four switching elements 3001 to 3004.
[0039]
Connection to the shared memory 3020 is performed by the switching elements 3001 to 3004 via the shared memory data buses 3031 to 3034 to the shared memories 3061 to 3064, respectively. That is, the shared memory data buses 3031 to 3034 are also bit-sliced into four equal parts.
[0040]
With reference to FIG. 4, an embodiment of queue management in a shared buffer packet switch according to the present invention will be described in detail.
[0041]
The packet switch of the shared buffer system according to the present invention has n reception data buses (four in the example of FIG. 3) and n transmission data buses (four in the example of FIG. 3). A bus or a transmission data bus accommodates ports connected to m LAN lines, and the entire switching element accommodates mxn ports.
[0042]
The connection between the reception data bus and the transmission data bus is performed by bit-slicing one data bus width to 1 / the number of switch elements (example in FIG. 3). In other words, the packet switch device is configured to increase the amount of data to be processed by a multiple of the number of switch elements by adopting a building block (building block) type configuration with a plurality of the same switch elements.
[0043]
The first switch element 4051 includes a data transmission / reception unit 4002 and a queue management control unit 4001. Connections on the LAN port side are connected by n reception data buses 4011 and n transmission data buses 4012. The shared memory 4300 has a configuration in which a memory address bus 4330 and a data bus 4310 are connected.
[0044]
The second switch element 4151 to the nth switch element 4251 have the same configuration.
[0045]
When the reception unit 4003 (and 4103, 4203) of each switch element 4051 (and 4151, 4251) recognizes the received packet from each reception data bus 4011 (and 4111, 4211), the queue management control unit 4001 in the same device. Received packet notification 4021 (and 4121, 4221) is performed on (and 4101, 4201). Each receiving unit 4003 (and 4103, 4203) notifies all received packets for mxn ports.
[0046]
The received packet is transferred to the shared memory 4300 via the data bus 4013 (and 4113, 4213).
[0047]
The queue management control unit 4001 recognizes that the queue management control unit exists in the first switch element 4051 based on the device position information and the like, and outputs a free address 4032 of the buffer for storing the received packet. The queue management control units 4101 and 4201 existing in other switch elements do not output.
[0048]
The transmission unit 4004 (and 4104, 4204) receives the notification of the transmission queue information 4022 (and 4122, 4222) for the m ports from the queue management control unit 4001 (and 4101, 4201), and determines the transmission port.
[0049]
Upon receiving the notification of the port number 4023 (and 4123, 4223) determined by the transmission unit 4004 (and 4104, 4204), the queue management control unit 4001 (and 4101, 4201) receives the transmission packet read address 4032 (and 4132, 4232). ) Is output. The transmission packet data 4014 (and 4114, 4214) is transferred to the transmission unit 4004 (and 4104, 4204), and transferred from the transmission data bus 4012 (and 4112, 4212).
[0050]
Next, specific examples of the queue management control units 4001 to 4201 will be described in detail with reference to FIG.
[0051]
The free address management queue 1010 operates only on the device 0 which is the first switch element. As long as they are the same device in other switch elements, the circuits of the empty address management queues 1110 and 1210 exist but do not operate.
[0052]
The used address management queue unit 1020 (and 1120, 1220) includes a used address management queue 0 (1021), a used address management queue 1, and a used address management queue k (1022). There are as many queues as there are queues for managing the chain of unit buffers constituting one packet. In each switch element, the contents of the used address management queue unit are the same.
[0053]
The transmission address management queue unit 1030 of the switch element of the device 0 includes a transmission address management queue 00 (1031), a transmission address management queue 01, and a transmission address management queue 0m (1032). In other words, only the head address of the buffer storing the packet exists in the transmission port unit existing under the transmission data bus 0, and the transmission order is managed. Similarly, transmission address management queue units 1130 and 1230 after device 1 also perform transmission address management queues corresponding to transmission ports under transmission data bus 1 and transmission data bus n, respectively.
[0054]
Next, the operation of the embodiment of the shared buffer packet switch according to the present invention will be described in detail with reference to the drawings.
[0055]
First, with reference to FIG. 3, the operation of the packet switch apparatus 2000 using the shared buffer packet switch according to the present invention will be described in detail.
[0056]
The packet data received as serial data at the port is subjected to serial / parallel conversion processing by a transmission / reception control unit, for example, 3011, and is output to the reception data bus. At that time, the transmission / reception control unit 3011 analyzes the destination information included in the received packet, performs a process of determining the destination port, and adds the destination port information to the packet data output to the reception data bus.
[0057]
The destination port information is bit-sliced and the same content is added to each divided bus unit. Each of the plurality of switching elements 3001 to 3004 looks at the transmission destination port information and determines whether or not it is a transmission packet to be managed by its own device. For packet data, in the case of reception, the data sent via the reception data bus at the bit slice position to which the device is connected is stored in the shared memory 3020 to which the device is connected.
[0058]
The same applies to transmission, and the data read from the shared memory 3020 to which the own device is connected is output to the transmission data bus at the bit slice position to which the own device of the transmission data bus is connected.
[0059]
Next, the operation of the queue management of the switch element according to the present invention will be described in detail with reference to FIG. First, the reception side operation will be described.
[0060]
When the switch element (4051 to 4251 in FIG. 4) receives one or a plurality of packets from the n reception data buses 4011 to 4211, it notifies the queue management control units 4001 to 4201 of packet reception 4021 to 4221. As described above, the reception port information and the destination information of the packet are notified.
[0061]
First, the vacant address management queue 1010 obtains the address of the vacant buffer for storing the packet from the packet reception information, and the received data transferred by the receiving unit (4003, 4103 and 4203 in FIG. 4) after being bit-sliced. In synchronization with the transfer timing to the shared memory, it is output as a write address to the shared memory. The timing to synchronize is known to both by a predetermined time slot. This empty address output is performed only for the empty address management queue 1010 of the device 0.
[0062]
At the same time, the used address management queue of each device, for example, 1120 receives the address output from the free address management queue 1010 from the enqueue path, for example, 1140, and manages the chain of unit buffers constituting the packet.
[0063]
The operation of storing variable-length packet data in the packet memory will be described with reference to FIG. The packet memory is used in units of a unit buffer having a capacity of b bytes. The packet is stored in the buffer using p unit buffers expressed by the following equation, where the data length is P bytes.
((P−1) * b) <P ≦ (p * b), (p = 1, 2, 3,...)
[0064]
The used address management queue 5201 manages this unit buffer chain. Assuming that the address of the unit buffer 5101 for storing the first b byte 5001 of the packet is ba01, the address of the unit buffer 5102 for storing the subsequent b bytes is ba02, and the address of the unit buffer 5103 to be similarly chained is ba03, the used address management The head buffer address indicated by the queue 5201 is ba01, and the address indicating the tail is ba0p.
[0065]
As a form in which the received packet is transferred, each packet received from a plurality of ports is multiplexed on the unit buffer and transferred on the received data. On the other hand, the used address management queue, for example, 1020 can be reassembled as one packet for each receiving port from the information of the receiving port transferred at the same time.
[0066]
At the same time, the transmission address management queue, for example 1130, determines whether it is addressed to the transmission port to be managed by the device from the notification of the destination information of the packet issued by the reception unit and the position information of the device.
[0067]
If it is packet data addressed to the transmission port to be managed, only the head storage address of the received packet is received from an enqueue path, for example, 1140, and enqueued at the end of the corresponding transmission buffer queue. If there is no packet data addressed to the transmission port to be managed, it is ignored and the enqueue operation is not performed.
[0068]
Next, the operation on the transmission side will be described. The transmission address management queue unit, for example, 1130 receives information (4122 in FIG. 4) as to whether or not the address of the packet to be transmitted is queued in each transmission address management queue, and sends it to the transmission unit (4104 in FIG. 4). Always forward to). Based on this information, the transmission unit determines the port number to be transmitted, and notifies the transmission address management queue unit 1130 of the result as a transmission request according to a predetermined time slot (4123 in FIG. 4).
[0069]
In the case of transmission from the head of the packet, the transmission address management queue unit 1130 extracts one head address of the packet from the corresponding transmission address management queue, for example, 1131 according to this notification, and the address of the shared memory via the dequeue path 1141 The data is output to the bus 1330 as a packet read address.
[0070]
Simultaneously with the reading of the packet data, the buffer address output to the shared memory address bus 1330 is enqueued to the empty address management queue 1010 via the enqueue path 1050 of the empty address management queue 1010, and the unit buffer is released. .
[0071]
In the case of transmission of p = 2 or more packets other than the first unit buffer, the used address management queue unit 1120 extracts one buffer address according to the notification from the transmission unit (4123 in FIG. 4), and the dequeue path 1141 To the shared memory address bus 1330 as a packet read address. Simultaneously with the reading of the packet data, the buffer address output to the shared memory address bus 1330 is enqueued to the empty address management queue 1010 via the enqueue path 1050 of the empty address management queue 1010, and the unit buffer is released. .
[0072]
Next, the operation of the shared buffer packet switch according to the present invention will be described in detail with reference to FIGS. First, the format of packet data transferred on the reception data bus will be described with reference to FIG. The four horizontal columns 8000 to 8003 are reception data buses that are bit-sliced in units of 8 bits, each having an 8-bit width. Vertical rows 8010, 8011, 8012, 8013... Represent one word of the received data bus, and are transferred in order from the word in the upper row 8010.
[0073]
The word of line number 8010 is transmission destination port information (RH) indicating the transmission destination port added by the transmission / reception control circuit unit. The destination port information (RH) can be received by all the switching elements by being added to all the bit-sliced reception data buses. The destination port information (RH) includes information on the reception port, information on the destination port, information on whether the data is from the beginning of the packet, information on whether the data includes the end of the packet, and the like. included. After the line number 8011, packet data having a byte order of D00, D01, D02, D03, D04... Received from the port is bit-sliced in units of bytes and transferred to each switching element.
[0074]
Next, the queue type buffer management operation will be described in detail with reference to FIGS. FIG. 8 shows an image in which packet data is stored on the shared memory. In this example, four shared memories bit-sliced in units of 8 bytes constitute one word, and 64 bytes are used as one buffer unit. The addresses of the buffers are address a, address b, and address c, respectively. It is an example which is the structure of a word address.
[0075]
The example of FIG. 7 shows a state in which these buffers are stored in the queue in the order of address a, address b, address c,... Address e (9003). In the empty address management queue in the device of the switch element or the transmission address management queue 9001 existing in units of ports, only the first pointer 9011 and the last pointer 9012 of the buffer queue existing in the queue memory 9002 are held.
[0076]
In the switch element according to the present invention, the pointer of this queue directly corresponds to the buffer address. Thus, the pointer (queue memory address) for accessing the queue memory 9002 also corresponds to the buffer address. That is, the first pointer 9011 is the first buffer address (address a) registered in the queue, and the second buffer address (address b) is stored at the queue memory address indicated by the first pointer (address a). ing.
[0077]
A dequeue operation for extracting the first buffer address (address a) registered in the queue will be described. First, the content of the head pointer 9011 is directly used as an empty buffer address or a transmission buffer address. Therefore, the buffer address can be generated at high speed. Subsequently, while the shared memory is being accessed, the head pointer 9011 used now is used as the queue memory address, the next buffer address is read, and the head pointer 9011 is updated with this value.
[0078]
An enqueue operation for registering a new buffer address at the end of the queue will be described. First, the last pointer 9012 is used as the queue memory address, and the buffer address to be registered is written therein. Also, the last pointer 9012 is updated with this value.
[0079]
Next, a time slot for accessing the shared memory will be described in detail with reference to FIG. In this example, there are a total of eight switch element master operations for the shared memory, that is, received packet data storage operation corresponding to four reception data buses and transmission packet data read operation corresponding to four transmission data buses. . Therefore, eight values are generated by a 3-bit always-on (free-run) counter and assigned to eight master operation time slots. In the example of FIG. 9, when the counter value = 000b, the write data transfer operation to the shared memory corresponding to the reception data bus # 0. When the counter value = 100b, the sharing corresponding to the transmission data bus # 0. This is a read data transfer operation from the memory.
[0080]
Next, another embodiment of a packet switch device using a shared buffer packet switch according to the present invention will be described with reference to FIG.
[0081]
A description will be given of the queue switching operation in the transmission address management queue between different devices. The transmission address management queue 00 (1031) is not a queue addressed to a LAN line port, but a transmission queue addressed to a CPU in the apparatus. In other words, the processing port of the CPU is located where the normal LAN line port exists. In the packet switch apparatus (2000 in FIG. 2), when the destination of the received packet cannot be resolved, the packet is temporarily queued in the transmission address management queue 00 (1031) addressed to the CPU, and the packet is processed by software processing. The operation of determining the transfer destination of the file occurs.
[0082]
In this case, the CPU directly reads the transmission address management queue 00 (1031), knows the address of the buffer in which the packet with unknown destination is stored, and takes out only the information necessary for destination resolution from the packet on the shared buffer. When the CPU resolves the destination, it notifies the queue change request via the reception unit (4003 in FIG. 4) using the path of the packet reception notification (4021 in FIG. 4).
[0083]
If the packet reception notification (4021 in FIG. 4) is a queue reconnection request, the free address management queue 1010 does not perform a normal free address dequeue operation and does not perform a write operation to the memory. Instead, the transmission address management queue 00 (1031) dequeues the head address and outputs it to the address bus via the dequeue path 1041.
[0084]
The used address management queue unit, for example, 1120 determines that the packet reception is not normal, and ignores this packet reception notification (4021 in FIG. 4). The other transmission address management queue, for example, 1130 determines that this packet reception notification (4021 in FIG. 4) is similar to the normal packet reception, and enqueues it in the transmission address management queue corresponding to the transmission port. At this time, even if the packet length is longer than p = 2 and the unit buffer chain information is required and the packet is moved to the transmission address management queue between different devices, the used address management queue has the same contents in all devices. Therefore, there is no problem, and it is possible to easily change queues.
[0085]
Next, a third embodiment of the packet switch device using the switch element of the present invention will be described with reference to FIG. FIG. 11 is a configuration diagram of a queue management control unit in multicast packet switching processing.
[0086]
Multicast address management queues 13020 to 13220 exist for each device, and perform temporary queue management of multicast packets. The enqueue path selectors 13040 to 13240 select enqueue paths 13072 to 13272 to the transmission address management queues 13030 to 13230. When a unicast packet is received, the enqueue path 13070 to 13270 is selected, and the empty time when there is no reception is selected to the enqueue path 13071 to 13271. Transmission port counters 13050 to 13250 exist for each device, and store the number of destination ports for each packet, store the number of transmitted ports for each unit buffer, and compare the number of destination ports with the number of transmitted ports.
[0087]
The device counter 13060 exists only in the device in which the free address management queue 13010 operates, stores the number of transmitted devices for each unit buffer, and compares the number of devices obtained from the device configuration information with the number of transmitted devices.
[0088]
First, a multicast packet switching operation will be described.
When the packet reception notification (4021 in FIG. 4) received from the receiving unit (4003 in FIG. 4) is a unicast packet, as described in the first embodiment, the packet destination information and device position information Therefore, only the devices to be managed are enqueued in the transmission address management queues 13030 to 13230. This is a case where the enqueue path selectors 13040 to 13240 are selected as the enqueue paths 13070 to 13270.
[0089]
On the other hand, when the packet reception notification (4021 in FIG. 4) is a multicast packet, it is temporarily enqueued in the multicast address management queues 13020 to 13220 of all devices. Thereafter, each device independently monitors whether or not a unicast packet has been received, switches the enqueue path selectors 13040 to 13240 to the dequeue path 13071 to 13271 in the idle time, and dequeues from the multicast address management queues 13020 to 13220. Then, the queues that are enqueued to the plurality of transmission address management queues 13030 to 13230 that are destinations are transshipped.
[0090]
At this time, even if the packet length is a packet of p = 2 or more and the unit buffer chain information is necessary, the used address management queues 13090 to 13290 hold the same contents in all devices. It doesn't matter. Further, since only one packet entity exists in the shared memory and only a copy of the queue entry is distributed in each device, high-speed switching operation is possible.
Next, the shared buffer release operation will be described.
[0091]
Since there is only one multicast packet on the shared memory, the buffer cannot be released until transmission to all destinations is completed.
[0092]
First, when dequeuing from the multicast address management queues 13020 to 13220 and enqueuing to the transmission address management queues 13030 to 13230, the number of destination ports enqueued for each device is stored in the transmission port counters 13050 to 13250. At the same time, the initial value “0” is written as the number of transmitted ports.
[0093]
Next, when the packet dequeued from the transmission address management queues 13030 to 13230 at the time of transmission is a multicast packet, the number of destination ports corresponding to the packet and the buffer corresponding to the packet are transmitted from the transmission port counters 13050 to 13250. The number of transmitted ports is extracted, the number of transmitted ports is incremented by +1, and if the number does not coincide with the number of destination ports, the number of transmitted ports incremented by +1 is written back to the transmission port counters 13050 to 13250. to start. Upon receiving a transmission completion notification 13500 from each device, the device counter 13060 takes out the number of transmitted devices corresponding to the buffer, adds +1 to this, and if it does not match the number of devices obtained from the device configuration information, adds +1. When the number of transmitted devices is written back to the device counter 13060 and they match, it is determined that transmission to all destinations is completed, and the address of the buffer is enqueued to the free address management queue 13010 by the enqueue path 13080, and the buffer is released. To do.
[0094]
If the packet length is p = 2 or more and the unit buffer chain information is necessary, the second buffer and subsequent buffers are taken out of the used address management queues 13090 to 13290 and similarly buffered. To release.
[0095]
Further, even in the release operation, the used address management queues 13090 to 13290 hold the same contents in all the devices, so there is no problem.
[0096]
The configuration and operation of the preferred embodiment of the shared buffer packet switch according to the present invention have been described above in detail. However, it should be readily understood by those skilled in the art that the present invention should not be limited to only such specific embodiments, and various modifications can be made without departing from the spirit of the present invention.
[0097]
【The invention's effect】
As is apparent from the above description, according to the shared buffer type packet switch according to the present invention, a large-scale (large capacity) packet switch device can be easily realized by using a plurality of the same shared buffer type switch elements. It has a remarkable effect in practical use. The reason is that the buffer management unit that realizes the shared buffer method should exist at one central location in the past, but the queue corresponding to the case where the data processing part of the switch element is made into a building configuration by a technique such as bit slice. This is because the structure of is realized.
[Brief description of the drawings]
FIG. 1 is a functional configuration diagram illustrating an embodiment of a shared buffer packet switch according to the present invention.
FIG. 2 is a configuration diagram of a network using a shared buffer packet switch according to the present invention;
FIG. 3 is a block diagram of a packet switch device in a shared buffer packet switch according to the present invention;
FIG. 4 is a configuration diagram illustrating connection of a plurality of switching elements in a shared buffer packet switch according to the present invention;
FIG. 5 is a block diagram showing a form of a buffer constituting a packet in a shared buffer type packet switch according to the present invention;
FIG. 6 is a configuration diagram of input / output data to a switching element in a shared buffer packet switch according to the present invention.
FIG. 7 is a functional configuration diagram showing queue management of a buffer pointer in the present invention.
FIG. 8 is a timing chart showing an example of a time slot in the present invention.
FIG. 9 is a configuration diagram of data stored on a buffer memory according to the present invention.
FIG. 10 is a format of packet data communicated in the present invention.
FIG. 11 is a functional configuration diagram showing another embodiment of the present invention.
FIG. 12 is a functional configuration diagram of a conventional shared buffer packet switching apparatus.
FIG. 13 is a functional configuration diagram of a switching element constituting a conventional shared buffer type packet switch device;
[Explanation of symbols]
2000 Packet switch device
1010, 1110, 1210, 13010 Free address management queue
1020 to 1022, 1120 to 1122, 1220 to 1222, 13090, 13190, 13290 Used address management queue
1030 to 1032, 1130 to 1132, 1230 to 1232, 13030, 13130, 13230 Transmission address management queue
1040, 1050, 13070, 13072, 13080, 13170, 13172, 13270, 13272 Enqueue path
1041, 1051, 13071, 13073, 13171, 13173, 13271, 13273, 13300, 13400 Dequeue path
3020, 3061-3064, 4300 Shared memory
13020, 13120, 13220 Multicast address management queue
13040, 13140, 13240 Enqueue path selector
13050, 13150, 13250 Transmission port counter
13060 device counter
13074, 13174, 13274, 13500 Transmission completion notification

Claims (7)

In the packet switch of the shared buffer system, in which the control circuit for queue management of the buffer address is distributed to a plurality of devices,
A free address management queue for managing a free buffer address of a shared buffer exists in each of a plurality of devices, and only a specific one of them is operated to centrally manage address information of a free buffer. Shared buffer packet switch. A used address management queue that manages the chain of unit buffers that make up a packet exists in each distributed device , and the unit buffer sequence information used by each device in one packet is managed redundantly as the same information at the same time. The shared buffer type packet switch according to claim 1. The transmission address management queue for managing the packet transmission order for each transmission channel is present in each distributed device unit, and manages the order information of the packets transmitted by each device independently. 3. The shared buffer packet switch according to 2. When moving a transmission packet between arbitrary transmission address management queues, even if the packet capacity is larger than the unit buffer and stored in multiple unit buffers by the transmission address management queue, one packet 3. The shared buffer type packet switch according to claim 2, wherein connection information of unit buffers constituting the management information is managed, and the management information does not move because the management information has the same information simultaneously in each device . Memory address when using have rows handshake addresses between idle address management queue and transmission address management queue or used address management queue, the path of the enqueue and dequeue address information, the time division data bus shared memory 4. The shared buffer packet switch according to claim 2, wherein the packet switch is performed using a bus . 4. The shared buffer packet switch according to claim 2, wherein the multicast management queue for temporarily holding the multicast packets individually manages the order of broadcast packets transmitted by each device unit . In the multicast packet buffer release processing, a means for recognizing that transmission to the destination managed by the device has been completed for each distributed device is present for each device, and transmission from each device is completed Upon receiving the notification, means for recognizing that all the devices have been transmitted is present in each device, and is operated simultaneously on the same device where the free address management queue is operated , and the buffer is released. 7. The shared buffer packet switch according to claim 6.

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