JP3613206B2 - Semiconductor IC output impedance matching method and matching method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an output impedance matching method for a semiconductor IC, and more particularly to an output impedance matching method for a semiconductor IC that performs impedance matching between an output buffer of the semiconductor IC and a wiring pattern outside the semiconductor IC.
[0002]
[Prior art]
In general, an output buffer of a semiconductor integrated circuit (hereinafter referred to as a semiconductor IC) has a fixed driving current, and transmits a signal by adjusting the characteristic impedance of the wiring pattern, or a resistor (dumping resistor) immediately after the output buffer. A method of connecting and matching the characteristic impedance of the wiring pattern was adopted. In recent years, devices that can change the drive current in a programmable manner have also been used. However, depending on the lot variation of the printed wiring board, the characteristic impedance of the wiring pattern may differ from the design value, and the drive current of the output buffer must be changed. is there.
[0003]
As prior arts for solving these problems, there are Japanese Laid-Open Patent Publication Nos. 11-017518 and 10-261948. However, these prior arts detect the voltages at the transmitting end and the receiving end of the output buffer and perform two processes. The output impedance is controlled so as to be between the threshold values.
[0004]
[Problems to be solved by the invention]
However, these prior arts do not have a clear way to determine this threshold voltage and depend on the designer's experience. In addition, starting from the minimum (or maximum) output impedance in order to determine the optimum output impedance, the output impedance is changed step by step, so that it takes time to obtain the optimum output impedance.
[0005]
Therefore, an object of the present invention is to ensure stable operation without obtaining a semiconductor IC or adding a damping resistor even when the characteristic impedance of such wiring patterns varies, and to obtain an optimum output impedance. is there.
[0006]
[Means for Solving the Problems]
According to the semiconductor IC output impedance matching method of the present invention, first, the output impedance matching of the semiconductor IC in the case of transmitting a signal from the first signal output terminal of the semiconductor IC to the first signal line provided with the electrical load. And a first impedance matching means provided between the internal circuit of the semiconductor IC and the first signal output terminal for matching the characteristic impedance between the internal circuit of the semiconductor IC and the first signal line. And signal generating means for generating the same signal as the output signal of the internal circuit of the semiconductor IC, and the first signal line connecting the signal input terminal and the second signal output terminal of the semiconductor IC to the electrical characteristics Are provided between the same second signal line and the signal generating means and the second signal output terminal to match the characteristic impedance of the signal generating means and the second signal line. of The second impedance matching means, which is the same as the impedance matching means, the subtracting means for subtracting both signal waveforms at the second signal output terminal and the signal input terminal, and the peak voltage of the subtraction signal and the reference voltage are compared. comparison means for detecting a magnitude relation, and characterized in that it comprises, and impedance control signal generating means for controlling said first and second impedance matching means based on the magnitude relationship detected by said comparing means.
[0007]
Secondly, in the semiconductor IC output impedance matching system according to the present invention, the first and second impedance matching means are field effect transistors.
[0008]
Thirdly, in the output impedance matching method of the semiconductor IC according to the present invention, the signal comparison means includes a subtracting circuit for calculating an amplitude difference between the rising portion overshoot or the falling portion undershoot of the two signal waveforms.
[0009]
Fourthly, in the semiconductor IC output impedance matching system according to the present invention, the signal comparison unit includes a peak value detection circuit for detecting a peak value voltage of the overshoot amplitude difference or the undershoot amplitude difference.
[0010]
In the semiconductor IC output impedance matching method according to the present invention, fifthly, the signal comparison means compares the peak value voltage of the peak value detection circuit output with a predetermined threshold voltage, and compares the result with the peak value voltage. And a voltage comparison circuit that outputs the first control signal. Further, in the semiconductor IC output impedance matching system according to the present invention, sixthly, the voltage comparison circuit includes a 1/2 power supply voltage generation circuit that supplies a half of the power supply voltage as the threshold voltage. Further, when a plurality of electrical loads are connected to the first signal line connected to the first signal output terminal, the same number of the electrical loads as the plurality of electrical loads are also connected to the second signal line. Provide a load.
[0011]
In the semiconductor IC output impedance matching method according to the present invention, first, output impedance matching of a semiconductor IC when a signal is transmitted from a first signal output end of the semiconductor IC to a first signal line having an electrical load. In the method, a first impedance matching step is provided between the internal circuit of the semiconductor IC and the first signal output terminal to match the characteristic impedance between the internal circuit of the semiconductor IC and the first signal line. And a signal generating step for generating the same signal as an output signal of an internal circuit of the semiconductor IC, and a signal input terminal and a second signal output terminal of the semiconductor IC are electrically connected to the first signal line. A step of connecting with the same second signal line, and a characteristic impedance between the signal generating means and the second signal output terminal provided between the signal generating means and the second signal output terminal. A second impedance matching step of taking matching, magnitude comparison and subtraction step of subtracting the two signal waveforms in said signal input terminal and said second signal output terminal, and a peak voltage with a reference voltage of the subtraction signal a comparing step of detecting a relationship, characterized in that it comprises a Louis impedance control signal generating step to drive the first and second impedance matching means based on the detected magnitude relation. In addition, as a second feature, in the signal comparison, a subtraction step of calculating an amplitude difference between the rising portion overshoot or the falling portion undershoot of the two signal waveforms is provided. Further, as a third feature, the signal comparison step includes a peak value detection step of detecting a peak value voltage of the amplitude difference of the overshoot or the amplitude difference of the undershoot. Furthermore, as a fourth feature, in the signal comparison step, the peak value voltage of the peak value detection circuit output is compared with a predetermined threshold voltage, and the result is output as the first control signal. And a voltage comparison step. As a fifth feature, the voltage comparison step includes a 1/2 power supply voltage generation step of supplying half the power supply voltage as the threshold voltage. Further, as a sixth feature, when the plurality of electrical loads are connected to the first signal line connected to the first signal output terminal, the plurality of electrical loads are also connected to the second signal line. Connecting the same number of electrical loads.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Next, description will be made with reference to the drawings.
[0013]
Referring to the block diagram of FIG. 1 showing the first embodiment of the present invention, the output circuit of the semiconductor IC of the present invention includes output buffers 13-1 to 13-3 on the output side of the semiconductor IC internal circuit 12, Drive current control circuits 14-1 to 14-3 connected to these outputs, and wiring patterns 3-1 to 3-3 connected to those outputs via signal output terminals 15-1 to 15-3 The input buffers 2-1 to 2-3 that terminate the wiring patterns, the signal generation circuit 111 that artificially generates a signal output from the semiconductor IC internal circuit 12, and the output buffer 13- connected to the output thereof The output buffer 112 having the same functions and characteristics as those of 1-13-3, the drive current control circuit 113 for adjusting the output impedance of the output buffer 112, and the pseudo signal from the signal generation circuit 111 of the output are signaled. The difference in level between the overshoot at the rising portion or the undershoot at the falling portion of the pseudo signal waveform 3-4 that turns back from the force end 15-4 to the signal input end 15-5 and the pseudo signal waveform at both ends of the pseudo wiring pattern 3-4. A subtracting circuit 114 to be calculated; a peak voltage detecting circuit 115 for detecting the maximum value of the differential signal of the output; a ½ power supply voltage generating circuit 116 for generating a voltage value half of the power supply voltage; A comparison circuit 117 that compares the peak value of the difference signal with a half voltage value of the ½ power supply voltage generation circuit 116 and outputs it as a difference level, and converts the difference level of the output into a drive current control signal to drive current. A control circuit 14-1 to 14-3 and a drive current control signal generation circuit 118 to be supplied to the drive current control circuit 113.
[0014]
Subsequently, the operation will be described. First, the consistency between the output impedance and the characteristic impedance of the wiring pattern will be described.
[0015]
The output signal of the normal CMOS output buffer is a ground potential (earth) and a power supply potential (power supply = VDD). However, when a transmission line having a characteristic impedance Z0 such as a wiring pattern is connected to the output buffer, if the output impedance of the output buffer is R0, the output signal at the sending end is divided by Z0 and R0, The voltage level becomes VDD × Z0 / (Z0 + R0), and this voltage level propagates on the transmission line, that is, on the wiring pattern here. Since the receiving end is normally electrically open, the input impedance is infinite, and the signal received here is reflected toward the transmitting end. The reflected signal is further reflected at the transmission end due to the relationship between Z0 and R0. However, since the matching condition is satisfied under the condition of R0 = Z0, the reflected wave is terminated here. That is, R0 = Z0 is ideal, and the voltage generated at the sending end must be VDD / 2 from the above equation. In the case of an integrated circuit in which the signal amplitude does not reach the power supply voltage, the same effect can be obtained by using the amplitude voltage instead of VDD in the above equation.
[0016]
Furthermore, a method for detecting that the output signal at the transmission end is a voltage of VDD / 2 will be described.
[0017]
4, 5, and 6 show the simulation results when the output impedance of the output buffer is larger than the characteristic impedance of the wiring pattern, FIG. 4 shows the simulation results, and FIG. 6 shows the simulation results when the output impedance is the same. ing. Each of these figures shows the waveform at the transmitting end, the waveform at the receiving end, and the waveform of the calculation result of “transmitting end−receiving end”. From this “transmission end-reception end” waveform, when the impedance is matched, it can be confirmed that the peak value (maximum value) of the calculation result matches VDD / 2. Therefore, if this peak value is compared with a voltage value that is half of the power supply voltage and this difference is fed back to the drive current control circuits 14-1 to 14-3 as a control signal, the output buffers 13-1 to 13-3 The output impedance can be controlled.
[0018]
Here, the subtraction circuit 114 and the peak voltage detection circuit 115 can be realized as an operational amplifier.
[0019]
Next, details of the operation will be described with reference to FIG.
[0020]
In FIG. 3, field effect transistors (FETs) are used as the drive current control circuits 14-1 to 14-3 shown in FIG. This FET is an element whose impedance between the drain and the source changes according to the gate voltage. The 1/2 power supply voltage generation circuit 116 can be realized by resistance-dividing the power supply voltage, and the comparison circuit 8 can be realized by an operational amplifier.
[0021]
The drive current control of the output buffer in the present invention is executed once when the output buffer is turned on, so that the drive currents of all the output buffers are automatically adjusted.
[0022]
More specifically, the pseudo signal output from the signal generator 111 drives the pseudo wiring pattern 3-4 drawn for adjusting the driving capability through the output buffer 112 and the drive current control circuit 113 through the signal output terminal 15-4. To do. In the initial state, it is desirable that the impedance of the drive current control circuit 113 is high, that is, the drive current is small. This is because when the characteristic impedance of the pseudo wiring pattern 3-4 is much larger than expected, the withstand voltage on the receiving side may be exceeded by the overshoot (or the undershoot of the falling portion) of the waveform due to reflection. Because there is. Therefore, in the first pseudo signal transmission, a waveform as shown in FIG. 4 is observed. At this time, the waveform sig. A and waveform sig. From the signal difference with B, the peak voltage detection circuit 115 holds a voltage smaller than half of the power supply voltage. Therefore, the comparison circuit 117 determines that “sig.A-sig.B” <power supply voltage / 2, raises the gate voltage of the drive current control circuit 113 through the drive current control signal generation circuit 118, and drain / source Try to reduce the impedance between.
[0023]
As a result, the voltage of the transmission end waveform (sig.A) that passes through the output buffer 112 and the drive current control circuit 113 increases, and the peak voltage of “sig.A-sig.B” approaches the power supply voltage / 2. To do.
[0024]
Conversely, when the impedance between the drain and source of the drive current control circuit 113 is small, that is, when the drive current is large, the comparison circuit 117 determines “sig.A-sig.B”> power supply voltage / 2. The gate voltage of the drive current control circuit 113 is lowered through the drive current control signal generation circuit 118 to increase the drain-source impedance.
[0025]
By repeating these operations, “sig.A-sig.B” = power supply voltage / 2, that is, a stable waveform as shown in FIG. 5 can be finally obtained.
[0026]
Here, the drive current of all the output buffers 13-1 to 13-3 is optimized by providing the drive current control signal generation circuit 118 with the gate voltage holding function of the final drive current control circuit 113. Can do. That is, the wiring patterns 3-1 to 3-3 from the semiconductor IC internal circuit 12 through the output buffers 13-1 to 13-3, the drive current control circuits 14-1 to 14-3, and the signal output terminals 15-1 to 15-3. All signals output to are optimized.
[0027]
Next, a second embodiment of the present invention will be described with reference to FIG.
[0028]
The second embodiment of FIG. 2 is a case where a plurality of input buffers 2-4 to 2-9 are connected to the wiring patterns 3-1 to 3-3. When these input buffers 2-4 to 2-9 are connected on the multiple wiring patterns 3-1 to 3-3, the characteristic impedance may be reduced equivalently. Thus, by connecting the input buffers 2-10 to 2-11 to the pseudo wiring pattern 3-4 in the same manner, it is possible to adjust the driving current with high accuracy.
[0029]
【The invention's effect】
As described above, according to the present invention, by automatically matching the drive capacity of the output buffer with the characteristic impedance of the actual wiring pattern, the waveform can be stabilized and the operation speed can be increased. It is possible to design the wiring of the substrate without worrying about the characteristic impedance. In addition, a high-precision printed wiring board for eliminating the variation in the characteristic impedance accuracy of the wiring pattern of the printed wiring board from lot to lot is very expensive. However, by using the present invention, the variation between lots is completely ignored. Therefore, an inexpensive printed wiring board can be used.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an output circuit of a semiconductor IC according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing an output circuit of a semiconductor IC according to a second embodiment of the present invention.
FIG. 3 is a specific block diagram showing an output circuit of the semiconductor IC according to the first embodiment of the present invention.
4 is a waveform diagram showing a first signal waveform simulation result of the output circuit of the semiconductor IC in the embodiment; FIG.
FIG. 5 is a waveform diagram showing a second signal waveform simulation result of the output circuit of the semiconductor IC in the embodiment;
6 is a waveform diagram showing a third signal waveform simulation result of the output circuit of the semiconductor IC in the embodiment; FIG.
[Explanation of symbols]
1 Semiconductor IC
2-1 to 2-3 Input Buffers 3-1 to 3-3 Wiring Pattern 3-4 Pseudo Wiring Pattern 11 Drive Capability Control Unit 12 Semiconductor IC Internal Circuits 13-1 to 13-3 Output Buffers 14-1 to 14-3 Drive Current Control Circuits 15-1 to 15-4 Signal Output Terminal 15-5 Signal Input Terminal 111 Signal Generation Circuit 112 Output Buffer 113 Drive Current Control Circuit 114 Subtraction Circuit 115 Peak Voltage Detection Circuit 116 1/2 Power Supply Voltage Generation Circuit 117 Comparison Circuit 118 Drive current control signal generation circuit

Claims (13)

In an output impedance matching system of a semiconductor IC when a signal is transmitted from a first signal output terminal of the semiconductor IC to a first signal line having an electrical load, the internal circuit of the semiconductor IC and the first signal output A first impedance matching means provided between the end of the semiconductor IC and matching the characteristic impedance of the internal circuit of the semiconductor IC and the first signal line; and the same signal as the output signal of the internal circuit of the semiconductor IC. A signal generating means for generating; a second signal line having the same electrical characteristics as the first signal line connecting the signal input terminal and the second signal output terminal of the semiconductor IC; the signal generating means; A second impedance matching means provided between the second signal output terminal and the same as the first impedance matching means for matching the characteristic impedance between the signal generating means and the second signal line. A subtracting means for subtracting both signal waveforms at the second signal output terminal and the signal input terminal, a comparing means for comparing a peak voltage of the subtracted signal with a reference voltage, and detecting a magnitude relationship , and the comparison An output impedance matching method for a semiconductor IC, comprising: impedance control signal generating means for controlling the first and second impedance matching means based on a magnitude relationship detected by the means . 2. A semiconductor IC output impedance matching system according to claim 1, wherein said first and second impedance matching means are field effect transistors. 2. The output impedance matching method for a semiconductor IC according to claim 1, wherein the signal comparison means includes a subtracting circuit for calculating an amplitude difference between the rising portion overshoot or the falling portion undershoot of the two signal waveforms. 4. The output impedance matching of a semiconductor IC according to claim 1, wherein said signal comparing means includes a peak value detection circuit for detecting a peak value voltage of the amplitude difference of the overshoot or the amplitude difference of the undershoot. method. The signal comparison means includes a voltage comparison circuit that compares the peak value voltage of the peak value detection circuit output with a predetermined threshold voltage and outputs the result as the first control signal. 5. The semiconductor IC output impedance matching system according to claim 1 or 4. 6. The semiconductor IC output impedance matching system according to claim 5, wherein the voltage comparison circuit includes a 1/2 power supply voltage generation circuit that supplies a half of a power supply voltage as the threshold voltage. When a plurality of electrical loads are connected to the first signal line connected to the first signal output terminal, the same number of electrical loads as the plurality of electrical loads are also connected to the second signal line. 2. The semiconductor IC output impedance matching method according to claim 1, further comprising: In an output impedance matching method for a semiconductor IC when a signal is transmitted from a first signal output terminal of the semiconductor IC to a first signal line having an electrical load, the internal circuit of the semiconductor IC and the first signal output A first impedance matching step that is provided between the semiconductor IC and the first signal line to match the characteristic impedance of the internal circuit of the semiconductor IC, and the same signal as the output signal of the internal circuit of the semiconductor IC. A signal generation step to be generated; and
Connecting a signal input terminal and a second signal output terminal of the semiconductor IC with a second signal line having the same electrical characteristics as the first signal line;
A second impedance matching step provided between the signal generating means and the second signal output terminal for matching characteristic impedances of the signal generating means and the second signal line;
A subtracting step of subtracting both signal waveforms at the second signal output terminal and the signal input terminal, a comparing step of comparing a peak voltage of the subtracted signal with a reference voltage and detecting a magnitude relationship; output impedance matching method of a semiconductor IC, characterized in that it comprises a Louis impedance control signal generation step controls said first and second impedance matching means based on the magnitude relation, the. " 9. The output impedance matching method for a semiconductor IC according to claim 8, further comprising a subtracting step of calculating an amplitude difference between an overshoot of a rising portion or an undershoot of a falling portion of the both signal waveforms in the signal comparison. 10. The output impedance matching of a semiconductor IC according to claim 8, further comprising a peak value detecting step of detecting a peak value voltage of the amplitude difference of the overshoot or the amplitude difference of the undershoot in the signal comparison step. Method. In the signal comparison step, the peak value voltage of the peak value detection circuit output is compared with a predetermined threshold voltage, and the result is compared with the first value. 1 11. A method for matching output impedance of a semiconductor IC according to claim 8, further comprising a voltage comparison step of outputting the control signal as a control signal. 12. The output impedance matching method for a semiconductor IC according to claim 11, wherein the voltage comparison step includes a half power supply voltage generation step of supplying half the power supply voltage as the threshold voltage. When the plurality of electrical loads are further connected to the first signal line connected to the first signal output terminal, the same number of the electrical loads as the plurality are also applied to the second signal line. 9. The output impedance matching method for a semiconductor IC according to claim 8, further comprising a step of connecting.

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