JP3612381B2 - Logic simulation device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a logic simulation apparatus used for simulating a logic operation of a semiconductor integrated circuit.
[0002]
[Prior art]
In the development of a digital LSI (Large Scale Integrated circuit), a logic simulation apparatus is used to verify a logic design. The logic simulation apparatus performs a simulation of an operation as a logic circuit of an LSI to be designed based on a logic design result, that is, a logic simulation. The result of the logic simulation is compared with the specification of the LSI. If the two do not match, the logic circuit as the design result is corrected and the logic simulation is further performed. In this way, the logic circuit correction and the logic simulation are performed until the LSI specifications and the logic simulation result match, and the logic design is completed when the two match. Thereafter, an LSI is manufactured based on the logical design result. If the LSI logic simulation result matches the LSI specification, the operation of the actually manufactured LSI also matches the specification.
[0003]
By the way, with recent advances in semiconductor microfabrication technology, the degree of integration of LSIs has dramatically increased, and a system that could only be realized on a printed circuit board can now be realized with a one-chip LSI. It is coming. As a result, the number of LSI pins is increasing. That is, LSIs tend to be “multi-pin”. In addition, advances in semiconductor microfabrication technology have led to dramatic improvements in operating speed in addition to increased integration. In other words, LSIs also tend to be “accelerated”.
[0004]
With the increase in speed and the number of pins of LSIs, various problems have arisen in the LSI development process. For example, the logic simulation at the design stage operates completely according to the specifications, but does not operate according to the specifications at the stage where the manufactured LSI is tested or mounted on the board and actually used. This has become a major problem as LSIs increase in speed and increase in pin count (for example, Takashi Yoshimori and Toshiaki Mori “Transmission and Noise Characteristics of High-Speed Multi-Pin CMOS Devices”, IEICE Technology) Research report ICD 88-79, Vol. 88, No. 230, pp. 47-53 (October 20, 1988)).
[0005]
The cause of this problem is that although the influence of noise has become so large that it cannot be ignored with the increase in LSI speed and the number of pins, this is not taken into consideration in the logic simulation. In other words, since the logic simulation was performed ignoring noise, there was a situation in which the actually manufactured LSI did not operate normally in spite of the LSI operating normally in the logic simulation.
[0006]
Among the noises that cause this problem, simultaneous switching noise has the greatest effect. That is, when a plurality of output buffers in an LSI are simultaneously switched, the influence of a wave-like fluctuation (called “ground bounce”) on the ground potential caused by the inductance of the ground pin parasitic to the package is large (David Shear “high-speed CMOS”). “Testing the ground bounce of standard logic IC”, Nikkei Electronics, May 15, 1989, no. 473, pp. 226-227).
[0007]
FIG. 5 is a diagram for explaining the influence of such simultaneous switching noise, and shows a circuit configuration of an input / output unit in an LSI. If the output buffers 101 and 102 are simultaneously switched, current flows from the power supply line through the output buffers 101 and 102 to the ground line, and the current flowing through the ground pin changes greatly. When the current flowing through the ground pin greatly changes, the ground line potential in the LSI, that is, the reference potential, fluctuates due to the inductance Lp of the ground pin parasitic in the LSI package (occurrence of ground bounce). When the reference potential of the LSI fluctuates in this way, the potential of the input signal to the input buffer 103 fluctuates apparently, and if the fluctuation exceeds the threshold voltage of the input buffer 103, the LSI malfunctions. As the LSI speed increases and the number of pins increases, the current change rate di / dt due to the simultaneous switching of the output buffer increases and the ground bounce increases, and thus more malfunctions occur. .
[0008]
On the other hand, conventionally, various countermeasures have been considered in order to suppress the influence of the simultaneous switching. In other words, measures to reduce the ground bounce itself by reducing the parasitic inductance Lp or reducing the current change rate di / dt, and the power source / ground of the input buffer and the power source / ground of the output buffer are separated. In order to prevent the influence of the ground bounce from being transmitted to the input buffer by dispersing the current causing the noise by appropriately arranging the ground pins.
[0009]
However, many of the conventional measures are not necessarily satisfactory in effect, increase costs, and limit the scope of application. Only the following measures are considered. This measure (hereinafter referred to as “conventional solution”) is often used in practice.
“Define the number of output buffers that can be simultaneously switched per ground pin, and arrange the ground pins appropriately so that the limit is not exceeded.”
Specific contents of the above solution are described in the following documents.
(1) Public Utility Model Publication No. Sho 63-20440
(2) “I / O cell selection and pin assignment”, CMOS Standard Cell RCS-08A Series Design Manual (Ricoh Co., Ltd.), p. 6-3
(3) “Digital waveform verification shifts from oscilloscope to circuit simulator”, Nikkei Electronics, July 31, 1995, no. 641, p. 184
[0010]
[Problems to be solved by the invention]
However, the conventional solution described above does not fundamentally solve the problems associated with the increase in the speed and the number of pins of the LSI, and has the following problems. The first problem is that the actual LSI uses different conditions depending on the product type, so the tolerance required for noise differs accordingly, and the “limit of the number of output buffers for simultaneous switching” itself is Since this is only a guideline, the effect as a solution is ambiguous and the effect cannot be quantitatively grasped. The second problem is that even though it is not actually necessary to add a ground pin, a situation occurs in which the ground pin is added in order not to exceed the above-mentioned “restriction”. There is a risk of a rise.
[0011]
By the way, the problem with increasing the speed and the number of pins of an LSI is that, in the logic simulation, the actually manufactured LSI does not operate normally although the LSI operates normally. The conventional countermeasures including the above-described solution have attempted to solve this problem by suppressing the simultaneous switching noise (ground bounce) that is the cause. However, it is impossible to completely suppress the noise by any countermeasures, and the simultaneous switching noise tends to increase as the LSI speed increases and the number of pins increases. The method cannot be a fundamental solution in nature.
[0012]
Therefore, in the present invention, considering that it is impossible to completely suppress the simultaneous switching noise, an LSI that does not actually operate normally due to the simultaneous switching noise is not normally operated by simulation at the design stage in advance. It is an object of the present invention to provide a logic simulation device that can be detected.
[0013]
[Means for Solving the Problems]
<First aspect>
In order to solve the above problems, in the first logic simulation apparatus according to the present invention, the operation of the semiconductor integrated circuit that inputs and outputs digital signals corresponds to the H level corresponding to the potential of the power supply line and the potential of the ground line. In a logic simulation apparatus that simulates the operation of a logic circuit with at least three types of signal values of L level and indefinite state X,
First input means for inputting a value of a power supply voltage Vdd supplied to the power supply line;
Second input means for inputting the minimum value VIH of the H level input voltage and the maximum value VIL of the L level input voltage of the input buffer in the integrated circuit;
Simultaneous switching detection means for detecting output buffers that switch simultaneously in the logic simulation process;
Calculation means for calculating the magnitude of the ground bounce ΔV caused by simultaneous switching of the output buffer based on the detection result by the simultaneous switching detection means;
A value Vdd-ΔV obtained by subtracting the ground bounce magnitude ΔV from the power supply voltage Vdd is output as an H level input voltage effective value, and the ground bounce magnitude ΔV is output as an L level input voltage effective value. A value calculating means;
Input value determination means for determining whether the value of a signal input from the outside of the integrated circuit to each input buffer in the integrated circuit is H level or L level;
For the input buffer determined by the input value determination means that an H level signal is input,
i) If the effective value of the H level input voltage is equal to or greater than the minimum value VIH of the H level input voltage of the input buffer, an H level signal is input to the input buffer;
ii) If the effective value of the H level input voltage is smaller than the minimum value VIH of the H level input voltage of the input buffer and larger than the maximum value VIL of the L level input voltage of the input buffer, the signal in the indefinite state X is Iii) If the effective value of the H level input voltage is less than the maximum value VIL of the L level input voltage of the input buffer, an L level signal is input to the input buffer. Suppose,
First control means for continuing the logic simulation while performing the first input value resetting process,
For the input buffer determined by the input value determination means that an L level signal is input,
i) If the effective value of the L level input voltage is less than or equal to the maximum value VIL of the L level input voltage of the input buffer, an L level signal is input to the input buffer;
ii) If the effective value of the L level input voltage is smaller than the minimum value VIH of the H level input voltage of the input buffer and larger than the maximum value VIL of the L level input voltage of the input buffer, the signal in the undefined state X is Iii) If the effective value of the L level input voltage is not less than the minimum value VIH of the H level input voltage of the input buffer, an H level signal is input to the input buffer. Suppose,
Second control means for continuing the logic simulation while performing the second input value resetting process,
It is set as the structure provided with.
[0014]
According to such a configuration, an output buffer that switches simultaneously is detected at each time point in the simulation, and the magnitude of the ground bounce ΔV caused by the simultaneous switching is calculated based on the detection result. This ΔV is an L level input voltage effective value, and a value Vdd−ΔV obtained by subtracting ΔV from the power supply voltage Vdd is an H level input voltage effective value. These effective values and the maximum of the L level input voltage of the input buffer The value of the input signal to the input buffer is corrected according to the magnitude relationship between the value VIL and the minimum value VIH of the H level input voltage, and the logic simulation is continued based on the corrected value.
[0015]
<Second aspect>
In the second logic simulation apparatus according to the present invention, in the first logic simulation apparatus,
A third input means for inputting a maximum value ΔV1 of a fluctuation amount in a wave-like fluctuation of the potential of the ground line generated when one output buffer is switched in the integrated circuit;
The calculation means calculates the product of the maximum bounce amount ΔV1 input by the third input means and the product ΔV1 · N of the number N of simultaneous switching output buffers detected by the simultaneous switching detection means as the magnitude of the ground bounce. ΔV
It is characterized by that.
[0016]
<Third Aspect>
In a third logic simulation apparatus according to the present invention, in the first logic simulation apparatus,
A fourth input means for inputting an inductance Lp of a ground pin parasitic to the package of the integrated circuit;
A fifth input for inputting a change amount dI / dt per unit time of the current I flowing from the power supply line through the output buffer to the ground line when one output buffer in the integrated circuit is switched. Means and
The calculating means calculates the inductance Lp inputted by the fourth input means, the change amount dI / dt inputted by the fifth input means, and the number N of the simultaneous switching output buffers detected by the simultaneous switching detecting means. Using the grand bounce magnitude ΔV.
ΔV = Lp · (dI / dt) · N
Calculated by
It is characterized by that.
[0017]
<Fourth aspect>
In a fourth logic simulation apparatus according to the present invention, in the first logic simulation apparatus,
A fourth input means for inputting an inductance Lp of a ground pin parasitic to the package of the integrated circuit;
When one output buffer in the integrated circuit is switched, a value dIj / dt for each output buffer of a change amount per unit time of a current flowing from the power supply line through the output buffer to the ground line is input. And an eighth input means for
The calculation means detects the product Lp · (dIj / dt) of the inductance Lp input by the fourth input means and the change amounts dIj / dt input by the eighth input means by the simultaneous switching detection means. Based on the above, the sum of the output buffers that switch simultaneously is defined as the ground bounce magnitude ΔV.
It is characterized by that.
[0018]
<Fifth aspect>
In a fifth logic simulation apparatus according to the present invention, in the first logic simulation apparatus,
A fourth input means for inputting an inductance Lp of a ground pin parasitic to the package of the integrated circuit;
A fifth input for inputting a change amount dI / dt per unit time of the current I flowing from the power supply line through the output buffer to the ground line when one output buffer in the integrated circuit is switched. Means,
Second storage means for storing layout data indicating the layout design result of the integrated circuit and pin arrangement data;
Ground pin recognition means for recognizing a ground pin of the package of the integrated circuit based on the layout data and pin arrangement data and outputting identification information of the ground pin;
When there are a plurality of pins recognized as ground pins by the ground pin recognizing unit, the calculating unit calculates the logic based on the change amount dI / dt inputted by the fifth input unit and the detection result by the simultaneous switching detecting unit. It is assumed that the current I passing through each output buffer that switches simultaneously in the simulation process flows in half to the left ground pin closest to the output buffer pin and the right ground pin closest to the output buffer pin. A change amount dIg / dt per unit time is calculated, and ΔVg = Lp · (dIg / dt) calculated for each ground pin using the change amount dIg / dt and the inductance Lp input by the fourth input means. The maximum value of which is the ground bounce magnitude ΔV. ing.
[0019]
<Sixth aspect>
In a sixth logic simulation apparatus according to the present invention, in the first logic simulation apparatus,
A tenth input means for inputting a minimum value VOH of the H level output voltage and a maximum value VOL of the L level output voltage of the output buffer of the integrated circuit;
A value Vdd−ΔV obtained by subtracting the ground bounce magnitude ΔV from the power supply voltage Vdd is output as an H level output voltage effective value, and the ground bounce magnitude ΔV is output as an L level output voltage effective value. A value calculating means;
Output value determination means for determining whether the value of a signal output from each output buffer of the integrated circuit to the outside of the integrated circuit is H level or L level;
For the output buffer determined by the output value determining means to output an H level signal,
i) If the effective value of the H level output voltage is equal to or higher than the minimum value VOH of the H level output voltage of the output buffer, an H level signal is output from the output buffer;
ii) If the effective value of the H level output voltage is smaller than the minimum value VOH of the H level output voltage of the output buffer and larger than the maximum value VOL of the L level output voltage of the output buffer, the signal in the undefined state X is It is assumed that it is output from the output buffer,
iii) If the H level output voltage effective value is less than or equal to the maximum value VOL of the L level output voltage of the output buffer, an L level signal is output from the output buffer.
Third control means for continuing the logic simulation while performing the first output value resetting process;
For the output buffer determined by the output value determination means that the L level signal is output,
i) If the effective value of the L level output voltage is less than or equal to the maximum value VOL of the L level output voltage of the output buffer, an L level signal is output from the output buffer;
ii) If the effective value of the L level output voltage is smaller than the minimum value VOH of the H level output voltage of the output buffer and larger than the maximum value VOL of the L level output voltage of the output buffer, the signal in the undefined state X is It is assumed that it is output from the output buffer,
iii) If the L level output voltage effective value is not less than the minimum value VOH of the H level output voltage of the output buffer, an H level signal is output from the output buffer.
Fourth control means for continuing the logic simulation while performing the second output value resetting process,
It is characterized by having.
[0020]
According to the sixth logic simulation device, during the logic simulation, not only the input value resetting process but also the output value setting process are performed based on the calculated ground bounce magnitude ΔV. This is reflected in not only the input value but also the output value.
[0021]
<Other aspects>
In the second to fifth logic simulation apparatuses, as means for obtaining the parasitic inductance (inductance parasitic to the integrated circuit package) Lp of the ground pin necessary for calculating the magnitude of ground bounce ΔV by simultaneous switching, In addition to the four input means, the following means can be used.
(1) To input first storage means for storing the parasitic inductance for each pin of the package of the integrated circuit as a package data file for each package type, and identification information for specifying the package type of the integrated circuit The package using the sixth input means, the seventh input means for inputting pin identification information indicating the ground pin of the package of the integrated circuit, and the identification information input by the sixth and seventh input means as keys. Means comprising first search means for obtaining an inductance Lp of a ground pin in a specific type of package by searching a data file;
(2) Instead of the seventh input means, second storage means for storing layout data and pin arrangement data indicating a result of layout design of the integrated circuit, and the above-described data based on the layout data and pin arrangement data. Ground pin recognition means for recognizing the ground pin of the package of the integrated circuit and outputting the identification information of the ground pin, wherein the first search means is for the identification information of the ground pin inputted by the seventh input means. Instead, means for obtaining an inductance Lp of a ground pin in a specific type of package by searching the package data file using ground pin identification information output from the ground pin recognition means as a key.
[0022]
In the fourth logic simulation apparatus, the through current change rate for each output buffer (the current flowing from the power supply line through the output buffer to the ground line is necessary for calculating the magnitude of the ground bounce ΔV by simultaneous switching. As a means for obtaining (change amount per unit time) dIj / dt, the following means can be used in addition to the eighth input means.
When one output buffer in the integrated circuit is switched, the amount of change dIj / dt per unit time of the current flowing from the power supply line through the output buffer to the ground line is changed according to the type of output buffer. Third storage means stored as a data file and an output buffer that switches simultaneously by searching the output buffer data file using identification information indicating the type of output buffer detected by the simultaneous switching detection means as a key Means for obtaining the change amounts dIj / dt.
[0023]
Furthermore, in the logic simulation apparatus of the various aspects described above, as specific detection means for the output buffer that switches simultaneously in the logic simulation process, in addition to means for detecting all output buffers whose signals change at the same time on the simulation, The following means can be used.
(1) A means for detecting output buffers that switch within a predetermined time interval inputted in advance as switching at the same time.
(2) Means for excluding predetermined output buffers from detection targets and detecting output buffers that are switched simultaneously.
(3) Recognizing means for recognizing a ground pin based on pre-stored integrated circuit layout data and pin arrangement data, and connecting to a pin sandwiched between two predetermined ground pins based on the recognition result Means for detecting output buffers that perform switching simultaneously with only the output buffer as a detection target.
(4) Of signal changes from one signal value included in a signal value group including at least three types of signal values of H level, L level, and indefinite state X to another signal value included in the signal value group, Means for designating a signal change that the simultaneous switching detection means recognizes as switching of the output buffer, and detecting an output buffer that switches simultaneously based on designation of the signal change by the first designation means;
[0024]
Further, in the logic simulation apparatus of various aspects described above, the following means can be used in order to limit the input buffer that is the target of the input value resetting process.
(1) Second designation means for designating an input buffer to be subjected to first and second input value resetting processing by the first and second control means.
(2) Second storage means for storing layout data and pin arrangement data indicating the layout design result of the integrated circuit, and first and second input value resetting processes by the first and second control means. The third designation means for designating whether or not to limit the input buffer to be subject to the third input means, the third designation means to limit the input buffer to be subject to the first and second input value resetting processing. A ground pin between the output buffer pins closest to the simultaneously switched output buffer pins to be detected by the simultaneous switching detection means based on the layout data and the pin arrangement data. Means for excluding an input buffer in which the first and second input values are reset.
[0025]
Further, in the logic simulation apparatus of the various aspects described above, the minimum values VIH and L level inputs of the H level input voltage of the input buffer required when performing the input value resetting process based on the ground bounce magnitude ΔV by simultaneous switching. In order to obtain the maximum voltage value VIL, the following means can be used in addition to the second input means.
Fourth storage means for storing the minimum value VIH of the H level input voltage and the maximum value VIL of the L level input voltage as input voltage data files for each type of input buffer, and the identification information indicating the type of the input buffer as a key. Means comprising: third search means for obtaining a minimum value VIH of the H level input voltage and a maximum value VIL of the L level input voltage of the desired input buffer by searching the input voltage data file;
[0026]
Further, in the sixth logic simulation apparatus, the minimum values VOH and L level output of the H level output voltage of the output buffer required when the output value resetting process is performed based on the magnitude of the ground bounce ΔV by simultaneous switching. In order to obtain the maximum voltage VOL, the following means can be used in addition to the tenth input means.
The fifth storage means for storing the minimum value VOH of the H level output voltage and the maximum value VOL of the L level output voltage of the output buffer as output voltage data files for each type of output buffer, and identification information indicating the type of output buffer Means comprising fourth search means for obtaining the minimum value VOH of the H level output voltage and the maximum value VOL of the L level output voltage of the desired output buffer by searching the output voltage data file as a key;
[0027]
【The invention's effect】
According to the present invention, at each time point in the simulation, an output buffer that switches simultaneously is detected, and a ground bounce magnitude ΔV is calculated based on the detection result, and an input to the input buffer is based on the value of ΔV. By correcting the signal value, simultaneous switching noise is reflected in the simulation result. Therefore, if the integrated circuit malfunctions due to simultaneous switching noise, it can be detected by logic simulation. Therefore, it is possible to avoid a situation where the integrated circuit actually operates in the logic simulation but the actually manufactured integrated circuit does not operate normally, and the reliability of the logic simulation is improved compared to the conventional case. . As a result, the design efficiency of the integrated circuit is improved.
[0028]
Further, according to the present invention, the malfunction of the integrated circuit due to the simultaneous switching noise can be predicted by the logic simulation and can be dealt with at the design stage. Therefore, the integrated circuit test stage, which is caused by the malfunction caused by the simultaneous switching noise, Troubles at the actual use stage can be reduced.
[0029]
Furthermore, according to the present invention, when a ground pin is added to reduce / remove noise or a parasitic inductance in a package is reduced, excessive ground pins are added by a logic simulation considering the influence of simultaneous switching noise. And excessive reduction of parasitic inductance in the package can be prevented. Thereby, the cost of the packaged semiconductor integrated circuit can be suppressed as compared with the conventional case.
[0030]
Also, according to the third logic simulation device of the various aspects of the present invention, the magnitude of the ground bounce is based on the inductance Lp of the ground pin parasitic to the package and the through current change rate dI / dt of the simultaneous switching output buffer. ΔV is calculated, and according to the fourth logic simulation apparatus of the present invention, the output buffer through current change rate is input as a value dIj / dt for each output buffer, and is used to determine the magnitude of the ground bounce. Since ΔV is calculated, accuracy as a logic simulation considering simultaneous switching noise is improved. Furthermore, according to the fifth logic simulation apparatus of the present invention, when there are a plurality of ground pins, the ground bounce magnitude ΔV can be appropriately calculated and the simulation can be performed with high accuracy. Further, according to the sixth logic simulation apparatus of the present invention, the influence of the simultaneous switching noise is also reflected in the output value, so that a malfunction caused by the simultaneous switching noise can be detected better.
[0031]
In the logic simulation apparatus of the present invention, in order to obtain the parasitic inductance Lp of the ground pin necessary for calculating the ground bounce magnitude ΔV, the package data file stored in the storage means is specified as the package type. By providing a means for searching using the identification information to be identified and the identification information of the ground pin as a key, it is possible to reduce the operation by the user and improve the operability. At this time, by providing means for automatically recognizing the ground pin based on the layout data and pin arrangement data of the integrated circuit stored in the storage means instead of the user inputting the identification information of the ground pin, the operability is improved. Can be further improved. Further, when obtaining the through current change rate dIj / dt for each output buffer, the output buffer data file stored in the storage means is searched using the identification information indicating the type of the output buffer that is simultaneously switched as a key. By providing, it is possible to reduce the operation by the user and improve the operability. Further, when obtaining the minimum value VIH of the H-level input voltage and the maximum value VIL of the L-level input voltage of the input buffer that require input value reset processing, the minimum of the H-level output voltage of the output buffer that requires output value reset processing When obtaining the value VOH and the maximum value VOL of the L level output voltage, the operability can be improved by providing the same means.
[0032]
Further, as a means used when detecting the simultaneous switching output buffer necessary for calculating the ground bounce magnitude ΔV, the user can define a finite period that can be considered “simultaneous” in the switching of the output buffer. Logic simulation that enables detailed setting of noise influence calculation conditions by providing means, means for excluding a predetermined output buffer from detection targets, and means for specifying signal changes considered as switching among signal changes in the output buffer Controllability can be improved. In addition, the controllability of the logic simulation can be improved by providing means for limiting the input buffer that is the target of the input value resetting process. By using these means, by excluding output buffers that are less affected by simultaneous switching noise from the detection target, or by removing input buffers that are less affected by simultaneous switching noise from the input value reset processing, There is also an effect that the time required for the logic simulation is shortened.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
<Overall Configuration of Embodiment>
FIG. 2 is a diagram illustrating a hardware configuration of the logic simulation apparatus according to the embodiment of the present invention. The hardware of this logic simulation device is a computer such as an engineering workstation, and includes a data processing device 50 including a CPU 56 and a memory 58, a hard disk device 52, a keyboard 54, a mouse 55, and a display device 60. And a printer 62.
[0034]
In this embodiment, when the CPU 56 operates based on a predetermined program stored in the memory 58, the computer functions as a logic simulation device that simulates the operation of the digital LSI as a logic circuit. FIG. 1 is a functional block diagram conceptually showing the configuration of the logic simulation apparatus of the present embodiment realized in this way. As shown in this figure, the logical simulation apparatus conceptually includes a test pattern storage unit 18, a simulator body 16, a display unit 20, a noise influence calculation condition input unit 10, a noise influence calculation unit 12, and the like. The noise influence calculation condition storage unit 14 includes a test pattern storage unit 18, a simulation main body 16, and a display unit 20 (a portion surrounded by a dotted line). It corresponds to a device.
[0035]
In the above configuration, the test pattern storage unit 18 is realized by the hard disk device 52, and in order to verify the logical operation of the LSI to be simulated (hereinafter referred to as “target LSI”), the input pin of the LSI at each time on the simulation A pattern composed of logical values of signals to be applied to is stored as a test pattern.
[0036]
The simulator body 16 is realized by the data processing device 50 and reads data describing the configuration of the target LSI as a logic circuit stored in advance in the hard disk device 52 based on the operation of the keyboard 54 and mouse 55 by the user. Using the test pattern stored in the storage unit 18, the logic operation of the target LSI is simulated. As a specific simulation method, a well-known conventional method such as a table driven method can be used. As signal values that can be taken by each signal of the target LSI, in addition to “0” and “1”, four types of values including “X” indicating an indefinite state and “Z” indicating a high impedance state are included. The L level corresponding to the voltage value of the ground line of the target LSI is made to correspond to the signal value (logic value) “0”, and the H level corresponding to the voltage value of the power supply line is set to the signal value (logic value) “ 1 ”. In the following, for the sake of convenience, the logical value “0” is represented by “L”, and the logical value “1” is represented by “H”.
[0037]
The display unit 20 is realized by the display device 60 and the printer 62, and displays a signal change (change in logical value) or the like of the output pin of the target LSI on the display device 60 as a simulation result or outputs it to the printer 62. Further, the signal change that should be obtained at the output pin when the target LSI operates correctly, that is, the expected value, and the signal change of the output pin that is the actual simulation result can be compared with each other in the display device 60. It is displayed or output to the printer 62.
[0038]
The noise influence calculation condition input unit 10 is data (hereinafter referred to as “noise influence calculation condition data”) indicating conditions for calculating the influence of the simultaneous switching noise described later based on the operation of the keyboard 54 and the mouse 55 by the user. In the target LSI, the power supply voltage Vdd, the minimum value VIH of the H level input voltage of the input buffer, the maximum value VIL of the L level input voltage, and the like are input.
[0039]
The noise influence calculation condition storage unit 14 is realized by the hard disk device 52, collects data usable as the noise influence calculation condition data, and stores each data as a data file in association with predetermined identification information.
[0040]
The noise influence calculation unit 12 is realized by the data processing device 50 and includes a calculation unit main body and a control unit. The calculation unit main body obtains data on the output buffer that is simultaneously switched from the simulation result in the simulator main body 16, and using this data, noise influence calculation condition data or noise influence calculation input from the noise influence calculation condition input unit 10. Under the conditions indicated by the noise influence calculation condition data obtained from the condition storage unit 14, the ground bounce magnitude ΔV due to simultaneous switching is calculated. Based on this ΔV, the control unit controls the simulator body 16 in order to reflect noise caused by simultaneous switching in the logic simulation (details will be described later). When obtaining the noise influence calculation condition data from the noise influence calculation condition storage section 14, the calculation section main body directly reads the noise influence calculation condition data from the noise influence calculation condition storage section 14 or uses predetermined identification information as a key. The noise influence calculation condition data is obtained by searching the data file in the noise influence calculation condition storage unit 14 as follows.
[0041]
By the way, if simultaneous switching of the output buffer occurs, not only the potential of the ground line but also the potential of the power supply line will fluctuate. However, since the inductance of the power supply pin parasitic to the package is relatively small, Small compared to the ground line. In general, since the noise margin of the H level in the input buffer is larger than that of the L level, there is little possibility that the LSI malfunctions even if potential fluctuation occurs in the power supply line due to simultaneous switching. Therefore, in this embodiment, when calculating the influence of the simultaneous switching noise, only the wave-like fluctuation of the potential in the ground line, that is, the ground bounce is considered.
[0042]
<Operation of Embodiment>
FIG. 3 is a flowchart showing the operation of the logic simulation apparatus of this embodiment. In the logic simulation apparatus, first, in step S10, the noise influence calculation condition data is input by the noise influence calculation condition input unit 10 as described or read from the noise influence calculation condition storage unit 14. As described above, the noise influence calculation condition data includes the power supply voltage Vdd, the minimum value VIH of the H level input voltage of each input buffer, the maximum value VIL of the L level input voltage, and the like. Here, the minimum value VIH of the H level input voltage and the maximum value VIL of the L level input voltage of each input buffer in the target LSI may be directly input by the user through the noise influence calculation condition input unit 10, or noise influence calculation. It may be read from the condition storage unit 14. When reading from the noise influence calculation condition storage section 14, as shown in FIG. 4, the noise influence calculation section 12 includes a search section 12c in addition to the calculation section main body 12a and the control section 12b. Data (hereinafter referred to as “input voltage data file”) 14a in which the minimum value VIH of the H level input voltage VIH and the maximum value VIL of the L level output voltage are collected for each type of input buffer is stored in the noise influence calculation storage unit 14. The user inputs the name of the input buffer (identification information for identifying the type of input buffer) used for the target LSI by the keyboard 54 and the mouse 55, and the search unit 12c searches the input voltage data file 14a using this name as a key. Thus, the minimum value VIH and L level of the H level input voltage of each input buffer in the target LSI Better to obtain the maximum value VIL force voltage.
[0043]
In addition to the above, the noise influence calculation condition data includes the size of the ground bounce generated when one output buffer in the target LSI is switched (more precisely, the maximum value of the fluctuation amount in the wavy fluctuation of the potential of the ground line) ) ΔV1 is included. Further, instead of ΔV1, the inductance Lp of the ground pin parasitic on the package of the target LSI and the current flowing from the power supply line to the ground line through the output buffer when one output buffer in the target LSI is switched. A change amount dI / dt per unit time (hereinafter referred to as “output buffer through current change rate”) may be included in the noise influence calculation condition data. In this case, as will be described later, the ground bounce magnitude ΔV is calculated using the parasitic inductance Lp of the ground pin in the package and the output buffer through current change rate dI / dt.
[0044]
As described above, when the parasitic inductance Lp and the output buffer through current change rate dI / dt in the package are included in the noise influence calculation condition data, the user inputs the parasitic inductance Lp in the package through the noise influence calculation condition input unit 10. . Instead of this, the noise influence calculation unit 12 includes the search unit 12c as in the case of FIG. 4, and data that collects the values of the parasitic inductance Lp of each pin for each type of LSI package (hereinafter “package”). Data file ”) is stored in the noise influence calculation storage unit 14, the user inputs the name of the package used for the target LSI and the number of the ground pin using the keyboard 54 and the mouse 55, and the search unit 12c uses these packages. The parasitic inductance Lp of the ground pin in the package may be obtained by searching the package data file using the name of the device and the number of the ground pin as a key. In this case, instead of the user inputting the number of the ground pin, layout data indicating the layout design result of the target LSI and the pin arrangement data are stored in the noise influence calculation storage unit 14 in advance and are used for grounding. You should ask for the pin number. That is, the ground pin recognition unit is realized in the search unit 12c by operating the CPU 56 based on a predetermined program stored in the memory 58, and the ground pin recognition unit determines the ground pin number from the layout data and the pin arrangement data. It is good to ask automatically.
[0045]
When the parasitic inductance Lp and the output buffer through current change rate dI / dt in the package are included in the noise influence calculation condition data as described above, the user can input the output buffer through current change rate dI / dt by the noise influence calculation condition input unit 10. input. At this time, if the through current change rate dI / dt differs depending on the type of output buffer, the through current change rate dIj / dt for each output buffer may be input. Further, instead of direct input by the user, the noise influence calculation unit 12 includes the search unit 12c as in the case of FIG. 4, and data (in which the output buffer through current change rate dIj / dt is collected for each type of output buffer ( (Hereinafter referred to as “output buffer data file”) may be stored in the noise influence calculation storage unit 14. In this case, in step S16 to be described later, based on the simulation result obtained by the simulator body 16, the name of the output buffer (identification information specifying the type of the output buffer) that is simultaneously switched at each time point on the simulation is obtained, and the search unit 12c By searching the output buffer data file using this as a key, the output buffer through-current change rate dIj / dt is obtained for each of the output buffers that are simultaneously switched at each time point in the simulation.
[0046]
In order to consider the influence of the simultaneous switching noise on the output signal of the target LSI in step S18 described later, the noise influence calculation condition data includes the minimum value VOH of the H level output voltage of the output buffer and the L level output voltage. The maximum value VOL may be included. In this case, the user inputs these VOH and VOL through the noise influence calculation condition input unit 10. Instead, the noise influence calculation unit 12 includes the search unit 12c as in the case of FIG. 4, and outputs the minimum value VOH of the H level output voltage and the maximum value VOL of the L level output voltage of various output buffers. Data collected for each type of buffer (hereinafter referred to as “output voltage data file”) is stored in the noise influence calculation storage unit 14, and the name of the output buffer (output buffer) that the user uses for the target LSI with the keyboard 54 and mouse 55 is stored. And the search unit 12c searches the output voltage data file using this name as a key, whereby the minimum value VOH and L level output of the H level output voltage of each output buffer in the target LSI is output. The maximum voltage VOL may be obtained.
[0047]
In step S12, the simulator body 16 applies a test pattern at the current simulation time among the test patterns stored in the test pattern storage unit 18 to the input pins of the target LSI on the simulation.
[0048]
In step S14, based on the change of the input signal due to the application of the test pattern in step S12, the simulator body 16 simulates the logical operation of the target LSI by calculation, and the output composed of the logical value of the signal of each output pin at the present time in the simulation. Get a pattern.
[0049]
In step S16, based on the result of the simulation in step S14, it is checked whether or not each output buffer of the target LSI has been switched at the time of the simulation, and based on the result, the target LSI of the target LSI caused by the simultaneous switching of the output buffer is checked. A wave-like variation in the potential of the ground line, that is, a ground bounce magnitude ΔV is calculated. One of the following methods can be used as a specific method of calculating the magnitude of the ground bounce ΔV.
[0050]
(1) Calculation method 1
Based on the simulation results in step S14, the number N of output buffers that are simultaneously switched is obtained, and the ground bounce magnitude ΔV1 due to switching of one output buffer input in step S10 is used to calculate the ground by simultaneous switching according to the following equation. The bounce size ΔV is calculated.
ΔV = ΔV1 · N (2)
[0051]
(2) Calculation method 2
In the same manner as described above, the number N of output buffers that are simultaneously switched is obtained, and by using the parasitic inductance Lp of the ground pin and the output buffer through-current change rate dI / dt obtained in step S10, The magnitude ΔV is calculated.
ΔV = Lp · (dI / dt) · N (3)
[0052]
(3) Calculation method 3
When the through current change rate dIj / dt for each output buffer is input in step S10, based on the simulation result in step S14, the through current change rate dIj / dt of each output buffer and the parasitic inductance Lp of the ground pin Is added to the output buffer that simultaneously switches the product Lp · (dIj / dt), and this value is set as the ground bounce magnitude ΔV due to the simultaneous switching. That is, the ground bounce magnitude ΔV is calculated by the following equation.
ΔV = Lp · Σ (j = 1, N) dIj / dt (4)
here,
N: Number of output buffers that switch simultaneously
dIj / dt: Rate of change in through current of output buffer that switches simultaneously
(J = 1, 2,..., N)
Note that “Σ” is a summation symbol, and “Σ (j = a, b)” means that the summation is performed from j = a to j = b for the next term.
[0053]
(4) Calculation method 4
When there are a plurality of ground pins in the package of the target LSI, in the simulation in step S14, the current i that passes through the output buffer that is simultaneously switched becomes i on the left side of the pin of the output buffer and closest to the pin. / 2 flows, and i / 2 is considered to flow to the ground pin closest to that pin to the right of the output buffer pin. That is, it is considered that the through current of the output buffer connected to the output pin sandwiched between the two ground pins flows by half in the two ground pins. Considering this, a change amount dIg / dt per unit time of the current Ig flowing through each ground pin is calculated by simultaneous switching of the output buffer, and the parasitic inductance Lp of each ground pin obtained in step S10 is used to calculate The ground bounce magnitude ΔVg is calculated for each ground pin by the equation.
ΔVg = Lp · (dIg / dt) (5)
Then, the maximum value of ΔVg for each ground pin obtained by the above formula is set as the size of ground bounce ΔV by simultaneous switching.
[0054]
By the way, in the calculation methods 1 to 4 described above, the ground bounce magnitude ΔV is calculated as an output buffer that simultaneously switches the output buffer that switches at the same time as the current time in the simulation. The user may be able to define a finite period that can be considered. For example, in step S10, the user inputs T nanoseconds as a period corresponding to “simultaneous” with the keyboard 54 and the mouse 55, and outputs simultaneously switching a plurality of output buffers whose switching time intervals are within T nanoseconds. It may be regarded as a buffer.
[0055]
Also, not all of the output buffers that switch within the predetermined time corresponding to the same time or “simultaneous” are regarded as output buffers that switch at the same time, but only those predetermined output buffers are regarded as output buffers that switch simultaneously. May be preferred. For example, if an output buffer that hardly contributes to ground bounce is known in advance, the processing time of the logic simulation apparatus can be shortened by excluding such an output buffer from being counted as an output buffer that switches simultaneously. Can do. When there are a plurality of ground pins, only the output buffer connected to an output pin sandwiched between a certain ground pin and another ground pin is targeted for the same time or within a predetermined period corresponding to “simultaneous”. It is also possible to check the output buffer to be switched between. This is because the output buffers that cause ground bounce may be arranged such that their output pins are sandwiched between two ground pins.
[0056]
In the present embodiment, signal values that can be taken by each signal of the target LSI include an L level corresponding to a logical value “0”, an H level corresponding to a logical value “1”, an indefinite state X, and a high impedance state Z. The change of the output value of the output buffer from one of these four types to another value may be considered as output buffer switching. It is also possible to limit signal changes regarded as switching to a few of these. For example, only output signal changes of H → L, H → X, H → Z, L → H, L → X, L → Z, X → H, X → L, Z → H, Z → L are output buffers. In addition, when there is no need to strictly evaluate the influence of ground bounce, only the change of the output signal of H → L and L → H may be regarded as switching of the output buffer.
[0057]
In step S18, the output pattern composed of the signal values (logical values) of the signals of the respective output pins at the present time in the simulation is stored in the hard disk device 52 and displayed on the display device 60 as a result of the simulation in step S14. In response to the user's predetermined operation of the keyboard 54 and mouse 55, the data is output to the printer 62.
[0058]
At this time, the output pattern obtained by the simulation in step S14 may be stored, displayed, and output as it is, but it is preferable to store, display, and output an output pattern considering the influence of simultaneous switching. Therefore, in the present embodiment, prior to storing, displaying, and outputting the output pattern, the output pattern obtained by the simulation is reset using the ground bounce magnitude ΔV calculated in step S16.
[0059]
That is, in the target LSI, the potential of the ground line rises to ΔV due to simultaneous switching of the output buffer, so this ΔV is set to “L level output voltage effective value” and this ΔV is subtracted from the power supply voltage Vdd obtained in step S10. The obtained value Vdd−ΔV is set as an “H level output voltage effective value”. Then, the value of the signal output from each output buffer is checked based on the simulation result, and based on the result, the maximum value VOL of the L level output voltage and the minimum value of the H level output voltage of each output buffer obtained in step S10. Using VOH, the value of the signal output from each output buffer is reset as follows (output pattern resetting process).
[0060]
(1) The output logic value Yj of each output buffer from which an L level signal is output is obtained by using the maximum value VOL of the L level output voltage, the minimum value VOH of the H level output voltage, and the effective value of the L level output voltage. The setting is reset as follows according to the magnitude relationship with ΔV.
i) When ΔV ≦ VOL, Yj = “L” (the output logic value remains unchanged)
ii) When VOL <ΔV <VOH, Yj = “X” (changes the output logic value)
iii) When ΔV ≧ VOH, Yj = “H” (change the output logic value)
[0061]
(2) The output logic value Yj of each output buffer from which an H level signal is output is obtained by using the maximum value VOL of the L level output voltage, the minimum value VOH of the H level output voltage, and the effective value of the H level output voltage. Depending on the magnitude relationship with Vdd−ΔV, the setting is reset as follows.
i) When Vdd−ΔV ≧ VOH, Yj = “H” (the output logical value remains as it is)
ii) When VOL <Vdd−ΔV <VOH, Yj = “X” (changes the output logic value)
iii) When Vdd−ΔV ≦ VOL, Yj = “L” (changes the output logic value)
[0062]
In step S20, it is determined whether all the test patterns stored in the test pattern storage unit 18 are applied to the input pins on the simulation. If all the test patterns are applied, the logic operation simulation of the target LSI is performed. Exit.
[0063]
If all the test patterns have not been applied, the process proceeds to step S22, where the influence of the simultaneous switching noise on the test pattern to be applied at the next time on the simulation is represented by the ground bounce magnitude ΔV calculated in step S16. Use to calculate. That is, in the target LSI, since the potential of the ground line rises to ΔV by simultaneous switching of the output buffer, this ΔV is set to “L level input voltage effective value”, and this ΔV is subtracted from the power supply voltage Vdd obtained in step S10. The value Vdd−ΔV is defined as “H level input voltage effective value”. Then, based on the data stored in the test pattern storage unit 18 as a test pattern applied to the input pin at the next time on the simulation, the value of the signal input to each input buffer of the target LSI is examined, and the result Based on the maximum value VIL of the L-level input voltage and the minimum value VIH of the H-level input voltage obtained in step S10, the logical value of the signal input to each input buffer, that is, the test pattern, is as follows: Set to.
[0064]
(1) The input logic value Xj of each input buffer to which an L level signal is input is changed to the maximum value VIL of the L level input voltage, the minimum value VIH of the H level input voltage, and the effective value of the L level input voltage. The setting is reset as follows according to the magnitude relationship with ΔV.
i) When ΔV ≦ VIL, Xj = “L” (the input logical value remains as it is)
ii) When VIL <ΔV <VIH, Xj = “X” (change the input logic value)
iii) When ΔV ≧ VIH, Xj = “H” (change the input logic value)
[0065]
(2) The input logic value Xj of each input buffer to which an H level signal is input is changed to the maximum value VIL of the L level input voltage, the minimum value VIH of the H level input voltage, and the effective value of the H level input voltage. Depending on the magnitude relationship with Vdd−ΔV, the setting is reset as follows.
i) When Vdd−ΔV ≧ VIH, Xj = “H” (the input logical value remains as it is)
ii) When VIL <Vdd−ΔV <VIH, Xj = “X” (change the input logic value)
iii) When Vdd−ΔV ≦ VIL, Xj = “L” (changes the input logic value)
[0066]
In the resetting process of the input logical value Xj according to the above (1) and (2) (hereinafter referred to as “input value resetting process”), all input buffers in the target LSI may be targeted, but are affected by simultaneous switching. It is preferable to exclude an input buffer that is known in advance from being subject to input value reset processing. As a method for determining whether or not the input buffer is to be excluded from the input value reset processing target, for example, an output pin connected to the output buffer closest to the input buffer among the output buffers that are simultaneously switched, and the input buffer. If there is a ground pin between the input pin connected to the input pin, the input buffer is excluded from the target, and if there is no such ground pin, the input buffer is included in the target. Can do. In this case, layout data indicating the layout design result of the target LSI and pin arrangement data are stored in the noise influence calculation condition storage unit 14 in advance, and the input value resetting process is performed by the user operating the keyboard 54 and mouse 55. When it is instructed to limit the target, the noise influence calculation unit 12 recognizes the ground pin, the input pin, the output pin, etc. based on the layout data and the pin arrangement data, and simultaneously switches based on the recognition result. It may be determined whether or not a ground pin exists between an output pin connected to an output buffer closest to the input buffer and an input pin connected to the input buffer. In this way, by excluding a predetermined input buffer from the above-described target of resetting the input logic value, the processing time of the logic simulation apparatus can be shortened.
[0067]
In step S24, the simulation time is advanced by one test pattern. Then, it returns to step S12.
[0068]
At this time, the test pattern to be applied at the current simulation time is reset in step S22, and in step S12, the reset test pattern is applied to the input pin of the target LSI. Based on the test pattern input in this way, the processes of steps S14 to S18 described above are executed. Thereafter, in the same manner, until the application of all test patterns is completed, a loop of steps S20 → S22 → S24 → S12 →... → S18 → S20 is repeatedly executed. If it is determined that it has been applied, the simulation of the logic operation of the target LSI is terminated.
[0069]
<Effect>
As described above, in this embodiment, the test pattern applied to the target LSI is reset based on the ground bounce magnitude ΔV generated by the simultaneous switching of the output buffers (step S22). This is reflected in the simulation of the logic operation of the target LSI. As a result, an LSI that does not actually operate normally due to simultaneous switching noise can be detected in advance by a logic simulation at the design stage. Therefore, it is possible to avoid a situation in which the actually manufactured LSI does not operate normally in spite of the normal operation of the LSI in the logic simulation, and the reliability of the logic simulation is improved as compared with the prior art. As a result, LSI design efficiency is improved.
[0070]
Further, when the output pattern is reset as described above based on the ground bounce magnitude ΔV caused by the simultaneous switching of the output buffer (step S18), the simultaneous switching noise is reflected in the output pattern. Malfunctions due to noise can be detected better.
[Brief description of the drawings]
FIG. 1 is a functional block diagram showing a configuration of a logic simulation apparatus according to an embodiment of the present invention.
FIG. 2 is a diagram showing a hardware configuration of a logic simulation apparatus according to an embodiment of the present invention.
FIG. 3 is a flowchart showing the operation of the logic simulation apparatus according to the embodiment of the present invention.
FIG. 4 is a block diagram showing a configuration example of a noise influence calculation unit in the logic simulation apparatus according to an embodiment of the present invention.
FIG. 5 is a circuit diagram for explaining the influence of simultaneous switching noise of the output buffer on the operation of the LSI.
[Explanation of symbols]
10 ... Noise influence calculation condition input section
12 ... Noise effect calculator
12a ... calculation unit body
12b ... control unit
12c ... search part
14 ... Noise effect calculation condition storage section
14a ... Input voltage data file
16 ... Simulator body
18 ... Test pattern storage
20 ... Display section

Claims (19)

The operation of the semiconductor integrated circuit that inputs and outputs a digital signal is a logic circuit based on at least three types of signal values: an H level corresponding to the potential of the power supply line, an L level corresponding to the potential of the ground line, and an indefinite state X. In a logic simulation device that simulates the operation of
First input means for inputting a value of a power supply voltage Vdd supplied to the power supply line;
Second input means for inputting the minimum value VIH of the H level input voltage and the maximum value VIL of the L level input voltage of the input buffer in the integrated circuit;
Simultaneous switching detection means for detecting output buffers that switch simultaneously in the logic simulation process;
Calculation means for calculating a ground bounce magnitude ΔV, which is a wave-like variation in potential of the ground line caused by simultaneous switching of the output buffer, based on a detection result by the simultaneous switching detection means;
A value Vdd-ΔV obtained by subtracting the ground bounce magnitude ΔV from the power supply voltage Vdd is output as an H level input voltage effective value, and the ground bounce magnitude ΔV is output as an L level input voltage effective value. A value calculating means;
Input value determination means for determining whether the value of a signal input from the outside of the integrated circuit to each input buffer in the integrated circuit is H level or L level;
For the input buffer determined by the input value determination means that an H level signal is input,
i) If the effective value of the H level input voltage is equal to or greater than the minimum value VIH of the H level input voltage of the input buffer, an H level signal is input to the input buffer;
ii) If the effective value of the H level input voltage is smaller than the minimum value VIH of the H level input voltage of the input buffer and larger than the maximum value VIL of the L level input voltage of the input buffer, the signal in the indefinite state X is Suppose that it is input to the input buffer,
iii) When the effective value of the H level input voltage is equal to or less than the maximum value VIL of the L level input voltage of the input buffer, an L level signal is input to the input buffer.
First control means for continuing the logic simulation while performing the first input value resetting process,
For the input buffer determined by the input value determination means that an L level signal is input,
i) If the effective value of the L level input voltage is less than or equal to the maximum value VIL of the L level input voltage of the input buffer, an L level signal is input to the input buffer;
ii) If the effective value of the L level input voltage is smaller than the minimum value VIH of the H level input voltage of the input buffer and larger than the maximum value VIL of the L level input voltage of the input buffer, the signal in the undefined state X is Suppose that it is input to the input buffer,
iii) When the effective value of the L level input voltage is equal to or greater than the minimum value VIH of the H level input voltage of the input buffer, an H level signal is input to the input buffer.
Second control means for continuing the logic simulation while performing the second input value resetting process,
A logic simulation apparatus comprising: The logic simulation apparatus according to claim 1,
A third input means for inputting a maximum value ΔV1 of a fluctuation amount in a wave-like fluctuation of the potential of the ground line generated when one output buffer is switched in the integrated circuit;
The calculation means calculates the product of the maximum bounce amount ΔV1 input by the third input means and the product ΔV1 · N of the number N of simultaneous switching output buffers detected by the simultaneous switching detection means as the magnitude of the ground bounce. ΔV
A logic simulation apparatus characterized by that. The logic simulation apparatus according to claim 1,
A fourth input means for inputting an inductance Lp of a ground pin parasitic to the package of the integrated circuit;
A fifth input for inputting a change amount dI / dt per unit time of the current I flowing from the power supply line through the output buffer to the ground line when one output buffer in the integrated circuit is switched. Means and
The calculating means calculates the inductance Lp inputted by the fourth input means, the change amount dI / dt inputted by the fifth input means, and the number N of the simultaneous switching output buffers detected by the simultaneous switching detecting means. And the magnitude of the ground bounce ΔV is ΔV = Lp · (dI / dt) · N
Calculated by
A logic simulation apparatus characterized by that. The logic simulation apparatus according to claim 3,
Instead of the fourth input means, the first storage means for storing the inductance of each pin parasitic in the package of the integrated circuit as a package data file for each package type, and the package type of the integrated circuit The sixth input means for inputting identification information to be identified, the seventh input means for inputting pin identification information indicating the ground pin of the package of the integrated circuit, and the sixth and seventh input means. Searching for the package data file using the identified information as a key, and obtaining a ground pin inductance Lp in a specific type of package,
The calculation means calculates the ground bounce magnitude ΔV using the inductance Lp obtained by the first search means instead of the inductance Lp inputted by the fourth input means.
A logic simulation apparatus characterized by that. The logic simulation apparatus according to claim 4,
In place of the seventh input means, second storage means for storing layout data indicating the layout design result of the integrated circuit and pin arrangement data, and the integrated circuit based on the layout data and pin arrangement data. Ground pin recognition means for recognizing the ground pin of the package and outputting identification information of the ground pin;
The first search means searches the package data file using the ground pin identification information output from the ground pin recognition means as a key instead of the ground pin identification information input by the seventh input means. Obtaining the inductance Lp of the ground pin in a particular type of package,
A logic simulation apparatus characterized by that. The logic simulation apparatus according to claim 1,
A fourth input means for inputting an inductance Lp of a ground pin parasitic to the package of the integrated circuit;
When one output buffer in the integrated circuit is switched, a value dIj / dt for each output buffer of a change amount per unit time of a current flowing from the power supply line through the output buffer to the ground line is input. And an eighth input means for
The calculating means detects a product Lp · (dIj / dt) of the inductance Lp input by the fourth input means and the change amounts dIj / dt input by the eighth input means by the simultaneous switching detecting means. Based on the result, the sum of the output buffers that switch simultaneously is defined as the ground bounce magnitude ΔV.
A logic simulation apparatus characterized by that. The logic simulation apparatus according to claim 6, wherein
Instead of the eighth input means, a change amount dIj / dt per unit time of a current flowing from the power supply line through the output buffer to the ground line when one output buffer in the integrated circuit is switched. The output buffer data file is searched using the third storage means for storing the output buffer data file by output buffer type and the identification information indicating the output buffer type detected by the simultaneous switching detection means as a key. And a second search means for obtaining the respective change amounts dIj / dt of the output buffers that are simultaneously switched,
The calculating means uses the change amounts dIj / dt obtained by the second search means in place of the change amounts dIj / dt inputted by the eighth input means to calculate the magnitude of the ground bounce ΔV. calculate,
A logic simulation apparatus characterized by that. The logic simulation apparatus according to claim 6, wherein
Instead of the fourth input means, the first storage means for storing the inductance of each pin parasitic in the package of the integrated circuit as a package data file for each package type, and the package type of the integrated circuit The sixth input means for inputting identification information to be identified, the seventh input means for inputting pin identification information indicating the ground pin of the package of the integrated circuit, and the sixth and seventh input means. Searching for the package data file using the identified information as a key, and obtaining a ground pin inductance Lp in a specific type of package,
The calculation means calculates the ground bounce magnitude ΔV using the inductance Lp obtained by the first search means instead of the inductance Lp inputted by the fourth input means.
A logic simulation apparatus characterized by that. The logic simulation apparatus according to claim 8,
In place of the seventh input means, second storage means for storing layout data indicating the layout design result of the integrated circuit and pin arrangement data, and the integrated circuit based on the layout data and pin arrangement data. Ground pin recognition means for recognizing the ground pin of the package and outputting identification information of the ground pin;
The first search means searches the package data file using the ground pin identification information output from the ground pin recognition means as a key instead of the ground pin identification information input by the seventh input means. Obtaining the inductance Lp of the ground pin in a particular type of package,
Instead of the eighth input means, a change amount dIj / dt per unit time of a current flowing from the power supply line through the output buffer to the ground line when one output buffer in the integrated circuit is switched. The output buffer data file is searched using the third storage means for storing the output buffer data file by output buffer type and the identification information indicating the output buffer type detected by the simultaneous switching detection means as a key. And a second search means for obtaining the respective change amounts dIj / dt of the output buffers that are simultaneously switched,
The calculation means uses the change amounts dIj / dt simultaneously switched obtained by the second search means instead of the change amounts dIj / dt inputted by the eighth input means, and the magnitude of the ground bounce. ΔV is calculated,
A logic simulation apparatus characterized by that. The logic simulation apparatus according to claim 1,
A fourth input means for inputting an inductance Lp of a ground pin parasitic to the package of the integrated circuit;
A fifth input for inputting a change amount dI / dt per unit time of the current I flowing from the power supply line through the output buffer to the ground line when one output buffer in the integrated circuit is switched. Means,
Second storage means for storing layout data indicating the layout design result of the integrated circuit and pin arrangement data;
Ground pin recognition means for recognizing a ground pin of the package of the integrated circuit based on the layout data and pin arrangement data and outputting identification information of the ground pin;
When there are a plurality of pins recognized as ground pins by the ground pin recognizing unit, the calculating unit calculates the logic based on the change amount dI / dt inputted by the fifth input unit and the detection result by the simultaneous switching detecting unit. It is assumed that the current I passing through each output buffer that switches simultaneously in the simulation process flows in half to the left ground pin closest to the output buffer pin and the right ground pin closest to the output buffer pin. A change amount dIg / dt per unit time is calculated, and ΔVg = Lp · (dIg / dt) calculated for each ground pin using the change amount dIg / dt and the inductance Lp input by the fourth input means. The maximum value of which is the ground bounce magnitude ΔV. Logic simulation device. The logic simulation apparatus according to claim 1,
The simultaneous switching detecting means includes a ninth input means for detecting a plurality of output buffers that are switched within a predetermined time interval as output buffers that are simultaneously switched in the process of the logic simulation and inputting the predetermined time. A logic simulation apparatus characterized by that. The logic simulation apparatus according to claim 1,
In the logic simulation apparatus, the simultaneous switching detection means excludes a predetermined output buffer from detection targets in detection of output buffers that are simultaneously switched in the logic simulation process. The logic simulation apparatus according to claim 1,
Second storage means for storing layout data indicating the layout design result of the integrated circuit and pin arrangement data;
Ground pin recognition means for recognizing a ground pin of the package of the integrated circuit based on the layout data and pin arrangement data and outputting identification information of the ground pin;
The simultaneous switching detecting means is an output buffer connected to a pin sandwiched between two predetermined ground pins based on a recognition result by the ground pin recognizing means in detecting an output buffer that switches simultaneously in the logic simulation process. A logic simulation apparatus characterized in that only a detection target is used. The logic simulation apparatus according to claim 1,
A tenth input means for inputting a minimum value VOH of the H level output voltage and a maximum value VOL of the L level output voltage of the output buffer of the integrated circuit;
A value Vdd−ΔV obtained by subtracting the ground bounce magnitude ΔV from the power supply voltage Vdd is output as an H level output voltage effective value, and the ground bounce magnitude ΔV is output as an L level output voltage effective value. A value calculating means;
Output value determination means for determining whether the value of a signal output from each output buffer of the integrated circuit to the outside of the integrated circuit is H level or L level;
For the output buffer determined by the output value determining means to output an H level signal,
i) If the effective value of the H level output voltage is equal to or higher than the minimum value VOH of the H level output voltage of the output buffer, an H level signal is output from the output buffer;
ii) If the effective value of the H level output voltage is smaller than the minimum value VOH of the H level output voltage of the output buffer and larger than the maximum value VOL of the L level output voltage of the output buffer, the signal in the undefined state X is It is assumed that it is output from the output buffer,
iii) If the H level output voltage effective value is less than or equal to the maximum value VOL of the L level output voltage of the output buffer, an L level signal is output from the output buffer.
Third control means for continuing the logic simulation while performing the first output value resetting process;
For the output buffer determined by the output value determination means that the L level signal is output,
i) If the effective value of the L level output voltage is less than or equal to the maximum value VOL of the L level output voltage of the output buffer, an L level signal is output from the output buffer;
ii) If the effective value of the L level output voltage is smaller than the minimum value VOH of the H level output voltage of the output buffer and larger than the maximum value VOL of the L level output voltage of the output buffer, the signal in the undefined state X is It is assumed that it is output from the output buffer,
iii) If the L level output voltage effective value is not less than the minimum value VOH of the H level output voltage of the output buffer, an H level signal is output from the output buffer.
Fourth control means for continuing the logic simulation while performing the second output value resetting process,
A logic simulation apparatus comprising: The logic simulation apparatus according to claim 1,
Among the signal changes from one signal value included in a signal value group consisting of at least three types of signal values of H level, L level, and indefinite state X to the other signal value included in the signal value group, the simultaneous switching A logic simulation apparatus comprising: a first designating unit for designating a signal change that is recognized as switching when the detecting unit detects an output buffer that switches simultaneously. The logic simulation apparatus according to claim 1,
Second specifying means for specifying an input buffer to be subjected to first and second input value resetting processing by the first and second control means;
The first and second control means target only the input buffer designated by the second designation means for the first and second input value resetting processes.
A logic simulation apparatus characterized by that. The logic simulation apparatus according to claim 1,
Second storage means for storing layout data indicating the layout design result of the integrated circuit and pin arrangement data;
Third specifying means for specifying whether or not to limit input buffers to be subjected to first and second input value resetting processing by the first and second control means, and the first and second 2 control means, based on the layout data and the pin arrangement data, when the limitation of the input buffer to be subjected to the first and second input value resetting processing is designated by the third designation means. An input buffer having a ground pin between the output buffer pins that are the switching targets of the switching detection means and that are the closest to the output buffer pins that are simultaneously switched is selected from the targets of the first and second input value resetting processes. exclude,
A logic simulation apparatus characterized by that. The logic simulation apparatus according to claim 1,
In place of the second input means, fourth storage means for storing the minimum value VIH of the H level input voltage and the maximum value VIL of the L level input voltage of the input buffer as input voltage data files according to the type of the input buffer; Third search means for obtaining the minimum value VIH of the H level input voltage and the maximum value VIL of the L level input voltage of the desired input buffer by searching the input voltage data file using the identification information indicating the type of the input buffer as a key. And
The first control means is configured to input the H level of the input buffer obtained by the third search means based on the identification information indicating the type of the input buffer that has been determined by the input value determination means to have received the H level signal. Performing the first input value resetting process using the minimum value VIH of the voltage and the maximum value VIL of the L level input voltage;
The second control means is configured to input the H level of the input buffer obtained by the third search means based on the identification information indicating the type of the input buffer determined that the L level signal is inputted by the input value judging means. Performing the second input value resetting process using the minimum value VIH of the voltage and the maximum value VIL of the L level input voltage;
A logic simulation apparatus characterized by that. 15. The logic simulation apparatus according to claim 14, wherein, instead of the tenth input means, an output voltage data file includes a minimum value VOH of the H level output voltage and a maximum value VOL of the L level output voltage of the output buffer for each type of output buffer. As a result of searching the output voltage data file using the fifth storage means stored as a key and identification information indicating the type of the output buffer as a key, the minimum value VOH and L level output of the H level output voltage of the desired output buffer A fourth search means for obtaining a maximum voltage VOL,
The first control means outputs the H level output of the output buffer obtained by the fourth search means based on the identification information indicating the type of the output buffer determined that the output value judging means is outputting the H level signal. The first output value resetting process is performed using the minimum value VOH of the voltage and the maximum value VOL of the L level output voltage,
The second control means outputs the H level output of the output buffer obtained by the fourth search means based on the identification information indicating the type of the output buffer determined that the L level signal is output by the output value determination means. Performing the second output value resetting process using the minimum value VOH of the voltage and the maximum value VOL of the L level output voltage;
A logic simulation apparatus characterized by that.

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