JP3606757B2 - Potential level judgment circuit - Google Patents

Description

【００８０】
になる。そこで、上記式（３）においてＣ＝１，Ｖｍ＝２Ｖとして、昇圧電源の設定値ＶｐｐｓをＶｐｐｓ＝Ｖｉｉ＋２Ｖにするためには、上記式（５）において、第１の電位Ｖ１＝２Ｖ、第５の電位Ｖ５＝０、抵抗値はｒ１＝ｒ２，ｒ３＝ｒ４にすれば良い。
【００８１】
その結果、昇圧電源Ｖｐｐの電位レベルが設定値Ｖｐｐｓ＝Ｖｉｉ＋２Ｖの時に、トランジスタＭ１，Ｍ２が共に、
Ｖｇｓ＝Ｖｉｉ／２、Ｖｄｓ＝１Ｖ、Ｖｂｓ＝０Ｖ
の電気的状態になる。従って、電位レベル判定回路は、上記設定値Ｖｐｐｓの上下で判定出力ＶｏをＨレベル、Ｌレベルに切り換える。しかも、その切り替わりの動作は、動作温度や製造ばらつきの影響を受けない。
【００８２】
上記の電気的状態では、両トランジスタＭ１，Ｍ２は同じインピーダンスを有するので、接続点の電位Ｖ３は電位Ｖ１＝２Ｖとグランド電位Ｖｓｓとの中間電位である１Ｖになる。そこで、コンパレータ１１の基準電位Ｖ６も電位Ｖ１＝２Ｖとグランド電位Ｖｓｓとの中間電位に設定することで、Ｖｐｐ＝Ｖｉｉ＋２Ｖの時にＶ３＝Ｖ６になる。そして、Ｖｐｐ＞Ｖｉｉ＋２Ｖの時に、Ｖ３＞Ｖ６になり、検出出力ＶｏはＨレベル、Ｖｐｐ＜Ｖｉｉ＋２Ｖの時に、Ｖ３＜Ｖ６になり、検出出力ＶｏはＬレベルになる。
【００８３】
基準電位発生回路２３は、Ｎチャネルトランジスタ以外に、図２，３と同様にＰチャネルトランジスタや抵抗素子の抵抗分圧による構成にすることもできる。また、第１及び第２のトランジスタＭ１，Ｍ２のバックゲートを共にグランドＶｓｓまたはそれより低いバックバイアス電源ＶＢＢに接続しても良い。
【００８４】
図８は、実施の形態例における昇圧電源Ｖｐｐの電位レベル判定回路の第４の例を示す図である。この例では、入力回路２２の第１の電位Ｖ１を内部電源Ｖｉｉに、第４の電位Ｖ４を定電位発生回路２１の出力電位に、第５の電位Ｖ５をグランド電位Ｖｓｓにそれぞれ接続し、更に、トランジスタＭ１のゲートの第２の電位を、昇圧電源Ｖｐｐを抵抗分割した電位に接続する。
【００８５】
両トランジスタＭ１，Ｍ２がゲートソース間電圧Ｖｇｓとソースドレイン間電圧Ｖｄｓとを同じにして、電気的に同じ状態にすると、図７の例で示した通り、次の式になる。
【００８６】
Ｖ２＝Ｖ４＋（Ｖ１−Ｖ５）／２
そこで、Ｖ２＝ｒ２×Ｖｐｐ／（ｒ１＋ｒ２）、Ｖ１＝Ｖｉｉを代入すると、次の式が導かれる。
Ｖｐｐｓ＝Ｖｉｉ／２Ａ＋（Ｖ４−Ｖ５／２）／Ａ （６）
（但し、Ａ＝ｒ２／（ｒ１＋ｒ２））
そこで、上記式（６）が上記設定値の式（３）を満足すれば、上記説明した条件が満たされることになる。即ち、
１／２Ａ＝Ｃ
（Ｖ４−Ｖ５／２）／Ａ＝Ｖｍ
になるように、抵抗値ｒ１〜ｒ４と第４及び第５の電位Ｖ４，Ｖ５を設定すれば良い。比例係数Ｃ及び閾値より少し高い値Ｖｍは、任意の値に設定可能である。
【００８７】
その結果、電位レベル判定回路の判定レベル（設定値Ｖｐｐｓ）は、使用される内部電源Ｖｉｉに応じて図１５で示したＶｐｐの線上の値に設定されることになる。しかも、その設定値Ｖｐｐｓでの判定は、動作温度や製造プロセスのばらつきの影響を受けない。
【００８８】
上記の式（６）に抵抗値ｒ１、ｒ２、Ｖ５＝０を代入すると、
【００８９】
【数２】

【００９０】
になる。そこで、上記式（３）においてＣ＝１，Ｖｍ＝２Ｖとして、昇圧電源の設定値ＶｐｐｓをＶｐｐｓ＝Ｖｉｉ＋２Ｖにする場合ためには、上記式（７）において、第４の電位Ｖ４＝１Ｖ、第５の電位Ｖ５＝０、抵抗値はｒ１＝ｒ２にすれば良い。
【００９１】
その結果、昇圧電源Ｖｐｐの電位レベルが設定値Ｖｐｐｓ＝Ｖｉｉ＋２Ｖの時に、トランジスタＭ１，Ｍ２が共に、
Ｖｇｓ＝１Ｖ、Ｖｄｓ＝Ｖｉｉ／２、Ｖｂｓ＝０Ｖ
の電気的状態になる。従って、電位レベル判定回路は、上記設定値Ｖｐｐｓの上下で判定出力ＶｏをＨレベル、Ｌレベルに切り換える。しかも、その切り替わりの動作は、動作温度や製造ばらつきの影響を受けない。
【００９２】
上記の電気的状態では、両トランジスタＭ１，Ｍ２は同じインピーダンスを有するので、接続点の電位Ｖ３は電位Ｖ１＝Ｖｉｉとグランド電位Ｖｓｓとの中間電位であるＶｉｉ／２になる。そこで、コンパレータ１１の基準電位Ｖ６も内部電源Ｖｉｉとグランド電位Ｖｓｓとの中間電位Ｖｉｉ／２に設定することで、Ｖｐｐ＝Ｖｉｉ＋２Ｖの時にＶ３＝Ｖ６になる。そして、Ｖｐｐ＞Ｖｉｉ＋２Ｖの時に、Ｖ３＞Ｖ６になり、検出出力ＶｏはＨレベル、Ｖｐｐ＜Ｖｉｉ＋２Ｖの時に、Ｖ３＜Ｖ６になり、検出出力ＶｏはＬレベルになる。
【００９３】
基準電位発生回路２３は、ＰチャネルトランジスタＭ３，Ｍ４以外に、図１，３と同様にＮチャネルトランジスタや抵抗素子の抵抗分圧による構成にすることもできる。また、第１及び第２のトランジスタＭ１，Ｍ２のバックゲートを共にグランドＶｓｓまたはそれより低いバックバイアス電源ＶＢＢに接続しても良い。
【００９４】
以上の実施の形態例では、電位Ｖ１，Ｖ４，Ｖ５などを既存のグランド電源Ｖｓｓや内部電源Ｖｉｉに接続し、残りの電位を定電位発生回路２１が生成する定電位を利用した。しかしながら、本発明はこれらの組み合わせに限定されず、任意の電位を利用して、上記の式を満足するように抵抗値や電位を設定すれば、設定値での判定出力の切り替わりが、動作温度や製造プロセスのばらつきの影響を殆ど受けなくなる。
【００９５】
また、第２の発明の実施の形態例では、第１及び第２のトランジスタにＮチャネルトランジスタを利用して、被判定電位として昇圧電源を例にして説明した。本発明はこれに限定されず、第１及び第２のトランジスタがＰチャネルトランジスタにして、被判定電位として内部電源Ｖｉｉに依存して変化するバックゲートバイアス電源ＶＢＢに適用しても良い。その場合も、設定電位近傍の時に両トランジスタの電気的状態が同一になるように、各抵抗値や電位を設定すれば良い。
【００９６】
さらに、上記実施の形態例で電源Ｖｉｉを内部電源として説明した。しかしながら、既に述べた様に、外部から供給される電源を電源Ｖｉｉに利用する場合も、本発明は適用可能である。
【００９７】
【発明の効果】
以上、第１の本発明によれば、動作温度や製造プロセスのばらつきの影響を受けにくく、消費電流の少ない電位レベル判定回路を提供することができる。この電位レベル判定回路を利用することにより、動作温度や製造プロセスのばらつきの影響を受けにくく、消費電力の少ないＶＢＢ発生回路あるいはＶｐｐ発生回路を実現することができる。
【００９８】
更に、第２の発明によれば、昇圧電源Ｖｐｐの検出レベルを内部電源Ｖｉｉのレベルに応じて変わるＣ×Ｖｉｉ＋Ｖｍに設定することができ、しかも、その検出レベルは動作温度や製造プロセスのばらつきの影響を受けにくくすることができる。
【図面の簡単な説明】
【図１】実施の形態例におけるＶＢＢ電位レベル判定回路の第１の例を示す図である。
【図２】実施の形態例におけるＶＢＢ電位レベル判定回路の第２の例を示す図である。
【図３】実施の形態例におけるＶＢＢ電位レベル判定回路の第３の例を示す図である。
【図４】実施の形態例におけるＶＢＢ電位レベル判定回路の第４の例を示す図である。
【図５】実施の形態例における昇圧電源Ｖｐｐの電位レベル判定回路の第１の例を示す図である。
【図６】実施の形態例における昇圧電源Ｖｐｐの電位レベル判定回路の第２の例を示す図である。
【図７】実施の形態例における昇圧電源Ｖｐｐの電位レベル判定回路の第３の例を示す図である。
【図８】実施の形態例における昇圧電源Ｖｐｐの電位レベル判定回路の第４の例を示す図である。
【図９】従来のＶＢＢ電位レベル判定回路を示す図である。
【図１０】従来の他のＶＢＢ電位レベル判定回路を示す図である。
【図１１】従来の他のＶＢＢ電位レベル判定回路を示す図である。
【図１２】従来の昇圧電源Ｖｐｐの電位レベル判定回路を示す図である。
【図１３】従来の別の昇圧電源Ｖｐｐの電位レベル判定回路を示す図である。
【図１４】従来の別の昇圧電源Ｖｐｐの電位レベル判定回路を示す図である。
【図１５】図１４のＶｐｐ電位レベル判定回路における内部電源ＶＩＩと昇圧電源Ｖｐｐとの関係を示す図である。
【符号の説明】
Ｍ１ 第１のトランジスタ
Ｍ２ 第２のトランジスタ
ＶＢＢ バックゲートバイアス電源
Ｖｐｐ 昇圧電源
Ｖｉｉ 内部電源
Ｖｓｓ グランド電源
１１ コンパレータ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a potential level determination circuit that is provided in a semiconductor integrated circuit device composed of MOS transistors and determines a potential level generated by a constant potential generation circuit, and more particularly to a potential level determination circuit that is less susceptible to process variations. Furthermore, the present invention relates to a potential level determination circuit in which the constant potential can maintain an optimum potential level according to an internal power supply.
[0002]
[Prior art]
The semiconductor integrated circuit is supplied with a predetermined external power supply, and internally generates an internal power supply VII for an internal circuit, a negative power supply VBB for back gate bias, a boosted power supply VPP higher than the external power supply, and the like. For example, in the case of a dynamic random access memory (DRAM), the internal power supply VII is used in a memory core in which memory cells are formed. The boost power supply VPP is generated to write the voltage of the internal power supply VII to the capacitor of the memory cell. As the internal power supply VII, an external power supply is often used as it is. Further, the back gate bias power supply VBB is applied to the channel region of the cell transistor to prevent off leakage of the cell transistor and to prevent junction leakage from the source region to which the cell capacitor is connected to the channel region.
[0003]
The back gate bias power supply VBB needs to be maintained at a constant potential lower than the normal ground potential Vss. Similarly, the boosted power supply VPP needs to be maintained at a potential higher than the internal power supply VII by the threshold voltage of the transistor.
[0004]
The normal back gate bias power supply VBB is generated by a VBB generation circuit having a pumping circuit. In order to maintain the back gate bias power supply VBB at a set potential, a potential level determination circuit is provided that compares the potential of the generated power supply VBB with a set potential value and generates a potential determination signal according to the magnitude relationship. . The back gate bias power supply VBB generated by the VBB generation circuit is maintained at a desired potential by controlling the operation of the pumping circuit according to the determination signal of the potential level determination circuit.
[0005]
Similarly, the boosted power supply VPP is generated by a VPP generation circuit having a pumping circuit. The boosted power supply VPP generated by the VPP generation circuit is also determined by the potential level determination circuit as to whether it is lower or higher than the set potential, and the operation of the pumping circuit is controlled according to the determination signal.
[0006]
[Problems to be solved by the invention]
FIG. 9 shows a conventional VBB potential level determination circuit. The back gate bias power supply VBB generated by the VBB generation circuit 10 is supplied to the channel region of the cell transistor and also supplied to the potential level determination circuit 12. The potential level determination circuit 12 includes a comparator 11 and an inverter 13 that compare a level obtained by dividing the internal power supply VII and the back gate bias power supply VBB with resistors r10 and r20 with a predetermined reference potential Vref. The comparator 11 includes N-type transistors N1, N2, and N3 and P-type transistors P1 and P2.
[0007]
When the back gate bias power supply VBB falls from a desired set value, the determination output Vo becomes H level, a pumping circuit (not shown) in the VBB generation circuit 10 is deactivated, and the potential of the back gate bias power supply VBB is in accordance with the internal operation. Rises. On the other hand, when the back gate bias power supply VBB rises above a desired set value, the determination output Vo becomes L level, and the pumping circuit is activated to operate so as to lower the potential of the back gate bias power supply VBB.
[0008]
However, in such a circuit, current is always absorbed from the internal power supply VII to the back gate bias power supply VBB via the resistors r10 and r20. As a result, even if the back gate bias power supply VBB is not consumed on the cell transistor side, the potential level determination circuit of FIG. 9 consumes the power of the power supply VBB, and the level of the power supply VBB gradually rises and becomes unstable. Further, the VBB generation circuit 10 requires more power than is necessary, which leads to an increase in power consumption.
[0009]
FIG. 10 shows another conventional VBB potential level determination circuit. In this circuit, the internal power supply VII is resistance-divided by two P-type transistors P10 and P11, the ground potential Vss is connected to the gate of the transistor P10, and the back gate bias power supply VBB is connected to the gate of the transistor P11. The impedance of the transistor P11 changes according to the potential of the back gate bias power supply VBB, and accordingly, the voltage VB divided by resistance changes similarly to the back gate bias power supply VBB. Therefore, similarly to the potential determination circuit of FIG. 9, the comparator 11 compares the voltage VB with the reference voltage Vref, and feeds back the determination output Vo output via the inverter 13 to the VBB generation circuit 10.
[0010]
The potential determination circuit of FIG. 10 does not have the problem of current consumption as shown in FIG. 9, but the electrical characteristics such as the gate length and gate width, gate-source voltage, and drain-source voltage of the transistors P10 and P11 that perform resistance voltage division. Since the dynamic conditions are different, the characteristics of the transistors P10 and P11 vary due to the influence of process variations and operating temperature changes. Therefore, the resistance voltage dividing ratio at the set potential varies, and the potential level cannot be determined at the set potential.
[0011]
FIG. 11 shows another conventional VBB potential level determination circuit. Even in this circuit, the back gate bias power supply VBB is divided by resistors by the transistors P10 and P11 to generate the voltage VB. However, in this example, an inverter including transistors P3, P4, and N4 is used instead of the comparator so that the determination output Vo becomes H or L level according to the level of the voltage VB. Also in this example, the characteristics of the transistors P10 and P11 fluctuate due to variations in manufacturing processes, changes in operating temperature, and the like, and it is not always possible to make a potential level determination at a set potential.
[0012]
FIG. 12 shows a conventional potential level determination circuit for boosted power supply Vpp. The Vpp potential level determination circuit 16 of this example has the same configuration as the VBB potential level determination circuit of FIG. That is, the boosted power supply Vpp generated by the Vpp generation circuit 14 is resistance-divided by the resistors r40 and r50, and the divided voltage value VP is compared with the reference potential Vref by the comparator 11, and the determination output Vo is generated via the inverter 13. The determination output Vo is fed back to the Vpp generation circuit 14, and the pumping operation is activated or deactivated. The configuration of the comparator is the same as in FIGS.
[0013]
Also in this example, a current flows from the boosted power supply Vpp toward the ground potential Vss through the resistors r40 and r50 as in the case of FIG. Such a current causes useless power consumption, and lowers the potential of the boost power supply Vpp to make it unstable.
[0014]
FIG. 13 shows a potential level determination circuit of another conventional boosted power supply Vpp. The Vpp potential level determination circuit 16 in this example has a circuit configuration corresponding to the VBB potential level determination circuit of FIG. That is, N-type transistors N10 and N11 are connected in series between the internal power supply VII and the ground potential Vss, the boost power supply Vpp is applied to the gate of the transistor N10, and the internal power supply VII is applied to the gate of the transistor N11. In this case, when the boosted power supply Vpp goes up and down, the divided voltage VP also goes up and down, the level thereof is compared with the reference potential Vref by the comparator 11, and the comparison result is generated as the determination output Vo through the inverter 13. Determination output Vo is supplied to Vpp generation circuit 14 and controlled such that the pumping operation of Vpp determination circuit is activated or deactivated according to the level of determination output Vo, and the potential of boosted power supply Vpp rises or falls. The
[0015]
Also in this example, as in the case of FIG. 10, the impedance of the transistors N10 and N11 varies due to variations in operating temperature and manufacturing process, and it is not always possible to obtain a determination result at the set potential.
[0016]
FIG. 14 is a diagram showing another conventional potential level determination circuit for boosted power supply Vpp. The Vpp potential level determination circuit 16 in this example has a circuit configuration corresponding to the VBB potential level determination circuit of FIG. In this example, the potential VP divided by the transistors N10 and N11 is determined by the inverter, and the determination output Vo is supplied to the Vpp generation circuit. This example is also not preferable because the determination level varies due to variations in operating temperature and manufacturing process.
[0017]
A second problem in the conventional Vpp potential level determination circuit is that it is difficult to vary the optimal determination level corresponding to the internal power supply VII. As described above, boosted power supply Vpp is generated from an external power supply, and internal power supply VII is generated using boosted power supply Vpp. The boost power supply Vpp is
Vpp ≧ C × VII + Vm
Needs to be maintained. However, the coefficient C is about 1.0 to 1.3, and Vm is a voltage slightly higher than the threshold voltage of the cell transistor. Therefore, when the internal power supply VII is high, the boosted power supply Vpp must be maintained at a high potential accordingly. On the other hand, when the internal power supply VII is low, the boosted power supply Vpp must be maintained at a low potential accordingly. Is desirable from the viewpoint of power consumption. Recent DRAMs have diversified applications, and there are applications that require low power consumption with low power supply voltage even if the speed is low, and applications that require high speed even with high power supply voltage and high power consumption. Therefore, it is desirable that the level of the boosted power supply Vpp be the minimum level having the above relationship over a wide range of the internal power supply VII.
[0018]
In the case of the Vpp potential level determination circuit shown in FIG. 12, in addition to the increase in power consumption described above, the divided voltage level VP is a level obtained by dividing the boosted power supply Vpp by resistors r40 and r50, and the divided voltage level VP is the reference level. Since it is compared with the potential Vref, there is a problem that the determination level is fixed. That is, the set level Vpps of the boosting power source that becomes the determination level is fixed to ((r40 + r50) / r50) × Vref. For this reason, the level of the boosted power supply Vpp cannot be made to satisfy the relationship with the internal power supply VII over a wide range of the internal power supply VII. Therefore, it is necessary to match the set potential level of the boost power supply Vpp when the internal power supply VII is the highest. In this case, when the internal power supply VII is low, the generation of the unnecessarily high boost power supply Vpp is inefficient and consumed. Increases power.
[0019]
The Vpp potential level determination circuit shown in FIG. 14 is configured using an inverter, and the determination output Vo is switched when the potential of the boosted power supply Vpp is at the set potential level. In addition, since the potential VP at the connection point of the input circuit composed of the transistors N10 and N11 is proportional to the internal power supply VII, the set potential Vpps of the boost power supply can be proportional to the level of the internal power supply VII. Accordingly, the set potential level of the boost power supply can be varied. However, in the case of the circuit of FIG. 14, the proportional count is about 1.5 or more, which is too large compared to the coefficient C described above.
[0020]
FIG. 15 is a diagram showing the relationship between internal power supply VII and boosted power supply Vpp in the Vpp potential level determination circuit of FIG. It is desirable that the Vpp potential level determination circuit changes so as to satisfy the above expression corresponding to the internal power supply VII in which the set potential Vpps corresponding to the determination level is used. However, as shown in FIG. 15, since the proportionality coefficient is as large as about 1.5 in the determination circuit of FIG. 14, for example, when the internal power supply VII2 is designed to the optimum set potential Vpps, In some cases, Vpps becomes too high and the transistor is destroyed. When the internal power supply VII1 is low, the set potential Vpps becomes too low and becomes lower than the worst internal power supply VII1 and becomes inoperable. Furthermore, since the transition potential of the output of the inverter changes due to variations in manufacturing processes and variations in operating temperature, it is difficult to keep the level of the boost power supply Vpp constant.
[0021]
SUMMARY OF THE INVENTION An object of the present invention is to provide a potential level determination circuit that consumes less power and can maintain a constant determination level without depending on variations in operating temperature and manufacturing process.
[0022]
Furthermore, an object of the present invention is to determine the potential level of the back gate bias power supply VBB or the potential level of the boost power supply Vpp, which consumes less power and can keep the determination level constant without depending on the operating temperature and manufacturing process variations. It is to provide a determination circuit.
[0023]
Furthermore, an object of the present invention is to determine the potential level of the boosted power supply Vpp that can be determined by the optimum set potential of the boosted power supply Vpp in accordance with the potential level of the internal power supply VII without depending on the operating temperature and variations in the manufacturing process. It is to provide a determination circuit.
[0024]
[Means for Solving the Problems]
According to the first feature of the present invention, the potential level determination circuit connects the first transistor supplied with a predetermined constant potential to the gate and the second transistor supplied with the determination potential level to the gate. The potential at the point is compared with the reference potential by a comparator, and a determination output is generated according to the magnitude of the connection point potential and the reference potential. When the channel length and the channel width of the first and second transistors are designed to be substantially the same, and the determined potential level is in the vicinity of the set potential (determination level), at least the gate-source voltage of these transistors. And the potential of each source, drain, and gate are set so that the electrical state including the drain-source voltage is substantially the same. If maintained in such an electrical state, even if the characteristics of the first and second transistors fluctuate under the influence of operating temperature and manufacturing process variations, the connection point when the judged potential level is in the vicinity of the set potential The potential is maintained at a constant value without fluctuation. Therefore, such a potential level determination circuit generates a determination output as to whether the determination potential level is high or low with respect to a certain set potential (determination level) without being affected by variations in operating temperature and manufacturing process. Can do. When the potential level to be judged is far from the set potential, it is affected by variations in operating temperature and manufacturing process, but the comparator amplifies the difference between both potentials, so there is no problem even if the affected potential difference occurs. . As the determination potential level, for example, a back gate bias power source VBB lower than the ground or a boost power source Vpp higher than the internal power source can be applied.
[0025]
In this potential level determination circuit, the ground potential, the internal power supply potential, and a predetermined constant potential generated inside are applied to the gates, sources, and drains of the first and second transistors together with the determination target level, so that the same as described above. It can be maintained in an electrical state.
[0026]
In order to achieve the above object, according to a first aspect of the present invention, in the potential level determination circuit for determining whether the determination potential level is larger or smaller than the set determination level,
A first transistor having a predetermined constant potential supplied to the gate; a second transistor having the determined potential level supplied to the gate;
Comparing the potential of the connection point of the first and second transistors with a predetermined reference potential, and having a comparator that generates a determination output according to the magnitude thereof,
When the channel length and channel width of the first and second transistors are set to be substantially the same, and the determined potential level is in the vicinity of the set determination level, at least the gate-source voltage and the drain of those transistors The potential of each source, drain, and gate is set so that the electrical state including the source-to-source voltage is substantially the same.
[0027]
According to the above invention, the potential level determination circuit can determine whether the potential to be determined is high or low with a fixed set potential level as a boundary without being affected by variations in operating temperature and manufacturing process. it can. In addition, power consumption can be reduced.
[0028]
Further, according to the second feature of the present invention, the potential level determination circuit of the boosted power supply Vpp includes a first transistor in which the boosted power supply Vpp at the determined potential level is divided into resistors and supplied to the gate, and the internal power supply. The potential at the connection point with the second transistor, to which Vii is resistance-divided and supplied to the gate, is compared with the reference potential by the comparator, and a determination output is generated according to the magnitude of the connection point potential and the reference potential. The channel length and channel width of the first and second transistors are designed to be substantially the same, and when the boost power supply Vpp is in the vicinity of the set potential Vpps, at least the gate-source voltage and the drain-source voltage of these transistors The potential of each node and the resistance division ratio are set so that the electrical state including the voltage is substantially the same.
[0029]
Assuming that the resistance voltage dividing ratio between the boosted power supply Vpp and the internal power supply Vii is A and B, respectively, A × Vpp and B × Vii are applied to the gates of the first and second transistors. If V1 is the source of the second transistor and V5 is
Vpps = B × Vii / A + (V1−V5) / 2A
At the same time, both transistors have the same electrical state. Therefore, if B / A = C and (V1−V5) / 2A = Vm are set, the set value Vpps is always Vpps = C × Vii + Vm.
[0030]
In addition, according to the second feature of the present invention, the potential level determination circuit of another boosted power supply Vpp has a boosted power supply Vpp at a determined potential level divided by a resistor and supplied to the gate, and the power supply Vii is supplied to the drain. The potential of the connection point between the first transistor and the second transistor to which a constant potential is supplied to the gate is compared with the reference potential by a comparator, and a determination output is made according to the magnitude of the connection point potential and the reference potential. Is generated. The channel length and channel width of the first and second transistors are designed to be substantially the same, and when the boost power supply Vpp is in the vicinity of the set potential Vpps, at least the gate-source voltage and the drain-source voltage of these transistors The potential of each node and the resistance division ratio are set so that the electrical state including the voltage is substantially the same.
[0031]
Assuming that the resistance voltage division ratio of the boosted power supply Vpp is A, A × Vpp is applied to the gate of the first transistor. Therefore, if the gate of the second transistor is V4 and the source is V5,
Vpps = Vii / 2A + (V4-V5 / 2) / A
At the same time, both transistors have the same electrical state. Therefore, if 1 / 2A = C and (V4−V5 / 2) / A = Vm are set, the set value Vpps is always Vpps = C × Vii + Vm.
[0032]
In order to achieve the above object, a second invention is a potential level determination circuit for determining whether a determination potential level is larger or smaller than a set determination level.
A first transistor in which a potential obtained by dividing the determination potential level by a first resistor is supplied to a gate; a second transistor in which a predetermined potential is supplied to a gate;
Comparing the potential at the connection point of the first and second transistors with a predetermined reference potential, and having a comparator that generates a determination output according to the magnitude thereof,
When the channel length and the channel width of the first and second transistors are set to be substantially the same, and the determined potential level is in the vicinity of the determination level set according to the power source, at least the gate-source between these transistors The potential of each source, drain, and gate and the first resistance voltage dividing ratio are set so that the electrical state including the voltage and the drain-source voltage is substantially the same.
[0033]
With this configuration, the potential level determination circuit is not affected by variations in operating temperature and manufacturing process, and whether the potential to be determined is high or low at the set potential level that changes depending on the power source. Can be determined.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. However, such an embodiment does not limit the technical scope of the present invention.
[0035]
[First invention]
FIG. 1 is a diagram illustrating a first example of a VBB potential level determination circuit in the embodiment. This VBB potential level determination circuit is a circuit for determining whether the potential level of the back gate bias power supply VBB lower than the ground potential Vss is higher or lower than a set value. The configuration includes an input circuit 22 including a P-channel type first transistor M1 and a P-channel type second transistor M2 to which a back gate bias power supply VBB is supplied to the gate, and a reference potential generation for generating a reference potential V5. The circuit 23, the comparator 11 that compares the connection point potential V 3 of the input circuit 22 with the reference potential V 5, and the V 1 generation circuit 21 that generates the first potential V 1 to be supplied to the input circuit 22.
[0036]
The first transistor M1 and the second transistor M2 constituting the input circuit 22 are designed so that their channel length l and channel width w are substantially the same. The first potential V1 is supplied to the source of the first transistor M1, the ground potential Vss is supplied to the gate as the second potential V2, and the back gate is supplied to the gate of the second transistor M2 as the detected potential Vx. The bias power supply VBB is supplied with the ground potential Vss as the fourth potential V4 at the drain. The potential V3 at the connection point between the drain and source of both transistors is supplied to the comparator 11. Also, the back bias voltages of both transistors are maintained at the same potential as the source.
[0037]
The comparator 11 includes a load circuit having a current mirror configuration including P-channel transistors M5 and M6 connected to the internal power source Vii, a current source transistor M9 whose gate is supplied with the internal power source Vii, and an N source whose source is commonly connected. Channel transistors M7 and M8. Then, the node potential V3 and the reference potential V5 are supplied to the gates of the transistors M7 and M8 and compared. A determination output Vo is generated from the drain of the transistor M8.
[0038]
The reference potential generation circuit 23 resistance-divides the first potential V1 by two N-channel transistors M3 and M4 to generate a reference potential V5. These transistors M3 and M4 are also set to have the same channel length and channel width.
[0039]
The V1 generating circuit 21 is connected to the internal power source Vii, a load circuit composed of P channel transistors M11 and M12 connected to the internal power source Vii, a comparator composed of N channel transistors M13 and M14 and an N channel transistor M15 serving as a current source. The P-channel transistor M10 for feedback supplied with the inverted output of the comparator to the gate, and the feedback resistors r1 and r2. A predetermined reference voltage Vref is supplied to the gate of the transistor M13. Such a V1 generation circuit is maintained so that the connection point potential between the resistors r1 and r2 is equal to the reference potential Vref by the negative feedback function of the P-channel transistor M10. Therefore, the first potential V1 is not related to the reference potential Vref regardless of the internal power supply Vii and is not affected by the operating temperature and process variations.
V1 = Vref × (r1 + r2) / r2
Maintained at a level of. The reference potential Vref is supplied as a constant potential from the outside, for example.
[0040]
In the VBB potential level determination circuit of FIG. 1, when the back gate bias power supply VBB is in the vicinity of the set value VBBS, the determination result is obtained at a constant set determination level without being affected by variations in operating temperature and manufacturing process. Designed to switch. Therefore, specifically, the first and second transistors M1 and M2 of the input circuit are designed to have substantially the same channel length l and substantially the same channel width w. These sources, drains, and gates are supplied with potentials such that the electrical states of both transistors are substantially the same when the determined potential level VBB is close to the set value VBBS.
[0041]
When the gate-source voltage Vgs and the drain-source voltage Vds of both transistors are the same when the back gate bias power supply VBB is the set value VBBS, the following equation is satisfied.
[0042]
Vgs = V2-V1 = Vx (= VBBS) -V3
Vds = V1-V3 = V3-V4
If the connection point potential V3 is erased from both of the above equations,
V2-VBBS = (V1-V4) / 2 (1)
become. Accordingly, when the second potential V2 and the fourth potential V4 are set to the ground potential Vss (= 0V) as shown in FIG. 1, VBBS = −V1 / 2. In order to set the set value VBBS to -1V, the first potential V1 may be set to 2V.
[0043]
Therefore, in the determination circuit of FIG. 1, if V1 = 2V and V2 = V4 = 0V are set, the transition voltage at which the determination output Vo of the determination circuit is switched is a constant setting that is not affected by variations in operating temperature and manufacturing process. It is understood that it becomes a judgment level. When the potential level Vx (= VBB) = − 1V, the gate-source voltage Vgs = −2V of the transistors M1 and M2, the drain-source voltage Vds = −1V, and the back gate-source voltage Vbs. It becomes stable at = 0V, the characteristic fluctuations due to variations in operating temperature and manufacturing process become the same, and the connection potential V3 becomes 1V which is an intermediate potential between the first potential V1 and the ground potential Vss.
[0044]
Further, in the potential level determination circuit of FIG. 1, the transistors M3 and M4 are formed of the same transistor and have the same connection relationship. Therefore, the fifth potential V5 which is the reference potential is the first potential V1 and the ground potential. It is set to 1 V, which is an intermediate potential with respect to Vss.
[0045]
As a result, the detected potential level Vx is
When Vx = -1V, V3 = V5,
When Vx> −1V, V3> V5 and the determination output Vo becomes H level.
When Vx <−1V, V3 <V5 and the determination output Vo becomes L level.
[0046]
As described above, by comparing the potentials V3 and V5, the magnitude relationship between the determined potential level and the expected set value can be determined. Moreover, the boundary level of the determination is constant without being affected by variations in operating temperature and manufacturing process.
[0047]
The reference potential generation circuit 23 generates the reference potential V5 by resistance division using the N-channel transistors M3 and M4. However, the reference potential generation circuit 23 is configured by using a P-channel transistor or a normal resistor to form a resistance division circuit. Also good. Further, even in other configurations, it is only necessary to satisfy the condition of V5 = (V1 + V4) / 2.
[0048]
FIG. 2 is a diagram illustrating a second example of the VBB potential level determination circuit in the embodiment. The parts corresponding to those in FIG. The determination circuit in FIG. 2 applies the first potential V1 to the back gates of the P-channel transistors M1 and M2 of the input circuit 22, and the reference potential generation circuit 23 is configured by the P-channel transistors M3 and M4. The circuit is different.
[0049]
In the determination circuit of FIG. 2, since the same potential V1 is applied to the back bias of the first and second transistors M1 and M2, both transistors can be formed in the same N well region, and the area efficiency of the integrated circuit can be improved. Can be increased. As a result, the back gate-source voltage Vbs of both transistors is slightly different, so that it is more influenced by variations in operating temperature and manufacturing process than in the case of FIG. However, since the difference in characteristics due to the difference in the back gate-source voltage Vbs of the MOS transistor is not so great, there is little influence on practical use.
[0050]
FIG. 3 is a diagram illustrating a third example of the VBB potential level determination circuit in the embodiment. Parts corresponding to those in FIG. 1 are given the same reference numbers. The determination circuit of FIG. 3 applies the internal power source Vii to the back gates of the P-channel transistors M1 and M2 of the input circuit 22, and the reference potential generation circuit 23 is configured by resistors r3 and r4 (= r3). The circuit is different.
[0051]
In this case, since the internal power supply Vii is applied to the back gates of both the transistors M1 and M2, the same back gate potential as that of the P channel transistors M11, M12, M5 and M6 of the V1 generating circuit 21 and the comparator 11 is obtained. It can be formed in the same N well region as the transistor, and the layout efficiency can be further increased. The difference in the transistor characteristics due to the difference in the back gate-source voltage Vgs between the two transistors is not so large. Further, since the resistors r3 and r4 vary in the same way, the reference potential V5 is kept constant.
[0052]
Note that the power supply Vcc supplied from the outside may be applied to the back gates of the transistors M1 and M2 instead of the internal power supply Vii. In some cases, the internal power supply Vii is the same as the external power supply.
[0053]
FIG. 4 is a diagram illustrating a fourth example of the VBB potential level determination circuit in the embodiment. Parts corresponding to those in FIG. 1 are given the same reference numbers. The determination circuit in FIG. 4 connects the first potential V1 of the input circuit 22 to the internal power source Vii, and instead connects the second potential V2 to the potential from the second potential generation circuit 21. Different from the circuit of 1. In this case, the second potential V2 is very low, for example, about 1V. Therefore, in the second potential V2 generation circuit 21, the generation circuit, the load circuit, and the current source transistor in FIG. . That is, the N-channel transistors M11 and M12 are connected to the ground potential Vss to form a load circuit including a current mirror circuit, the P-channel transistors M13 and M14 are connected in common to the source, and a current source including the P-channel transistor M15 is connected to the load circuit. Is done. With this configuration, even when the second potential V2 is low, the potential difference between the internal potential Vii and the second potential V2 or the reference potential Vref is sufficient, so that there is no problem in the operation of the transistors M13 and M14. .
[0054]
In the example of FIG. 4, among the first potential V1, the second potential V2, and the fourth potential V4 to be set for the source, drain, and gate of the transistor of the input circuit 22, the first potential V1 is set to the internal power supply Vii. In addition, the fourth potential V4 is set to the ground potential, and the remaining second potential V2 is generated by the constant potential generation circuit 21. Then, the second potential V2 is generated by the constant potential generation circuit 21 so as to be a potential satisfying the above formula (1).
[0055]
In the example of FIG. 4, when the set value VBBS of the detected potential level Vx is −1V and the internal power supply Vii = 2.4V, in order to satisfy the above formula (1), V2 = 0.2V good. In that case, when the detected potential level Vx (back gate bias power supply VBB) is Vx = −1V, the gate-source voltage Vgs of the transistors M1, M2 = −2.2V, and the source-drain voltage Vds = −1. 2V and the back gate-source voltage Vbs = 0V are stable, and the variation in characteristics due to variations in operating temperature and manufacturing process is the same. Therefore, the determination result is inverted when the connection point potential V3 = 1.2V.
[0056]
Since the reference potential V5 is set to the intermediate potential 1.2V of the internal power source Vii, when the detected potential level Vx supplied with the back gate bias power source VBB is Vx = −1V, V3 = V5. Thus, when Vx> −1V, V3> V5 and the detection output Vo becomes H level. When Vx <−1V, V3 <V5 and the detection output Vo becomes L level. Therefore, it can be determined whether the back gate bias power supply VBB is higher or lower than the set value VBBS without being affected by temperature and process variations.
[0057]
In FIG. 4, both the back gates of the transistors M1 and M2 may be connected to the internal power source Vii. In that case, the P-channel transistors M1 and M2 can be formed in the same N-well region as the other P-channel transistors as in FIG. 3, and the layout efficiency can be increased.
[0058]
FIG. 5 is a diagram showing a first example of the potential level determination circuit of boosted power supply Vpp in the embodiment. In the potential level determination circuit of FIG. 5, in order to detect whether the boosted power supply Vpp higher than the internal power supply Vii is higher or lower than the set potential Vpps, the input circuit 22 has a configuration in which N-channel transistors are connected in series. Then, the first transistor M1 is connected to the ground potential Vss side, the second transistor M2 is connected to the predetermined fourth potential V4, and the boosted power supply Vpp is connected to the gate of the second transistor M2 as the detected potential Vx. Connected. Similarly, the reference voltage V5 generation circuit 23 includes N-channel transistors M3 and M4. The other configuration is the same as that of FIG. 1, and the same reference numerals are given to the corresponding portions. The V4 generation circuit 21 and the comparator 11 are the same as those in FIG.
[0059]
In the input circuit 22 of the potential level determination circuit of FIG. 5, the first and second transistors M1 and M2 are designed to have the same channel length and channel width. Then, the potentials V1, V2, and V4 are set so that the electrical states of the first and second transistors M1 and M2 are substantially the same when the detected potential Vx is in the vicinity of the set potential Vpps. That is, each potential is set so as to satisfy the following equation (2) as in the above equation (1).
[0060]
V2-Vpps = (V1-V4) / 2 (2)
In the example of FIG. 5, the first potential is connected to the ground potential Vss. Since the fourth potential V4 and the second potential V2 are connected to the same potential, the fourth potential V4 may be set to V4 = 2Vpps / 3 from the above equation (2). When such a condition is satisfied, when the boosted power supply Vpp is in the vicinity of the set value Vpps that is the determination level, the transistors M1 and M2 are in the same electrical state (same gate-source voltage, same source-drain voltage), Unaffected by operating temperature and manufacturing process variations.
[0061]
In the example of FIG. 5, V1 = 0V is set. Then, assuming that the set value Vpps = 3V, which is the determination level, according to the above equation (2), if V4 = V2 = 2V is set, the boosted power supply Vpp is in the vicinity of the set value Vpps. The gate-source voltage Vgs = 2.0 V, the drain-source voltage Vds = 1.0 V, and the back gate-source voltage Vbs = 0 V, which are not affected by variations in operating temperature and manufacturing process. That is, the characteristics of both transistors fluctuate in the same way even if they vary, so that the potential V3 at the connection point is kept constant.
[0062]
Also, in the circuit 23 that generates the reference potential V5, the characteristics of the transistors M3 and M4 similarly vary with respect to variations, so that the reference potential V5 is always maintained at an intermediate potential of the fourth potential V4.
[0063]
Therefore, in the example of FIG. 5, when the boosted power supply Vpp (= Vx) = 3V, V3 = V5, and when Vpp> 3V, V3> V5, the detection output Vo becomes H level, and Vpp <3V. Sometimes V3 <V5 and the detection output Vo becomes L level. Accordingly, a detection result that is higher or lower than the fixed set value can be generated in the detection output Vo.
[0064]
In the circuit of FIG. 5, the back gates of the transistors M1 and M2 may be connected to the ground potential Vss. Even in this case, similarly to the above example, it is possible to prevent the detection level from fluctuating due to the characteristic variation between the transistors M1 and M2.
[0065]
FIG. 6 is a diagram showing a second example of the potential level determination circuit for boosted power supply Vpp in the embodiment. This example corresponds to the VBB potential level determination circuit of FIG. That is, the first potential V1 of the input circuit 22 is connected to the ground power source Vss, the fourth potential V4 is connected to the internal power source Vii, and the remaining second potential V2 to be set is generated by the constant voltage generation circuit 21. Connect to the specified potential. The boosted power supply Vpp is supplied as the detected potential Vx to the gate of the second transistor M2.
[0066]
Also in the example of FIG. 6, the channel length and channel width of the first and second transistors M1 and M2 are designed to be the same, and the electrical state is expressed by the above formula (when the boosted power supply Vpp is in the vicinity of the set potential Vpps that is the determination level) 2) is set to satisfy. In the example of FIG. 6, when the set value Vpps = 3V, the first potential V1 is 0V, and the fourth potential V4 is the internal power supply Vii = 2.4V, the second potential V2 is obtained from the above equation (2). Is set to 1.8V. When such a potential is set, when the detected potential Vx = Vpps = 3V, the transistors M1 and M2 have a back gate-source voltage Vgs = 1.8V, a drain-source voltage Vds = 1.2V, It becomes the same as the gate-source voltage Vbs = 0 V, and is not affected by variations in operating temperature or manufacturing process.
[0067]
In the example of FIG. 6, V3 = V5 when the boosted power supply Vpp (= Vx) = 3V, V3> V5 when Vpp> 3V, the detection output Vo becomes H level, and Vpp <3V. Sometimes V3 <V5 and the detection output Vo becomes L level. Accordingly, a detection result that is higher or lower than the fixed set value can be generated in the detection output Vo.
[0068]
In the circuit of FIG. 6 as well, the back gates of the transistors M1 and M2 may be connected to the ground potential Vss. Even in this case, similarly to the above example, it is possible to prevent the detection level from fluctuating due to the characteristic variation between the transistors M1 and M2.
[0069]
The potential level determination circuit according to the above embodiment also determines a predetermined power supply potential lower than the ground potential other than the back gate bias power supply VBB and a power supply potential higher than the internal power supply Vii other than the boost power supply Vpp. be able to.
[0070]
[Second invention]
In the embodiment according to the first invention, the potential level determination is made as to whether the back gate bias power source VBB lower than the ground potential or the boosted power source Vpp higher than the internal power source is higher or lower than the fixed set value. The change of judgment at the set value is not affected by the variation of operating temperature and manufacturing process. On the other hand, in the embodiment according to the second invention, when the set value Vpps of the boost power source Vpp itself varies depending on the internal power source Vii, the fluctuating set value depends on the operating temperature and the manufacturing process. Avoid being affected by variations.
[0071]
Here, boosted power supply Vpp has a potential boosted by a pumping operation based on a normal external power supply. An internal power generation circuit using the boosted power supply Vpp generates an internal power supply Vii having a lower potential than the boosted power supply Vpp. In the DRAM, the internal power supply Vii applied to the cell transistor is compared to the boost power supply Vpp.
Vpp ≧ C × Vii + Vm
It is required to have the following relationship. In other words, the boosted power supply Vpp only needs to have a potential that satisfies the above equation according to the internal power supply Vii to be used. Therefore, from the viewpoint of power consumption and efficiency, the setting value for determining the boost power supply Vpp is preferably C × Vii + Vm. However, C is a constant of about 1.0 to 1.3, and Vm is a value slightly higher than the threshold voltage of the cell transistor. That is, it is preferable that the set value Vpps also varies according to the potential of the internal power supply Vii to be used. Then, it is necessary for the switching of the determination at the set value not to be affected by changes in the characteristics of the transistor due to variations in operating temperature and manufacturing process.
[0072]
FIG. 7 is a diagram showing a third example of the potential level determination circuit of boosted power supply Vpp in the embodiment. The potential level determination circuit of FIG. 7 also includes a constant voltage generation circuit 21, an input circuit 22, a reference potential generation circuit 23, and a comparator 11, as in the example of FIG. The constant voltage generation circuit 21, the reference potential generation circuit 23, and the comparator 11 have the same configuration as the example of FIG. 5, and are given the same reference numbers. In the potential level determination circuit of FIG. 7, the configuration of the input circuit 22 is different from that of FIGS.
[0073]
In the input circuit 22, N-channel transistors M1 and M2 are connected in series between a first potential V1 generated by the constant voltage generation circuit 21 and a fifth potential V5 which is a ground potential. Is supplied to the comparator 11. A potential V2 (= r2 × Vpp / (r1 + r2)) obtained by dividing the boosted power supply Vpp by the resistors r1 and r2 is applied to the gate of the first transistor M1. The potential V4 (= r4 × Vii / (r3 + r4)) obtained by dividing the internal power supply Vii by the resistors r3 and r4 is applied to the gate of the second transistor M2. When the boosted power supply Vpp is at the set potential Vpps, the first and second transistors M1 and M2 have the same electrical state, for example, the gate-source voltage and the source-drain voltage are substantially the same. The potential V1 and the resistance values r1, r2, r3, r4 are set. Moreover, the set potential Vpps is
Vpps = C × Vii + Vm (3)
It is set to satisfy.
[0074]
If the electrical states of both transistors M1, M2 are equal, the following equation is derived.
[0075]
Vgs = V2-V3 = V4-V5
Vds = V1-V3 = V3-V5
If the third potential V3 is erased from these equations,
V2 = V4 + (V1-V5) / 2
Therefore, if V2 = A × Vpps and V4 = B × Vii are substituted into this equation,
Vpps = (B / A) Vii + (V1-V5) / 2A (4)
(However, A = r2 / (r1 + r2), B = r4 / (r3 + r4)).
[0076]
Therefore, if the above equation (4) satisfies the above equation (3), the above-described condition is satisfied. That is,
B / A = C
(V1-V5) / 2A = Vm
The resistance values r1 to r4 and the first and fifth potentials may be set so that In this case, the proportional coefficient C and the value Vm slightly higher than the threshold value can be set to arbitrary values.
[0077]
As a result, the determination level (set value) Vpps of the potential level determination circuit is set to the value on the line Vpp shown in FIG. 15 according to the internal power supply Vii to be used. In addition, the determination at the set value Vpps is not affected by variations in operating temperature and manufacturing process.
[0078]
Substituting resistance values r1 to r4 and V5 = 0 into the above equation (4),
[0079]
[Expression 1]

[0080]
become. Thus, in order to set the boosted power supply setting value Vpps to Vpps = Vii + 2V by setting C = 1 and Vm = 2V in the above equation (3), the first potential V1 = 2V, the fifth potential in the above equation (5) The potential V5 = 0, and the resistance values may be r1 = r2, r3 = r4.
[0081]
As a result, when the potential level of the boost power supply Vpp is the set value Vpps = Vii + 2V, both the transistors M1 and M2 are
Vgs = Vii / 2, Vds = 1V, Vbs = 0V
It becomes the electrical state. Therefore, the potential level determination circuit switches the determination output Vo between the H level and the L level above and below the set value Vpps. In addition, the switching operation is not affected by the operating temperature or manufacturing variations.
[0082]
In the above electrical state, both transistors M1 and M2 have the same impedance, so that the potential V3 at the connection point is 1V which is an intermediate potential between the potential V1 = 2V and the ground potential Vss. Therefore, the reference potential V6 of the comparator 11 is also set to an intermediate potential between the potential V1 = 2V and the ground potential Vss, so that V3 = V6 when Vpp = Vii + 2V. When Vpp> Vii + 2V, V3> V6, and the detection output Vo becomes H level. When Vpp <Vii + 2V, V3 <V6, and the detection output Vo becomes L level.
[0083]
In addition to the N-channel transistor, the reference potential generating circuit 23 can also be configured by resistance voltage division of a P-channel transistor or a resistance element as in FIGS. Further, the back gates of the first and second transistors M1 and M2 may be connected to the ground Vss or a lower back bias power source VBB.
[0084]
FIG. 8 is a diagram showing a fourth example of the potential level determination circuit for boosted power supply Vpp in the embodiment. In this example, the first potential V1 of the input circuit 22 is connected to the internal power source Vii, the fourth potential V4 is connected to the output potential of the constant potential generating circuit 21, and the fifth potential V5 is connected to the ground potential Vss. The second potential of the gate of the transistor M1 is connected to the potential obtained by dividing the boost power supply Vpp by resistance.
[0085]
When both the transistors M1 and M2 have the same gate-source voltage Vgs and source-drain voltage Vds and are electrically in the same state, the following equation is obtained as shown in the example of FIG.
[0086]
V2 = V4 + (V1-V5) / 2
Therefore, when V2 = r2 × Vpp / (r1 + r2) and V1 = Vii are substituted, the following expression is derived.
Vpps = Vii / 2A + (V4-V5 / 2) / A (6)
(However, A = r2 / (r1 + r2))
Therefore, if the above equation (6) satisfies the above set value equation (3), the above-described condition is satisfied. That is,
1 / 2A = C
(V4-V5 / 2) / A = Vm
The resistance values r1 to r4 and the fourth and fifth potentials V4 and V5 may be set so that The proportional coefficient C and the value Vm slightly higher than the threshold value can be set to arbitrary values.
[0087]
As a result, the determination level (set value Vpps) of the potential level determination circuit is set to the value on the line Vpp shown in FIG. 15 according to the internal power supply Vii to be used. In addition, the determination at the set value Vpps is not affected by variations in operating temperature and manufacturing process.
[0088]
Substituting resistance values r1, r2, and V5 = 0 into the above equation (6),
[0089]
[Expression 2]

[0090]
become. Therefore, in order to set the boosted power supply setting value Vpps to Vpps = Vii + 2V with C = 1 and Vm = 2V in the above equation (3), the fourth potential V4 = 1V in the above equation (7), 5 potential V5 = 0 and the resistance value may be r1 = r2.
[0091]
As a result, when the potential level of the boosted power supply Vpp is the set value Vpps = Vii + 2V, both the transistors M1 and M2 are
Vgs = 1V, Vds = Vii / 2, Vbs = 0V
It becomes the electrical state. Therefore, the potential level determination circuit switches the determination output Vo between the H level and the L level above and below the set value Vpps. In addition, the switching operation is not affected by the operating temperature or manufacturing variations.
[0092]
In the above electrical state, both transistors M1 and M2 have the same impedance, so that the potential V3 at the connection point is Vii / 2, which is an intermediate potential between the potential V1 = Vii and the ground potential Vss. Therefore, the reference potential V6 of the comparator 11 is also set to an intermediate potential Vii / 2 between the internal power supply Vii and the ground potential Vss, so that V3 = V6 when Vpp = Vii + 2V. When Vpp> Vii + 2V, V3> V6, the detection output Vo is H level, and when Vpp <Vii + 2V, V3 <V6, and the detection output Vo is L level.
[0093]
In addition to the P-channel transistors M3 and M4, the reference potential generating circuit 23 can be configured by resistance voltage division of an N-channel transistor or a resistance element as in FIGS. Further, the back gates of the first and second transistors M1 and M2 may be connected to the ground Vss or a lower back bias power source VBB.
[0094]
In the above embodiment, the potentials V1, V4, V5, etc. are connected to the existing ground power supply Vss or the internal power supply Vii, and the constant potential generated by the constant potential generation circuit 21 is used for the remaining potential. However, the present invention is not limited to these combinations, and if a resistance value or a potential is set so as to satisfy the above formula using an arbitrary potential, the switching of the judgment output at the set value is performed at the operating temperature. And is hardly affected by variations in the manufacturing process.
[0095]
In the embodiment of the second invention, an N channel transistor is used as the first and second transistors, and the boosted power supply is used as the determination potential. The present invention is not limited to this, and the first and second transistors may be P-channel transistors, and may be applied to the back gate bias power supply VBB that varies depending on the internal power supply Vii as the potential to be determined. Even in this case, each resistance value and potential may be set so that the electrical state of both transistors is the same when near the set potential.
[0096]
Furthermore, the power source Vii has been described as an internal power source in the above embodiment. However, as described above, the present invention can also be applied to a case where an externally supplied power source is used as the power source Vii.
[0097]
【The invention's effect】
As described above, according to the first aspect of the present invention, it is possible to provide a potential level determination circuit that is less affected by variations in operating temperature and manufacturing process and consumes less current. By using this potential level determination circuit, it is possible to realize a VBB generation circuit or a Vpp generation circuit that is less affected by variations in operating temperature and manufacturing process and consumes less power.
[0098]
Furthermore, according to the second invention, the detection level of the boost power supply Vpp can be set to C × Vii + Vm that changes according to the level of the internal power supply Vii, and the detection level varies depending on the operating temperature and the variation in the manufacturing process. Can be less affected.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first example of a VBB potential level determination circuit in an embodiment.
FIG. 2 is a diagram illustrating a second example of the VBB potential level determination circuit in the embodiment.
FIG. 3 is a diagram illustrating a third example of the VBB potential level determination circuit in the embodiment.
FIG. 4 is a diagram showing a fourth example of the VBB potential level determination circuit in the embodiment.
FIG. 5 is a diagram showing a first example of a potential level determination circuit for boosted power supply Vpp in the embodiment.
FIG. 6 is a diagram showing a second example of the potential level determination circuit for boosted power supply Vpp in the embodiment.
FIG. 7 is a diagram showing a third example of the potential level determination circuit for boosted power supply Vpp in the embodiment.
FIG. 8 is a diagram showing a fourth example of the potential level determination circuit for boosted power supply Vpp in the embodiment.
FIG. 9 is a diagram showing a conventional VBB potential level determination circuit.
FIG. 10 is a diagram showing another conventional VBB potential level determination circuit.
FIG. 11 is a diagram showing another conventional VBB potential level determination circuit.
FIG. 12 is a diagram showing a potential level determination circuit of a conventional boosted power supply Vpp.
FIG. 13 is a diagram showing a potential level determination circuit of another conventional boosted power supply Vpp.
FIG. 14 is a diagram showing a potential level determination circuit of another conventional boosted power supply Vpp.
15 is a diagram showing the relationship between internal power supply VII and boosted power supply Vpp in the Vpp potential level determination circuit of FIG. 14;
[Explanation of symbols]
M1 first transistor
M2 second transistor
VBB Back gate bias power supply
Vpp boost power supply
Vii internal power supply
Vss ground power supply
11 Comparator

Claims (21)

In the potential level determination circuit that determines whether the determination potential level is larger or smaller than the set determination level,
A first transistor having a predetermined constant potential supplied to the gate; a second transistor having the determined potential level supplied to the gate;
Comparing the potential at the connection point of the first and second transistors with a predetermined reference potential, and having a comparator that generates a determination output according to the magnitude thereof,
When the channel length and the channel width of the first and second transistors are set to be substantially the same, and the determined potential level is in the vicinity of the set determination level, at least the gate-source voltage and the drain of those transistors A potential level determination circuit in which the potential of each source, drain, and gate is set so that the electrical state including the source-to-source voltage is substantially the same. In claim 1,
The source of the first transistor is connected to the first potential V1, the gate is connected to the second potential V2, the gate of the second transistor is connected to the determination potential, and the drain is connected to the fourth potential V4. , Connecting the drain of the first transistor and the source of the second transistor,
When the potential to be judged is in the vicinity of the set judgment level Va, the first, second and fourth potentials V1, V1 and V2 are set so that the electrical states of the first and second transistors are substantially the same. A potential level determination circuit in which V2 and V4 are set. In claim 2,
The first, second, and fourth potentials V1, V2, and V4 are set so as to satisfy the relationship V2-Va = (V1-V4) / 2 with the set determination level Va. A potential level determination circuit. In claim 2 or 3,
The potential level determination circuit, wherein the first and second transistors are P-channel MOS transistors, and the set determination level is lower than a ground potential. In claim 2 or 3,
The potential level determination circuit, wherein the first and second transistors are P-channel MOS transistors, and the determined potential is a potential of a back gate bias power source. In claim 2 or 3,
The potential level determination circuit according to claim 1, wherein the first and second transistors are N-channel MOS transistors, and the set determination level is higher than a power supply. In claim 2 or 3,
The potential level determination circuit according to claim 1, wherein the first and second transistors are N-channel MOS transistors, and the potential to be determined is a boosted power source potential higher than a power source. In claim 2 or 3,
The potential level determination circuit, wherein the back gates of the first and second transistors are connected to respective source potentials. In claim 2 or 3,
A potential level determination circuit, wherein the back gates of the first and second transistors are both connected to the source potential of the first transistor. In claim 4,
A potential level determination circuit, wherein the back gates of the first and second transistors are both connected to an internal power supply or an external power supply. In claim 6,
A potential level determination circuit, wherein the back gates of the first and second transistors are both connected to a ground power source. In claim 2,
The potential level determination circuit, wherein the predetermined reference potential is an intermediate potential between the first potential V1 and the fourth potential V4. In the potential level determination circuit that determines whether the determination potential level is larger or smaller than the set determination level,
A first transistor in which a potential obtained by dividing the determination potential level by a first resistor is supplied to a gate; a second transistor in which a predetermined potential is supplied to a gate;
Comparing the potential of the connection point of the first and second transistors with a predetermined reference potential, and having a comparator that generates a determination output according to the magnitude thereof,
When the channel length and the channel width of the first and second transistors are set to be substantially the same, and the determined potential level is in the vicinity of the determination level set according to the power source, at least the gate-source between these transistors Potential level determination characterized in that the potential of each source, drain, and gate and the first resistance voltage division ratio are set so that the electrical state including the voltage and the drain-source voltage is substantially the same. circuit. In claim 13,
The first potential V1 is supplied to the drain of the first transistor, the potential obtained by dividing the power source Vii by the second resistance is supplied to the gate of the second transistor, and the fifth potential V5 is supplied to the source. The source of the first transistor and the drain of the second transistor are connected,
The set determination level Va is set to Va = C × Vii + Vm (C and Vm are constants),
The ratios A and B of the first and fifth potentials V1 and V5 and the first and second resistance division voltages are between the set determination level Va,
Va = (B / A) Vii + (V1−V5) / 2A = C × Vii + Vm
A potential level determination circuit characterized by being set so as to hold. In claim 13,
A power source Vii is supplied to the drain of the first transistor, a predetermined fourth potential is supplied to the gate of the second transistor, a fifth potential V5 is supplied to the source, and the drain of the first transistor The source of the second transistor is connected,
The set determination level Va is set to Va = C × Vii + Vm (C and Vm are constants),
The ratio A between the fourth and fifth potentials V4 and V5 and the first resistance partial pressure is between the set determination level Va,
Va = Vii / 2A + (V4-V5 / 2) / A = C × Vii + Vm
A potential level determination circuit characterized by being set so as to hold. In claim 14 or 15,
The potential level determination circuit, wherein the first and second transistors are N-channel MOS transistors, and the set determination level is higher than a power supply. In claim 14 or 15,
The potential level determination circuit according to claim 1, wherein the first and second transistors are N-channel MOS transistors, and the potential to be determined is a boosted power source potential higher than a power source. In claim 14 or 15,
The potential level determination circuit, wherein the first and second transistors are P-channel MOS transistors, and the set determination level is lower than a ground potential. In claim 14 or 15,
The potential level determination circuit, wherein the back gates of the first and second transistors are connected to respective source potentials. In claim 14 or 15,
The back gates of the first and second transistors are both connected to a ground power source or a predetermined internal power source lower than the ground power source. In claim 14 or 15,
The potential level determination circuit, wherein the predetermined reference potential is an intermediate potential between the first potential V1 and the fifth potential V5.

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