JP3602381B2 - Cell transfer circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a cell transfer circuit in an ATM transfer system, and more particularly to a cell transfer circuit for performing a connection within a LAN via an ATM transfer system.
[0002]
[Prior art]
Since the ATM transfer system is connection-type communication, it is necessary to set up connections between communicating terminals, and the procedure is complicated. For example, assuming that the number of terminals in the same subnet is 256 and emulation of communication between terminals in the same subnet is considered, in this case, it is necessary to perform connection setting between 256 terminals in full mesh. × 255 connections are required, which is not realistic. Further, when performing packet communication between the terminals, it is necessary to reconstruct the packet at each terminal. However, in the ATM transfer system, since information is transferred in units of cells, in the worst case, assuming that a part of a cell constituting a packet arrives from all terminals facing each other at substantially the same time, if all the cells constituting the packet arrive, Since a packet cannot be reconstructed until a cell arrives and all cells must be retained, when the maximum number of cells constituting a packet is 32, the product is the product of this maximum cell number 32 and the total number of opposite terminals 255. It is necessary to provide a buffer corresponding to 8k cells, and there is a problem that mounting and processing of the terminal become heavy.
[0003]
Also, a configuration in which a packet is transmitted once from all terminals to a server or a router, terminated once in an upper layer by the server or router, reconfigured for each packet, put cells on one connection, and multicast to all terminals However, in this case, since the information must be terminated and reconfigured in the upper layer, the load on the server cannot be ignored, and the processing delay due to the limitation of the connectable terminal scale and the processing wait is ignored. become unable.
[0004]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION An object of the present invention is to provide a cell transfer circuit which requires only a small amount of terminal mounting and processing while using an ATM transfer system in view of the above situation.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, the cell transfer circuit of the present invention sets the same VP or VC for all connected terminals, and determines the cell input from each terminal by the VP or VC according to the value of the cell header. The storage that discriminates the packet to which the cell belongs, stores the cell individually for each input route connected to the terminal, and discards the cell in packet units when the number of cells exceeds the storable number of cells. Means for selecting cells constituting the same packet, successively outputting the cells from the storage means, and transferring the cells to all terminals connected by the VP or VC. Means that if no cell constituting another packet being transferred by the same VC is present and the last cell transferred by the VC is the last cell constituting the packet, the cell is stored in the storage means. Input method Cyclically, and continuously outputs from the storage means to the last cell constituting the same packet from the selected input route, and makes the cell transfer opportunity fair among routes connecting each terminal. And transferring the cell . Further, when there is no cell constituting another packet being transferred by the same VC and the last cell transferred by the VC is the last cell forming the packet, the transfer means stores the cell in the storage means. Is preferentially selected from the input routes in which the number of cells output in the past fixed time is small, and from the selected input route to the last cell constituting the same packet. , And outputs cells continuously, and transfers cells with fair cell transfer opportunities between routes connecting each terminal.
[0006]
In such a cell transfer circuit according to the present invention, the storage means identifies the VPI value, the VCI value, the PT value, or the CLP value described in the cell header of the input cell on the same route, and for each identified value. The cells may be stored individually, and the transfer unit may transfer the cells with a fair cell transfer opportunity between the sets in which the storage unit stores the packets individually. Also, in one or more routes, the value described in the cell header is identified and only a specific cell is passed, or in one or more routes, the address described in the information area of the packet is May be provided with a gateway means for identifying only the value of and passing only a specific cell. Also, a separating unit for identifying a value described in the cell header and separating a cell transferred via the storage unit from a cell directly output to a preset route without passing through the storage unit is provided. You may have. Further, the transfer unit may identify an input route input by the cell to be transferred, and transfer the cell to an output route other than an output route that outputs to a device that has input the cell to the input route. .
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0008]
[Example 1]
FIG. 1 is a diagram showing a configuration of an embodiment of a cell transfer circuit of the present invention. In this embodiment, the same VP or VC4 is set for all terminals to which the cell transfer circuit 1 is connected, and those terminals output cells to the cell transfer circuit 1 at the VP or VC4. The cell transfer circuit 1 includes a storage unit 3 for storing cells input from the input routes 5, 6, and 7 from each terminal via its VP or VC4 in packet units, and a cell unit for storing cells stored in the storage unit 3 in packet units. And a transfer means 2 for transferring the packets from the output routes 5 ', 6', 7 'to all terminals connecting the cells constituting the same packet continuously by VP or VC4.
[0009]
The cell transfer circuit 1 operates as follows. The cell input from each input path 5, 6 or 7 of VP or VC 4 is first input to the storage means 3. If no cell is currently being transferred by the transfer means and the last cell transferred is the last cell constituting the packet, the transfer means 2 controls the cells for all output routes 5 ', 6' and 7 '. Is transferred. Here, the output routes 5 ', 6', and 7 'are output routes corresponding to the input routes 5, 6, and 7, respectively. Also, in this embodiment, the identification of the packet uses the PT (payload type) value in the cell header. When the PT value is 1 or 3, it is recognized as the last cell constituting the packet, and when the PT value is any other value, it is recognized as a cell in another part constituting the packet. If there is a cell currently being transferred or the last cell transferred by the transfer unit 2 is an intermediate cell constituting a packet, the packet is transferred from the storage unit 3 after the transfer of another packet is completed.
[0010]
Further, the storage unit 3 has a packet discarding function for discarding the entire cell constituting the same packet when cells are excessively stored in the storage unit 3. By implementing this packet discarding function, it is possible to suppress the transfer of incomplete cells that cannot be reconfigured as a packet even if transferred, so that the occurrence of an invalid band can be suppressed.
[0011]
In this embodiment, since cells constituting one packet and cells constituting another packet are not inputted in a reversed manner, a cell header which is a mark for identifying a cell inputted from each input route is used. Even if the VPI (virtual path identifier) value or the VCI (virtual channel identifier) value is the same, the packet is not destroyed. Therefore, all the ATM terminals connected to the cell transfer circuit 1 need only set a single VPI value or a combination of the VPI value and the VCI value to exchange data with all the connected ATM terminals. Can be. That is, it is possible to exchange data with all terminals without specially reestablishing connections in response to an increase or decrease in the number of terminals. This indicates that the connection-type transfer system can be used in a connectionless manner as in the case of Ethernet, as in the case of using the ATM, thereby improving the convenience for the user. Moreover, in this embodiment, processing is performed at the ATM layer without terminating once in the IP layer or a layer higher than the IP layer as in a server or a router, so that the processing speed is increased.
[0012]
In the case of setting connections with all terminals, it is necessary to set connections of approximately the square of the number of terminals. According to this embodiment, however, the number of connection setting processes can be dramatically reduced. For example, when 256 terminals are connected in the same subnet as the maximum value of the total number of terminals, 65280 connections can be reduced to only one connection. In addition, since each terminal transmits a cell as a packet-by-packet, it suffices to have a packet reconstruction buffer for at most one packet. This is because, considering the case where cell-by-cell transfer is performed with all terminals and cells are received from all terminals to the middle of a packet, a buffer of (the number of terminals × the maximum value of the number of cells constituting a packet−1) is required. Therefore, the requirements for the implementation of the terminal are significantly reduced.
[0013]
This embodiment is highly adaptable to an ATM-PON system specified in, for example, ITU G983.1. In this case, the upstream direction from the ONT that virtually configures the ATM-PON to the OLT that similarly configures the ATM-PON and installs the cell transfer circuit 1 can be regarded as the input route 5, 6, or 7. , The number of input routes 5, 6 or 7 is equal to the number of ONTs. In addition, the downstream direction from the OLT to the ONT to which each terminal connects can be regarded as the output route 5 ′, 6 ′, or 7 ′. In the case of the ATM-PON, the downstream direction is a path in which a single optical signal is demultiplexed by an optical demultiplexer and virtually identified by a VP value described in the optical signal. Therefore, the downstream band of the ATM-PON system can be used more effectively than in the conventional example.
[0014]
When the cell transfer circuit 1 is incorporated into an ATM-PON system, in the direction in which cells are transferred from the ONT to which each terminal is connected in the upstream direction toward the OLT where the cell transfer circuit 1 is installed, each ONT When it is necessary to make the VPI value or the value of the combination of the VPI value and the VCI value different, it is necessary to provide a means for converting the VPI value and the VCI value in the cell transfer circuit 1. Further, the setting by the combination of the VPI value or the combination of the VPI value and the VCI value in the down direction from the OLT to each ONT via the cell transfer circuit 1 is performed based on the multicast VPI value or the VPI value and the VCI value received by the plurality of ONTs. Must be set as a combination of
[0015]
When this embodiment is used for connection between LANs configured by 10/100 BASE-T, the cells of 10/100 BASE-T are once encapsulated, and the VPI or VCI connection broadcasted by the cell transfer circuit of this embodiment is used. It is possible to communicate as the same LAN apparently without changing the settings depending on the situation of the LAN to which the connection is made by passing the ATM cell into the ATM cell.
[0016]
As described above, by using the cell transfer circuit of the present invention, by connecting the terminals in a star configuration and broadcasting cells to all routes, the full mesh connection is eliminated, and the packet is transferred in packet units. Eliminating the necessity of equipping each terminal with a packet reconstruction buffer corresponding to the number of all terminals, the processing amount becomes the same as that of exchanging data by Ethernet on the terminal side while using the ATM transfer system.
[0017]
[Example 2]
In this embodiment, the storage means 3 of the cell transfer circuit 1 stores cells individually for each input route, and the transfer means 2 cyclically switches between input routes in which the storage means 3 stores packets. Cell, or preferentially reads a path having a smaller number of cells read out in a certain time in the past between input paths storing packets. With this configuration, the opportunity for cell transfer between routes becomes fair. As a method for reading cells cyclically, for example, a round robin scan can be used.
[0018]
This embodiment is compared with a FIFO (first-in first-out) that reads data in the order of input regardless of the route. In the FIFO, if there is a large amount of data to be input from a certain input route, the data is read out in the input order, so that data transfer by another route must wait until the transfer of that route is completed. When the average value of the input data amount exceeds the average value of the output data amount, the cells are sequentially stored in the storage circuit, and the cells are eventually discarded. In the FIFO, the discard occurs regardless of the input bandwidth. Therefore, a terminal having a small input band other than a terminal connected to a route storing a large amount of data is disadvantageous. On the other hand, according to this embodiment, since the storage area is set for each input route, the data of the route having the larger input data amount is discarded in order, so that the fairness among the input routes is reduced. Property can be ensured. In this case, it is desirable to discard cells in packet units when discarding cells.
[0019]
[Example 3]
In this embodiment, the storage means 3 stores input cells from the same route in a VPI value existing in the cell header, a combination of the VPI value and the VCI value, a PT (payload type) value, a CLP (cell loss priority) value, and the like. The transfer means 2 reads the cell cyclically from each input route in which the packet is stored in the storage means 3 or stores the packet in the input path in which the packet is stored. A route with a smaller number of cells read out in a certain time in the past between routes is preferentially read out. With this configuration, the opportunity for cell transfer between routes becomes fair.
[0020]
[Example 4]
In this embodiment, as shown in FIG. 2, one or more routes are provided with gateway means 8 for identifying a value described in a cell header and determining a cell to be passed. That is, the barrier means 8 allows the cell to pass through the output route only when the values of the VPI value, the combination of the VPI value and the VCI value, the PT value, the CLP value, and the like of the cell header are within a specific value range. With this configuration, it is possible to prevent unnecessary cells from being transferred to the connection destination beyond the gateway unit 8. By setting another cell transfer circuit as a connection destination of a route having the barrier means 8, it becomes possible to transfer only cells of a specific value to the cell transfer circuit.
[0021]
[Example 5]
In this embodiment, one or more routes are provided with gateway means 8 for identifying the value of the address described in the information area of the packet and determining the cell to be connected. That is, in this embodiment, the gateway means 8 uses the address information of the source terminal instead of the cell header value. According to this configuration, it is possible to transfer a packet from a specific source to a specific output route without adding a special cell header on the terminal side.
[0022]
[Example 6]
In this embodiment, as shown in FIG. 3, a value described in the cell header is identified, and a cell transferred via the storage means 3 is connected to a predetermined route without passing through the storage means 3. Separation means 9 for separating the cells directly output is provided. That is, when the VPI value or the combination of the VPI value and the VCI value in the cell header is a preset value, the separating means 9 outputs the cell to the same route without outputting the cell to the storage means 3. Thus, when a cell constituting another packet is not outputting, the packet is output directly to the output path. With this configuration, the terminal can mix and output the communication inside the cell transfer circuit 1 and the communication outside the cell transfer circuit 1 on the same route.
[0023]
[Example 7]
In this embodiment, the transfer means 2 identifies an input route to which a cell to be transferred has been input, and transfers the cell to an output route excluding an output route corresponding to the input route. In other words, the transfer unit 2 does not transfer to the output route of the transmission source. With this configuration, the transfer band can be saved for one route.
[0024]
【The invention's effect】
As described above, according to the cell transfer circuit of the present invention, in the ATM transfer system, connection setting and buffers to be provided in the terminal can be saved irrespective of the connection status of the connection terminal.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of an embodiment of a cell transfer circuit of the present invention.
FIG. 2 is a diagram showing a configuration of another embodiment of the cell transfer circuit of the present invention.
FIG. 3 is a diagram showing a configuration of still another embodiment of the cell transfer circuit of the present invention.
[Explanation of symbols]
1 cell transfer circuit 2 transfer means 3 storage means 4 VP or VC
5, 6, 7 Input routes 5 ', 6', 7 'Output routes 8 Gateway means 9 Separation means

Claims (7)

The same VP or VC is set for all the terminals to be connected, and the cell to which the VP or VC is input from each terminal is determined based on the value of the cell header as to the packet to which the cell belongs . A storage unit that stores cells individually for each route , and discards cells in packet units when cells are input in excess of the number of cells that can be stored; and
Transfer means for selecting a cell constituting the same packet, continuously outputting the cell from the storage means, and transferring the cell to all terminals connected by the VP or VC;
When there is no cell constituting another packet being transferred on the same VC and the last cell transferred on the VC is the last cell forming a packet, the transfer means stores the cell in the storage means. The stored input route is cyclically selected, the output is continuously output from the storage means to the last cell constituting the same packet from the selected input route, and between the routes connecting each terminal. A cell transfer circuit for transferring cells with fair cell transfer opportunities . The same VP or VC is set for all the terminals to be connected, and the cell to which the VP or VC is input from each terminal is determined based on the value of the cell header as to the packet to which the cell belongs. A storage unit that stores cells individually for each route, and discards cells in packet units when cells are input in excess of the number of cells that can be stored; and
Transfer means for selecting a cell constituting the same packet, continuously outputting the cell from the storage means, and transferring the cell to all terminals connected by the VP or VC;
When there is no cell constituting another packet being transferred on the same VC and the last cell transferred on the VC is the last cell forming a packet, the transfer means stores the cell in the storage means. From the stored input routes, an input route having a smaller number of cells output in a certain time in the past is preferentially selected, and from the selected input route to the last cell constituting the same packet from the storage means. A cell transfer circuit which continuously outputs cells and transfers cells with fair cell transfer opportunities between routes connecting each terminal . The storage means identifies a VPI value, a VCI value, a PT value, or a CLP value described in a cell header of an input cell on the same route, and individually accumulates each of the identified values. 3. The cell transfer circuit according to claim 1 , wherein a cell transfer opportunity is equalized between sets in which packets are individually stored by the storage means, and cells are transferred. The same VP or VC is set for all the connected terminals, and the cells input by the VP or VC from each terminal are stored by determining the packet to which the cell belongs based on the value of the cell header, and the number of cells that can be stored. Storage means for discarding cells in packet units when cells are input beyond
When a cell constituting another packet is not output by the same VC, a cell constituting the same packet from the cells stored in the storage means by the VP or VC is transmitted to all connected terminals. And transfer means for continuously outputting and transferring the selected data, and gateway means for identifying a value described in a cell header and passing only a specific cell in one or a plurality of routes. A cell transfer circuit, characterized in that: In place of the gateway means according to claim 4, gateway means for identifying an address value described in an information area of a packet and passing only a specific cell is provided in one or a plurality of routes. The cell transfer circuit according to claim 4 , wherein: The same VP or VC is set for all the connected terminals, and the cells input by the VP or VC from each terminal are stored by determining the packet to which the cell belongs based on the value of the cell header, and the number of cells that can be stored. Storage means for discarding cells in packet units when cells are input beyond
When cells of the other packets in the same VC is not output, for all terminals to be connected, said at VP or VC, cells constituting the same packet from cells stored in said storage means Transfer means for selecting and continuously outputting and transferring, and identifying a value described in a cell header , and a cell transferred via the storage means and a cell transferred without passing through the storage means. 2. The cell transfer circuit according to claim 1, further comprising a separation unit that separates cells directly output to a preset route. The transfer unit further identifies an input route input by a cell to be transferred , and transfers the cell to an output route excluding an output route that is output to a device that has input the cell to the input route. The cell transfer circuit according to claim 1 .

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