JP3600562B2 - Semiconductor storage device - Google Patents

Description

【００３８】
（第３の実施形態）
図３は本発明の第３の実施例に係わる半導体記憶装置を示すブロック図で、図４は同装置におけるレイアウト図である。前記図２７と比較して分かるように本実施例は、メモリセルアレイ６とデータ回路８との間に誤り訂正回路１１を設けるのではなく、データ入出力バッファ１２の１つ毎に誤り訂正検出回路１１を設けている。誤り訂正検出回路１１は、入力された書き替えデータから誤りの訂正又は検出を行うための検査データを発生し、かつ読み出しデータを出力する際に読み出しデータと検査データから読み出しデータの誤りの訂正又は検出を行うものである。
【００３９】
本実施例では、２０４８ビット構成の情報データは、８個のデータ入出力パッドを通じて並列に入出力される。即ち、各データ入出力パッド当り２５６ビットの情報データが入出力される。ここで、情報データ２５６ビット中の１ビット誤りを訂正し、偶数ビット誤りを検出する拡大ハミング符号（２６６、２５６）が用いられる。
【００４０】
図５〜図７は、本実施例における符号化・復号化回路を表し、図８、図９は、それぞれ書き込み時、読み出し時の制御信号のタイミングを表す。
【００４１】
初めに、書き込み時の説明をする。
【００４２】
信号ＤＩＮがハイの間データ入出力パッドから書き込み情報データＤＩＮｉに（ｉ＝１、…、８）が入力され、図５（ａ）（ｂ）の符号化回路に入力される。このとき、信号ＤＩＮＯＵＴＢはローとされ、ＤＩＮＳｉ＝ＤＩＮｉがデータ回路８に送られる。同時に、信号ＳＬＩＮＢはロー、信号ＤＩＶはハイとされているため、書き込み情報データＤＩＮｉはシフトレジスタＳＬ１とシフトレジスタ列ＳＬ２、…、１０に入力され、検査ビット生成のための計算が実行される。シフトレジスタのクロックは、入力データＤＩＮｉのクロックと同期される。信号ＳＬＯＵＴ１Ｂ、ＳＬＯＵＴ２Ｂはハイとされているので、シフトレジスタＳＬ１〜１０の出力はＤＩＮＳｉに出力されない。
【００４３】
書き込み情報データＤＩＮｉの入力が終了すると、信号ＤＩＮＯＵＴＢはハイ、信号ＤＩＶはロー、信号ＳＬＩＮＢはハイ、信号ＳＬＯＵＴ１Ｂはローに変わり、シフトレジスタＳＬ１のクロックはストップする。このとき、シフトレジスタ列ＳＬ２、…、１０の状態は９個の検査ビットを表し、入力はローに固定されることによって、ＣＩＮＳｉに出力される。その後、信号ＳＬＯＵＴ１Ｂはハイ、信号ＳＬＯＵＴ２Ｂはローにされ、１個の検査ビットであるシフトレジスタＳＬ１の状態がＤＩＮＳｉに出力される。信号ＤＩＮＳがローになり、信号ＳＬＯＵＴ２Ｂがハイになるとデータ回路８への入力が終了する。
【００４４】
このようにして、データ回路８に入力される書き込みデータは２５６ビット情報データと１０ビット検査データとなる。
【００４５】
その後、書き込みデータ２０４８ビット（＝２５６ビット×８組）は、信号ＰＲＧがハイの間にメモリセルに書き込まれる。
【００４６】
さらにその後、信号ＢＥＲＥＡＤがハイの間にバースト誤りがあったか否かの検出を行う。信号ＢＥＲＥＡＤがハイになると、書き込んだデータをＤＩＮＳｉに出力された順番にＤＩＮｉに読み出す。このとき、信号ＤＩＶはハイ、信号ＳＬＩＮＢはローとされ、シフトレジスタＳＬ１とシフトレジスタ列ＳＬ２、…、１０に入力され、シンドロームを計算する。
【００４７】
読み出しデータに誤りがある場合、シフトレジスタの状態Ｌ１ｉ〜Ｌ１０ｉのうち一つ以上がハイとなる。従って、シンドローム計算が終了した後に信号ＤＥＴＥがハイになると信号ＥＲＤＥＴｉがハイとなる。そして、全てのｉに対して信号ＥＲＤＥＴｉがハイとなった場合に、バースト誤りが発生したことを信号ＢＳＴＥＲＲが伝える。
【００４８】
一般に、誤り訂正検出回路の入力データは、書き込み入力データとその反転データのいずれでも可能であるが、ここではバースト誤りが発生したときにそのデータが符号語とならないようなデータとしている。即ち、バースト誤りが発生したときにそのデータの“１”が全て“０”になり、全“０”となってしまうと、この全“０”データは誤りがないと判定されてしまうためバースト誤りを知ることはできない。しかしながら、バースト誤りが発生したときにそのデータの“０”が全て“１”になり、全“１”となるようにしておけば誤りが検出されるためバースト誤りを知ることが可能となる。
【００４９】
次に、読み出し時の説明をする。
【００５０】
読み出しは２サイクル、即ちシンドロームの計算を行う第１サイクル（信号ＥＣＣＲＥＡＤがハイである期間）と誤り訂正をしながら誤りが訂正された正しいデータを外部に出力するための第２のサイクル（信号ＤＡＴＡＯＵＴがハイである期間）とから構成される。第１サイクルでは信号ＤＩＶがハイ、信号ＳＬＩＮＢはローとなり、読み出されたデータはＤＩＮｉに出力され、シフトレジスタ列に入力される。全データが入力され終わると、誤り検出のための信号ＤＥＴＥがハイにされる。このとき、誤りがあった場合にはシフトレジスタの状態は少なくとも一つはハイになるため、誤りが検出されたことを知らせる信号ＥＲＤＥＴｉがハイとなる。このとき、さらに偶数個の誤りがあった場合には、それを知らせる信号２ＥＲＤＥＴｉがハイになる。これで第１のサイクルは終了する。
【００５１】
続いて、第２サイクルでは信号ＣＯＲＥがハイとなり、誤り訂正をしながら誤りが訂正された正しいデータを外部に出力していく。データはあるクロックに同期して出力されていくが、それと同時に入力を出力に等しくされたシフトレジスタ列の状態は、信号ＳＬＩＮＢをハイとしたままそのクロックに同期してシフトしていく。誤りの訂正は、シフトレジスタ列がある特定の状態になるときに出力されるデータを反転することによって行われる。誤りの訂正が行われたとき、信号ＣＯＲＲＥＣＴｉはハイとなる。しかし、もし誤りが検出されたことを知らせる信号ＥＲＤＥＴｉがハイとなったにも拘らず、信号ＣＯＲＲＥＣＴｉがローのままである、即ち誤りの訂正が行われなかった場合には、信号ＮＯＴＣＯＲｉがハイになる。
【００５２】
このようにして、各データ入出力バッファ毎に誤り訂正検出回路を設け、復号すべき入力データを２サイクル繰り返し読み出す方法によって、従来に比べ遅延時間なしに復号を行うことができ、遅延回路を省略できる。従って、特に長い符号長の場合に誤り訂正回路の回路規模を縮小できる。
【００５３】
さらに、本実施例の場合、図３や図４に示されるように誤り訂正回路１１は、メモリセルアレイ６とデータ回路８の間に配置する必要がないため、周辺部、即ち各データ入出力バッファ１２の付近に配置することができ、レイアウト上の柔軟度を増すことが可能となる。
【００５４】
（第４の実施形態）
図１０は本発明の第４の実施例に係わる半導体記憶装置を示すブロック図で、図１１は同装置におけるレイアウト図である。本実施例が先に説明した第３の実施例と異なる点は、データ入出力バッファ１２の複数個（２つ）毎に誤り訂正検出回路１１を設けたことである。
【００５５】
本実施例では、２０４８ビット構成の情報データは、８個のデータ入出力ピンＩＯｉ（ｉ＝１、…、８）を通じて並列に入出力される、即ち、各データ入出力ピン当り２５６ビットの情報データが入出力される。レイアウト上、データ入出力ピンはチップの左端に４個（ＩＯ１〜４）、右端に４個（ＩＯ５〜８）、それぞれ配置されているものとする。ここで、８個のデータ入出力ピンを２組（ＩＯ１〜４、ＩＯ５〜８）に分ける。各組の各データは、あるクロックに同期して並列に入出力されるが、第１クロックで入出力される４ビットと第２クロックで入出力される４ビットで１バイト（＝８ビット）を構成し、以下同様に奇数番目のクロックで入出力される４ビットと偶数番目のクロックで入出力される４ビットで１バイトを構成していく（図１９（ａ）（ｂ））。
【００５６】
このようにして、各組は、１２８バイト＝１０２４ビットの情報データで構成される。本実施例で用いられる誤り訂正符号は、１２８バイト中の１バイト誤り訂正する、リードソロモン符号（１３０、１２８）である。
【００５７】
図１２〜図２０に本実施例に用いた誤り訂正回路の具体的な回路構成を示し、図２１，図２２にはそれぞれ書き込み、読み出し時の制御信号のタイミング図を示す。
【００５８】
初めに、書き込み時の説明をする。
【００５９】
信号ＤＩＮがハイの間データ入出力ピンから書き込み情報データＤＩＮｍ−ｉ（ｍ＝１、２、ｉ＝１、…、８）が入力され、図１２（ａ）〜（ｃ）の符号化回路に入力される。このとき、信号ＤＩＮＯＵＴＢはローとされ、ＤＩＮＳｍ−ｉ＝ＤＩＮｍ−ｉがデータ回路８に送られる。同時に、信号ＤＩＶはハイとされているため、書き込み情報データＤＩＮｍ−ｉは８ビットシフトレジスタＳＬ１に入力され、検査ビット生成のための計算が実行される。シフトレジスタのクロックは、入力データＤＩＮｍ−ｉのクロックと同期される。信号ＳＬＯＵＴＢはハイとされているので、８ビットシフトレジスタＳＬ２の出力ＳＬＯＵＴｍ−ｉはＤＩＮＳｍ−ｉに出力されない。
【００６０】
書き込み情報データＤＩＮｍ−ｉの入力が終了すると、信号ＤＩＮＯＵＴＢはハイ、信号ＤＩＶはロー、信号ＳＬＯＵＴＢはローに変わり、入力ＳＬＩＮｍ−ｉがローに固定されることによって、８ビットシフトレジスタＳＬ１，２の状態がＤＩＮＳｍ−ｉに出力される。その後、信号ＤＩＮＳがロー、信号ＳＬＯＵＴＢがハイになると書き込みデータの入力が終了する。
【００６１】
このようにして、データ回路８に入力される書き込みデータは、１２８バイト情報データと２バイト検査データとで構成される２つの符号語となる。
【００６２】
その後、この書き込みデータは、信号ＰＲＧがハイの間にメモリセルに書き込まれる。
【００６３】
さらにその後、信号ＢＥＲＥＡＤがハイの間にバースト誤りがあったか否かの検出を行う。信号ＢＥＲＥＡＤがハイになると、書き込んだデータをＤＩＮＳｍ−ｉに出力された順番にＤＯＵＴｍ−ｉに読み出す。このとき、信号ＣＣＲＢはローとされ、シフトレジスタＳＬ３，４に入力され、シンドロームを計算する。読み出しデータに誤りがある場合、Ｓ０ ｍ−ｉのうち一つ以上がハイとなる。従って、シンドローム計算が終了した後に信号ＤＥＴＥがハイになると信号ＥＲＤＥＴｍＢがハイとなる。そして、ｍ＝１、２に対して信号ＥＲＤＥＴｍＢがともにローとなった場合に、バースト誤りが発生したことを信号ＢＳＴＥＲＲが伝える。
【００６４】
一般に、誤り訂正検出回路の入力データは、書き込み入力データとその反転データのいずれでも可能であるが、ここではバースト誤りが発生したときにそのデータが符号語とならないようなデータとしている。即ち、バースト誤りが発生したときにそのデータの“１”が全て“０”になり、前記“０”となってしまうと、この全“０”データは誤りがないと判定されてしまうためバースト誤りを知ることはできない。しかしながら、バースト誤りが発生したときにそのデータの“０”が全て“１”になり、全“１”となるようにしておけば誤りが検出されるためバースト誤りを知ることが可能となる。
【００６５】
次に、読み出し時の説明をする。
【００６６】
読み出しは２サイクル、即ち、シンドロームの計算を行う第１サイクル（信号ＥＣＣＲＥＡＤがハイである期間）と誤り訂正をしながら誤りが訂正された正しいデータを外部に出力するための第２のサイクル（信号ＤＡＴＡＯＵＴがハイである期間）とから構成される。第１サイクルでは信号ＥＣＣＲＢがローとなり、読み出されたデータはＤＯＵＴｍ−ｉに出力され、８ビットシフトレジスタＳＬ３，４，８，９に入力される。全データが入力され終わると、誤り検出のための信号ＤＥＴＥがハイにされる。このとき、誤りがあった場合にはシフトレジスタの状態は少なくとも一つはハイになるため、誤りが検出されたことを知らせる信号ＥＲＤＥＴｍＢがローとなる。これで第１のサイクルは終了する。
【００６７】
続いて、第２サイクルでは信号ＯＵＴＥＢがローとなり、誤り訂正をしながら誤りが訂正された正しいデータを外部に出力していく。データはあるクロックに同期して出力されていくが、それと同時に入力がローである８ビットシフトレシスタＳＬ５，１０の出力はそのクロックに同期してシフトし、フィードバックしていく。誤りの訂正は、８ビットシフトレジスタＳＬ５，１０の出力がシンドロームＳｍ−ｉと一致するときに出力されるデータを反転することによって行われる。誤りの訂正が行われたとき、信号ＣＯＲＲＥＣＴｉはハイとなる。しかし、もし、誤りが検出されたことを知らせる信号ＥＲＤＥＴｉがハイとなったにもかかわらず、信号ＣＯＲＲＥＣＴｉがローのままである、即ち誤りの訂正が行われなかった場合には、信号ＮＯＴＣＯＲｉがハイになる。
【００６８】
このようにして、データ入出力バッファの組毎に誤り訂正検出回路を設け、復号すべき入力データを２サイクル繰り返し読み出す方法によって、従来に比べ遅延時間なしに復号を行うことができ、遅延回路を省略できる。従って、特に長符号長の場合に誤り訂正回路の回路規模を縮小できる。
【００６９】
また、バイト当りのビット数を４ビットから８ビットに拡張することによって、最大符号長を拡大できる。
【００７０】
さらに、本実施例の場合、図４や図５に示されるように誤り訂正回路１１は、メモリセルアレイ６とデータ回路８の間に配置する必要がないため、周辺部、即ち各データ入出力バッファ１２の付近に配置することができ、レイアウト上の柔軟度を増すことが可能となる。
【００７１】
なお、本発明は上述した各実施例に限定されるものではなく、その要旨を逸脱しない範囲で、種々変形して実施することができる。
【００７２】
【発明の効果】
以上詳述したように本発明によれば、各データ（入）出力バッファ毎又は複数のデータ（入）出力バッファ毎に、誤り訂正回路をデータ（入）出力バッファ付近に設けることによって、レイアウトの自由度を増すことができる。さらに、バースト誤りが検出できる位置で符号化復号化を行うことにより、データ書き替え時のバースト誤り発生を検出できる。
【００７３】
また、１バイト誤り検出符号において、１バイトを構成するビット数を並列に入出力される単位から複数単位とすることによって、符号長を大きくすることが可能となる。さらに、同一データを２回入力することによって、誤り訂正回路の回路規模に占める割合の大きい遅延回路を省略することができるため、誤り訂正回路の回路規模を極めて小さくできるだけでなく、従来に比べ遅延なしに誤り訂正検出のための復号が行える。
【図面の簡単な説明】
【図１】第１の実施例に係わる多項式方式の誤り訂正検出回路を示すブロック図。
【図２】第２の実施例に係わる多項式方式の誤り訂正検出回路を示すブロック図。
【図３】第３の実施例に係わる半導体記憶装置を示すブロック図。
【図４】第３の実施例におけるメモリセルアレイと各回路及び入出力パッド等のレイアウト図。
【図５】第３の実施例装置における符号化・復号化回路を示す図。
【図６】第３の実施例装置における符号化・復号化回路を示す図。
【図７】第３の実施例装置における符号化・復号化回路を示す図。
【図８】第３の実施例装置における書き込み時、読み出し時の制御信号のタイミングを示す図。
【図９】第３の実施例装置における書き込み時、読み出し時の制御信号のタイミングを示す図。
【図１０】第４の実施例に係わる半導体記憶装置を示すブロック図。
【図１１】第４の実施例におけるメモリセルアレイと各回路及び入出力パッド等のレイアウト図。
【図１２】誤り訂正回路の具体的な回路構成を示す図。
【図１３】誤り訂正回路の具体的な回路構成を示す図。
【図１４】誤り訂正回路の具体的な回路構成を示す図。
【図１５】誤り訂正回路の具体的な回路構成を示す図。
【図１６】誤り訂正回路の具体的な回路構成を示す図。
【図１７】誤り訂正回路の具体的な回路構成を示す図。
【図１８】誤り訂正回路の具体的な回路構成を示す図。
【図１９】誤り訂正回路の具体的な回路構成を示す図。
【図２０】誤り訂正回路の具体的な回路構成を示す図。
【図２１】誤り訂正回路の具体的な回路構成を示す図。
【図２２】誤り訂正回路の具体的な回路構成を示す図。
【図２３】行列方式と多項式方式における１ビット誤り訂正符号の構成例を示す図。
【図２４】第１の従来例に係わる誤り訂正検出回路を示すブロック図。
【図２５】第２の従来例に係わる誤り訂正検出回路を示すブロック図。
【図２６】第２の従来例において、複数の単一バイト誤り訂正回路を設けた例を示す図。
【図２７】第３の従来例に係わる誤り訂正検出回路を備えた半導体記憶装置を示すブロック図。
【図２８】第３の従来例におけるメモリセルアレイと各回路及び入出力パッド等のレイアウトを示す図。
【符号の説明】
１…シンドローム計算回路
２…誤り位置大きさ計算回路
３…誤り訂正回路
４…遅延回路
５…書き込み・読み出し制御回路
６…メモリセルアレイ
７…ロウデコーダ
８…データ回路
９…カラムデコーダ
１０…アドレスバッファ
１１…誤り訂正検出回路
１２…データ入出力バッファ
１３…半導体記憶装置
１４…単一バイト誤り訂正回路
１５…符号長拡大回路
１６…単一ｍｂビット／バイト誤り訂正回路
１００…データ入出力パッド
１０１…ＩＯ線[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device using an error correction detection circuit that detects and corrects a bit error in bit data.
[0002]
[Prior art]
Conventionally, as a method of error correction detection, a matrix method (IEEE Journal of Solid-State Circuit, vol. 24, pp50, 1989) and a polynomial method (Error-Correcting Codes by Peterson and Weldon, two of which are known in the art) are known. Have been. FIG. 23 shows a configuration example of a 1-bit error correction code for data having a depth of 512 bits × a width of 8 bits in both cases.
[0003]
In the conventional semiconductor memory device, since the error correction processing time is given the highest priority, the occurrence of an error check bit in data writing at the time of data input / output and the error-correction at the time of data reading using a matrix method with less time loss ( a) has been used. At this time, four redundant check bits are required for the 8-bit data, that is, the memory area is increased by 50%. On the other hand, in the case of the polynomial system (b), the check bits may be 10 bits for 512-bit data, and the redundancy is about 2%. However, it takes a 522-bit delay time to correct the error.
[0004]
The reliability of the memory when no error correction code is added is worse than required, and the reliability of the memory when adding a code for correcting a 1-bit error in 512-bit data is better than required. If the rate of increase in the memory area is given priority over the processing time for error correction, the polynomial method is more appropriate than the matrix method. However, on the contrary, the size of the error correction circuit may be larger in the polynomial system than in the matrix system. This is because, in the case of the polynomial system, the error correction circuit mainly includes a delay circuit composed of a shift register (522 bits × 8 sets in the above example) equal to the data depth including the test data section, and a check bit. It is composed of a syndrome calculation circuit consisting of shift registers equal to the number (10 bits × 8 pairs in the above example), while the matrix method is composed of only four sets of 5-input exclusive ORs and logics of these outputs. Because it is done.
[0005]
As can be seen from the above, although the polynomial system can greatly reduce the increase rate of the memory area as compared with the matrix system, the effect of suppressing the increase rate of the memory chips is small because the size of the error correction circuit is conversely large.
[0006]
Further, in the matrix system, since it is necessary to perform 8-bit parallel processing, the error correction circuit must be arranged between the memory cell and the bit line control circuit or in a place where all the IO lines are gathered. The degree of freedom was small.
[0007]
Hereinafter, the configuration and problems of the conventional error correction detection circuit will be specifically described.
[0008]
(Conventional example 1)
FIG. 24 is a block diagram showing an error correction detection circuit according to the first conventional example. Represents This is disclosed in the above-mentioned document (Error-Correcting Codes. Second Edition by Peterson and Weidon).
[0009]
The input data is input to a syndrome calculation circuit (check bit generation circuit) 1 and a delay circuit 4. If there is no error in the input data, the syndrome has a value of zero, and if there is an error, the syndrome has a non-zero value. The value is input to an error position size calculation circuit 2 which calculates the position and size of the error.
[0010]
When the input syndrome is zero, the error position size calculation circuit 2 outputs zero, and the data input to the delay circuit 4 is output as it is through the error correction circuit 3 without being changed. When the syndrome has a certain non-zero value, the position and size of the error are calculated by the error position size calculation circuit 2, and the data input to the delay circuit 4 is corrected by the error correction circuit 3. Output. That is, error correction is performed by the error correction circuit 3 only when erroneous data is output, and correct data is output.
[0011]
However, this type of configuration has the following problems. That is, the delay circuit 4 is composed of a shift register having the same length as the input data, and particularly in the case of a long code length, the ratio of the delay circuit 4 to the entire error correction circuit increases. This has caused an increase in the size of the error correction circuit.
[0012]
(Conventional example 2)
FIG. 25 is a block diagram showing an error correction detection circuit according to a second conventional example. This relates to a so-called one-byte error correction code for correcting an error of one byte in information data of (2b-3) bytes or less in which one byte is composed of b bits. The single-byte error correction circuit 14 generates 2-byte check data from the input information data (encoding), corrects a 1-byte error from the information data and the check data (decodes), and outputs correct information data. Output.
[0013]
By the way, since the maximum data length is limited to (2b-3) by the size b of 1 byte, when trying to handle information data longer than (2b-3) bytes, the information data is converted to (2b-3). ) Must be divided into blocks of the following length: When information data is continuously input to the error correction circuit 14, a single-byte error correction circuit 14 is required for each block, as shown in FIG. Therefore, there is a problem that the scale of the error correction circuit is increased.
[0014]
Further, in the case where only a single error correction circuit 14 is provided, there is a problem that information data cannot be continuously input / output to / from the error correction circuit because encoding / decoding is performed for each block of information data. there were.
[0015]
(Conventional example 3)
FIG. 27 is a block diagram showing a semiconductor memory device provided with an error correction detection circuit according to the third conventional example. The semiconductor memory device 13 includes a memory cell array 6 in which electrically rewritable memory cells are arranged in a matrix, a data circuit 8 for storing data of memory cells in the memory cell array and rewrite data, A plurality of data input / output buffers 12 for inputting rewrite data and outputting read data of memory cells, and generating inspection data for correcting and detecting errors from the input rewrite data, and reading the read data. An error correction / detection circuit 11 for correcting or detecting an error in the read data from the read data and the test data when outputting the data; an address buffer 10 to which a memory cell address is input and outputting a column address and a row address; And a column decoder 9 for controlling the input / output of the data of the data circuit 8 A row decoder 7 which decodes the row address, and a writing and reading control circuit 5 for outputting a control signal for rewriting and reading of data in the memory cell.
[0016]
Such a semiconductor memory device 13 is disclosed in the above-mentioned document (IEEE Journal of Solid-Slate Circuits, vol. 24, pp. 50, 1989). In this conventional example, the error correction codes are processed in parallel in order to minimize the processing time for encoding and decoding. This code is composed of 1-bit or plural-bit information data for each data input / output line and inspection data obtained from this information data, since parallel processing is possible.
[0017]
Every time the number of bits of the information data is doubled, the number of bits of the inspection data needs to be increased by about one bit. Therefore, as the number of bits of the information data increases, the ratio of the number of bits of the inspection data to the number of information data decreases. . On the other hand, since the number of exclusive ORs for encoding / decoding is approximately proportional to the number of bits of information data, the scale of the encoding / decoding circuit increases as the number of bits of information data increases. Therefore, there is a minimum value of the sum of the area of the redundant memory cell for performing error correction detection and the area of the encoding / decoding circuit, and there is an optimum value of the number of bits of information data that gives it.
[0018]
On the other hand, the error correction detection circuit includes a type realized by a shift register array in addition to the above type realized by an exclusive OR. In the latter case, it is necessary to provide a delay circuit realized by a number of shift register rows equal to the number of bits of test data and a number of shift register rows equal to the sum of the number of bits of information data and the number of bits of test data. Therefore, the required number of shift registers increases by about 2 bits each time the number of bits of information data doubles. For this reason, although the scale of the encoding / decoding circuit per unit information data decreases with an increase in the number of bits of the information data, the ratio of the delay circuit to the entire error correction circuit becomes large, especially when the code length is long, This has caused an increase in the size of the error correction circuit. Further, when this error correction detection circuit is used, there is a problem that a delay time proportional to the sum of the number of bits of information data and the number of bits of check data is required for decoding.
[0019]
FIG. 28 shows a layout of the memory cell array 6, the circuits 8, 11, 12 and the input / output pads 100 in the conventional example. As can be seen from this figure, since the error correction detection circuit 11 needs to be arranged between the memory cell array 6 and the data circuit 8 or where all the IO lines are gathered, there is no flexibility in their layout. There was a problem.
[0020]
Further, when a burst error occurs, the data becomes a code word, and the burst error cannot be detected in some cases. That is, when a burst error occurs, all "1" s of the data become "0" and all "0", and if all the data "0" are determined to have no error, the burst I can't know the error.
[0021]
[Problems to be solved by the invention]
As described above, conventionally, in the error correction detection circuit of the polynomial system, when the code length is long, the ratio of the delay circuit to the entire error correction circuit becomes large, which causes an increase in the scale of the error correction circuit.
[0022]
When only a single byte error correction circuit is provided, information data cannot be continuously input / output. To continuously input information data to the error correction circuit, a single block is required for each block. A one-byte error correction circuit is required, and the scale of the error correction circuit increases.
[0023]
Further, in the case of the type realized by a shift register array, especially in the case of a long code length, the ratio of the delay circuit to the entire error correction circuit increases, which causes an increase in the scale of the error correction circuit.
[0024]
Further, since the error correction detection circuit needs to be arranged between the memory cell array and the data circuit or in a place where all the IO lines are gathered, there is a problem that there is no flexibility in these layouts.
[0025]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device that can increase the degree of freedom in the layout of an error correction detection circuit.
[0026]
[Means for Solving the Problems]
(Constitution)
In order to solve the above problems, the present invention employs the following configuration.
[0027]
That is, the present invention provides a memory cell array in which memory cells are arranged in a matrix, a plurality of data output buffers for outputting data to the memory cells, and one or more of the data output buffers (the number of all buffers). A polynomial-type error correction / detection circuit that corrects or detects an error in read data for each predetermined number of bit data input serially, not for each byte input in parallel, for each half of the data. The storage device is characterized in that the error correction detection circuit is arranged not in a core area where the memory cell array is arranged but in a peripheral area where the data output buffer is arranged.
[0028]
Further, the present invention provides a memory cell array in which electrically rewritable memory cells are arranged in a matrix, and a plurality of data for inputting rewrite data from outside and outputting read data of the memory cells to the memory cell array. An input / output buffer and an input for each one or a plurality of data input / output buffers (（or less of the total number of buffers), not for each byte input in parallel, but for each predetermined number of bit data input serially. Check data for correcting or detecting errors from the rewritten data, and polynomial error correction for correcting or detecting errors in read data from read data and test data when outputting read data. A semiconductor memory device comprising: a detection circuit, wherein the error correction detection circuit includes the memory cell array. Rather than A area, it is characterized in that are arranged in a peripheral region in which the data output buffer is disposed.
[0029]
(Action)
According to the present invention, the degree of freedom in layout can be increased by providing an error correction circuit near each data (input / output) buffer for each data (input / output) buffer or for each of a plurality of data (input / output) buffers. it can. Furthermore, by performing encoding / decoding at a position where a burst error can be detected, occurrence of a burst error at the time of data rewriting can be detected.
[0030]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
[0031]
(1st Embodiment)
FIG. 1 is a block diagram showing a polynomial error correction detection circuit according to a first embodiment of the present invention. The basic configuration is the same as that of the circuit shown in FIG. 24. However, in this embodiment, the delay circuit is omitted, and switches S1 and S2 are provided on the input side instead. Then, the input data is repeated twice.
[0032]
At the time of the first input, the switch S1 is turned on and the switch S2 is turned off. Simultaneously with the input of all the first data, the syndrome calculation by the syndrome calculation circuit 1 ends, and the execution of the error position magnitude calculation is started. At this time, the switch S2 is turned on and the switch S1 is turned off. Therefore, the second input data is input to the error correction circuit 3.
[0033]
In this way, the circuit size of the error correction circuit can be reduced as compared with the related art, and not only can the circuit size of the error correction circuit be significantly reduced particularly in the case of a long code length, but also correct data can be output without increasing the delay time. . If a memory used as an input object has a data latch circuit of the same number as the code length, such as a NAND type EEPROM, it is not necessary to add a new circuit to repeat the input data twice.
[0034]
(Second embodiment)
FIG. 2 is a block diagram showing a polynomial error correction detection circuit according to a second embodiment of the present invention. The code length expansion circuit (byte length expansion circuit) 15 converts m successively input b bits / bytes into one mb bit / byte and outputs the result. This output is input to a single mb bit / byte error correction circuit 16. This error correction circuit 16 corrects a single mb bit / byte error.
[0035]
In this case, not only can the maximum data length of a single error correction circuit 16 be m × (2 mb−3) bytes (1 byte = b bits), but also the required check data can be 2 m bytes (1 byte). = B bits).
[0036]
Conventionally, when the maximum data length is set to m × (2 mb−3) bytes (1 byte = b bits), when information data is continuously input to the error correction circuit, the single-byte error correction circuit 14 m × (2 mb−3) / (2b−3) data and 2m × (2 mb−3) / (2b−3) data were required (FIG. 26). The following (Table 1) summarizes these figures.
[0037]
[Table 1]

[0038]
(Third embodiment)
FIG. 3 is a block diagram showing a semiconductor memory device according to a third embodiment of the present invention, and FIG. 4 is a layout diagram of the device. As can be seen from comparison with FIG. 27, in the present embodiment, the error correction circuit 11 is not provided between the memory cell array 6 and the data circuit 8 but the error correction detection circuit is provided for each data input / output buffer 12. 11 are provided. The error correction detection circuit 11 generates test data for correcting or detecting an error from the input rewrite data, and corrects or corrects an error in the read data from the read data and the test data when outputting the read data. It performs detection.
[0039]
In the present embodiment, information data having a 2048-bit configuration is input / output in parallel through eight data input / output pads. That is, information data of 256 bits is input / output for each data input / output pad. Here, an extended Hamming code (266, 256) for correcting a one-bit error in the 256 bits of information data and detecting an even-bit error is used.
[0040]
5 to 7 show the encoding / decoding circuit according to the present embodiment, and FIGS. 8 and 9 show the timings of control signals at the time of writing and at the time of reading, respectively.
[0041]
First, a description will be given of writing.
[0042]
While the signal DIN is high, (i = 1,..., 8) is input to the write information data DINi from the data input / output pad, and is input to the encoding circuit of FIGS. At this time, the signal DINOUTB is made low, and DINSi = DINi is sent to the data circuit 8. At the same time, since the signal SLINB is low and the signal DIV is high, the write information data DINi is input to the shift register SL1 and the shift register rows SL2,..., 10, and the calculation for generating check bits is performed. The clock of the shift register is synchronized with the clock of the input data DINi. Since the signals SLOUT1B and SLOUT2B are high, the outputs of the shift registers SL1 to SL10 are not output to DINSi.
[0043]
When the input of the write information data DINi is completed, the signal DINOUTB changes to high, the signal DIV changes to low, the signal SLINB changes to high, the signal SLOUT1B changes to low, and the clock of the shift register SL1 stops. At this time, the states of the shift register rows SL2,..., 10 represent nine check bits, and the input is fixed to low and output to CINSi. After that, the signal SLOUT1B is set high and the signal SLOUT2B is set low, and the state of the shift register SL1, which is one check bit, is output to DINSi. When the signal DINS goes low and the signal SLOUT2B goes high, the input to the data circuit 8 ends.
[0044]
In this way, the write data input to the data circuit 8 becomes 256-bit information data and 10-bit inspection data.
[0045]
Thereafter, the write data of 2048 bits (= 256 bits × 8 sets) is written to the memory cells while the signal PRG is high.
[0046]
Thereafter, it is detected whether or not a burst error has occurred while the signal BEREAD is high. When the signal BEREAD goes high, the written data is read out to DINi in the order in which it was output to DINSi. At this time, the signal DIV is set high and the signal SLINB is set low, and is input to the shift register SL1 and the shift register rows SL2,..., 10 to calculate the syndrome.
[0047]
When there is an error in the read data, at least one of the states L1i to L10i of the shift register becomes high. Therefore, when the signal DETE goes high after the syndrome calculation is completed, the signal ERDETi goes high. When the signal ERDETi goes high for all i, the signal BSTERR notifies that a burst error has occurred.
[0048]
In general, the input data of the error correction detection circuit can be either the write input data or its inverted data, but here the data is such that when a burst error occurs, the data does not become a codeword. That is, when a burst error occurs, all "1" s of the data become "0" and all "0", and if all the data "0" are determined to have no error, the burst I can't know the error. However, when a burst error occurs, all "0" s of the data become "1" and if all the data become "1", the error is detected, so that the burst error can be known.
[0049]
Next, reading will be described.
[0050]
Reading is performed in two cycles, that is, a first cycle for calculating the syndrome (a period during which the signal ECCREAD is high) and a second cycle for outputting correct data in which an error has been corrected while performing error correction (signal DATAOUT). Is high). In the first cycle, the signal DIV is high and the signal SLINB is low, and the read data is output to DINi and input to the shift register column. When all data has been input, the signal DETE for error detection is made high. At this time, if there is an error, at least one of the states of the shift register becomes high, so that the signal ERDETi indicating that an error has been detected becomes high. At this time, if there is an even number of errors, the signal 2ERDETi notifying it becomes high. This ends the first cycle.
[0051]
Subsequently, in the second cycle, the signal CORE goes high, and correct data having an error corrected is output to the outside while correcting the error. Data is output in synchronization with a certain clock, and at the same time, the state of the shift register row whose input is equal to the output shifts in synchronization with that clock while the signal SLINB remains high. The correction of the error is performed by inverting the data output when the shift register row enters a certain state. When the error has been corrected, the signal CORRECTi goes high. However, if the signal CORRECTi remains low, i.e., if no error has been corrected, despite the signal ERDETi, which indicates that an error has been detected, going high, the signal NOTCORi goes high. Become.
[0052]
In this manner, by providing an error correction detection circuit for each data input / output buffer and repeatedly reading input data to be decoded for two cycles, decoding can be performed without a delay time as compared with the conventional case, and the delay circuit is omitted. it can. Therefore, the circuit size of the error correction circuit can be reduced particularly when the code length is long.
[0053]
Further, in the case of the present embodiment, the error correction circuit 11 does not need to be disposed between the memory cell array 6 and the data circuit 8 as shown in FIGS. 12, so that the flexibility in layout can be increased.
[0054]
(Fourth embodiment)
FIG. 10 is a block diagram showing a semiconductor memory device according to a fourth embodiment of the present invention, and FIG. 11 is a layout diagram of the device. This embodiment differs from the third embodiment described above in that an error correction detection circuit 11 is provided for each of a plurality (two) of data input / output buffers 12.
[0055]
In the present embodiment, the information data having a 2048-bit configuration is input / output in parallel through eight data input / output pins IOi (i = 1,..., 8), ie, 256 bits of information per data input / output pin Data is input and output. In the layout, it is assumed that four data input / output pins are arranged at the left end (IO1 to 4) and four at the right end (IO5 to 8) of the chip. Here, the eight data input / output pins are divided into two sets (IO1-4, IO5-8). Each data of each set is input / output in parallel in synchronization with a certain clock. One byte (= 8 bits) of 4 bits input / output by the first clock and 4 bits input / output by the second clock Similarly, one byte is composed of four bits input / output at odd-numbered clocks and four bits input / output at even-numbered clocks (FIGS. 19A and 19B).
[0056]
Thus, each set is composed of information data of 128 bytes = 1024 bits. The error correction code used in this embodiment is a Reed-Solomon code (130, 128) for correcting one byte error in 128 bytes.
[0057]
12 to 20 show a specific circuit configuration of the error correction circuit used in this embodiment, and FIGS. 21 and 22 show timing diagrams of control signals at the time of writing and reading, respectively.
[0058]
First, a description will be given of writing.
[0059]
While the signal DIN is high, the write information data DINm-i (m = 1, 2, i = 1,..., 8) is input from the data input / output pin, and is input to the encoding circuits of FIGS. Will be entered. At this time, the signal DINOUTB is made low, and DINSm-i = DINm-i is sent to the data circuit 8. At the same time, since the signal DIV is high, the write information data DINm-i is input to the 8-bit shift register SL1, and the calculation for generating the check bits is performed. The clock of the shift register is synchronized with the clock of the input data DINm-i. Since the signal SLOUTB is high, the output SLOUTm-i of the 8-bit shift register SL2 is not output to DINSm-i.
[0060]
When the input of the write information data DINm-i is completed, the signal DINOUTB changes to high, the signal DIV changes to low, the signal SLOUTB changes to low, and the input SLINm-i is fixed to low. The status is output to DINSm-i. Thereafter, when the signal DINS goes low and the signal SLOUTB goes high, the input of the write data ends.
[0061]
In this way, the write data input to the data circuit 8 is two code words composed of 128-byte information data and 2-byte check data.
[0062]
Thereafter, the write data is written to the memory cells while the signal PRG is high.
[0063]
Thereafter, it is detected whether or not a burst error has occurred while the signal BEREAD is high. When the signal BEREAD goes high, the written data is read out to DOUTm-i in the order in which they were output to DINSm-i. At this time, the signal CCRB is set to low and input to the shift registers SL3 and SL4 to calculate the syndrome. If there is an error in the read data, one or more of the S0 mi become high. Therefore, when the signal DETE goes high after the syndrome calculation ends, the signal ERDETmB goes high. When both signals ERDETmB are low for m = 1 and 2, signal BSTERR notifies that a burst error has occurred.
[0064]
In general, the input data of the error correction detection circuit can be either the write input data or its inverted data, but here the data is such that when a burst error occurs, the data does not become a codeword. That is, when a burst error occurs, all "1" s of the data become "0" and if the data becomes "0", it is determined that there is no error in all the "0" data. I can't know the error. However, when a burst error occurs, all "0" s of the data become "1" and if all the data become "1", the error is detected, so that the burst error can be known.
[0065]
Next, reading will be described.
[0066]
Reading is performed in two cycles, that is, a first cycle for calculating the syndrome (a period during which the signal ECCREAD is high) and a second cycle (for outputting the correct data in which the error has been corrected while the error is being corrected). (Period during which DATAOUT is high). In the first cycle, the signal ECCRB becomes low, the read data is output to DOUTm-i, and is input to the 8-bit shift registers SL3, 4, 8, and 9. When all data has been input, the signal DETE for error detection is made high. At this time, if there is an error, at least one of the states of the shift register becomes high, so that the signal ERDETmB indicating that an error has been detected becomes low. This ends the first cycle.
[0067]
Subsequently, in the second cycle, the signal OUTEB becomes low, and correct data having errors corrected is output to the outside while correcting errors. Data is output in synchronization with a certain clock. At the same time, the outputs of the 8-bit shift registers SL5 and SL10 whose inputs are low shift in synchronization with the clock and feed back. The error is corrected by inverting the data output when the outputs of the 8-bit shift registers SL5 and SL10 match the syndrome Sm-i. When the error has been corrected, the signal CORRECTi goes high. However, if the signal CORRECTi remains low despite the fact that the signal ERDETi, which indicates that an error has been detected, has gone high, that is, if the error has not been corrected, the signal NOTCORi goes high. become.
[0068]
In this manner, by providing an error correction detection circuit for each set of data input / output buffers and repeatedly reading out input data to be decoded for two cycles, decoding can be performed without a delay time as compared with the prior art. Can be omitted. Therefore, the circuit size of the error correction circuit can be reduced especially in the case of a long code length.
[0069]
The maximum code length can be increased by expanding the number of bits per byte from 4 bits to 8 bits.
[0070]
Further, in the case of the present embodiment, the error correction circuit 11 does not need to be disposed between the memory cell array 6 and the data circuit 8 as shown in FIGS. 12, so that the flexibility in layout can be increased.
[0071]
The present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the scope of the invention.
[0072]
【The invention's effect】
As described above in detail, according to the present invention, an error correction circuit is provided in the vicinity of a data (input / output) buffer for each data (input / output) buffer or for each of a plurality of data (input / output) buffers, thereby improving layout. The degree of freedom can be increased. Furthermore, by performing encoding / decoding at a position where a burst error can be detected, occurrence of a burst error at the time of data rewriting can be detected.
[0073]
In the 1-byte error detection code, the code length can be increased by changing the number of bits constituting one byte from a unit input / output in parallel to a plurality of units. Further, by inputting the same data twice, it is possible to omit a delay circuit which accounts for a large proportion of the circuit size of the error correction circuit. Decoding for error correction detection can be performed without any.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a polynomial error correction detection circuit according to a first embodiment.
FIG. 2 is a block diagram showing a polynomial error correction detection circuit according to a second embodiment.
FIG. 3 is a block diagram showing a semiconductor memory device according to a third embodiment.
FIG. 4 is a layout diagram of a memory cell array, circuits, input / output pads, and the like in a third embodiment.
FIG. 5 is a diagram showing an encoding / decoding circuit in the device of the third embodiment.
FIG. 6 is a diagram showing an encoding / decoding circuit in the device of the third embodiment.
FIG. 7 is a diagram showing an encoding / decoding circuit in the device of the third embodiment.
FIG. 8 is a diagram showing timings of control signals at the time of writing and at the time of reading in the device according to the third embodiment.
FIG. 9 is a diagram showing timings of control signals at the time of writing and reading in the device of the third embodiment.
FIG. 10 is a block diagram showing a semiconductor memory device according to a fourth embodiment.
FIG. 11 is a layout diagram of a memory cell array, circuits, input / output pads, and the like in a fourth embodiment.
FIG. 12 is a diagram showing a specific circuit configuration of an error correction circuit.
FIG. 13 is a diagram showing a specific circuit configuration of an error correction circuit.
FIG. 14 is a diagram showing a specific circuit configuration of an error correction circuit.
FIG. 15 is a diagram showing a specific circuit configuration of an error correction circuit.
FIG. 16 is a diagram showing a specific circuit configuration of an error correction circuit.
FIG. 17 is a diagram showing a specific circuit configuration of an error correction circuit.
FIG. 18 is a diagram showing a specific circuit configuration of an error correction circuit.
FIG. 19 is a diagram showing a specific circuit configuration of an error correction circuit.
FIG. 20 is a diagram showing a specific circuit configuration of an error correction circuit.
FIG. 21 is a diagram showing a specific circuit configuration of an error correction circuit.
FIG. 22 is a diagram showing a specific circuit configuration of an error correction circuit.
FIG. 23 is a diagram showing a configuration example of a 1-bit error correction code in a matrix system and a polynomial system.
FIG. 24 is a block diagram showing an error correction detection circuit according to a first conventional example.
FIG. 25 is a block diagram showing an error correction detection circuit according to a second conventional example.
FIG. 26 is a diagram showing an example in which a plurality of single-byte error correction circuits are provided in the second conventional example.
FIG. 27 is a block diagram showing a semiconductor memory device including an error correction detection circuit according to a third conventional example.
FIG. 28 is a diagram showing a layout of a memory cell array, circuits, input / output pads, and the like in a third conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Syndrome calculation circuit 2 ... Error position magnitude calculation circuit 3 ... Error correction circuit 4 ... Delay circuit 5 ... Write / read control circuit 6 ... Memory cell array 7 ... Row decoder 8 ... Data circuit 9 ... Column decoder 10 ... Address buffer 11 ... Error correction detection circuit 12 Data input / output buffer 13 Semiconductor memory device 14 Single byte error correction circuit 15 Code length expansion circuit 16 Single mb bit / byte error correction circuit 100 Data input / output pad 101 IO line

Claims (3)

A memory cell array in which memory cells are arranged in a matrix; a plurality of data output buffers for outputting data to the memory cell array; and one or more of the data output buffers (（or less of the total number of buffers) A polynomial type error correction detection circuit for correcting or detecting errors in read data for each predetermined number of bit data input serially, not for each byte input in parallel. ,
The error correction detection circuit includes: a syndrome calculation circuit configured to generate a syndrome from information data and test data input in a first cycle due to access to a predetermined address of the memory cell ; and an error detection unit configured to detect an error from the syndrome obtained by the syndrome calculation circuit. An error position size calculation circuit for calculating the position and size, and a second cycle by accessing the same address of the memory cell based on the error position and size obtained by the error position size calculation circuit. An error correction circuit that outputs error-corrected information data from the same information data as the input information data,
2. A semiconductor memory device according to claim 1, wherein said semiconductor memory device is arranged not in a core region in which said memory cell array is arranged but in a peripheral region in which said data output buffer is arranged. A memory cell array in which electrically rewritable memory cells are arranged in a matrix, a plurality of data input / output buffers for inputting rewrite data from the outside to the memory cell array and outputting read data from the memory cells, Rewriting data input for each of a predetermined number of bit data input serially, not for each byte input in parallel, for each or a plurality of data input / output buffers (（or less of the total number of buffers) And a polynomial error correction detection circuit for correcting or detecting an error in the read data from the read data and the test data when outputting the read data, and generating a check data for correcting or detecting an error from the read data. Semiconductor memory device,
The error correction detection circuit includes: a syndrome calculation circuit configured to generate a syndrome from information data and test data input in a first cycle due to access to a predetermined address of the memory cell ; and an error detection unit configured to detect an error from the syndrome obtained by the syndrome calculation circuit. An error position size calculation circuit for calculating the position and size, and a second cycle by accessing the same address of the memory cell based on the error position and size obtained by the error position size calculation circuit. An error correction circuit that outputs error-corrected information data from the same information data as the input information data,
2. A semiconductor memory device according to claim 1, wherein said semiconductor memory device is arranged not in a core region in which said memory cell array is arranged but in a peripheral region in which said data output buffer is arranged. 3. The method according to claim 2 , wherein at the time of rewriting data, an operation for detecting burst error correction is performed at a position where all input data of the error correction detection circuit does not become "0" when a burst error occurs. Semiconductor storage device.

Images