JP3600311B2 - Magnetic recording / reproducing device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a magnetic recording / reproducing apparatus, and more particularly to the transfer of a write data signal and a read data signal between a write data generation circuit and a read / write amplifier when data is recorded on a recording medium.
[0002]
[Prior art]
A conventional magnetic recording / reproducing apparatus generally includes a disk-shaped magnetic recording medium 1, a magnetic head 10, an R / W (write / read) amplifier 32, an R / W signal processing circuit 33, as shown in FIG. It comprises a controller 4, a microcomputer 5, a servo control circuit 6, and an I / F (interface) circuit 7. The R / W signal processing circuit 33 includes a write data generation circuit 38 and a read data reproduction circuit 9.
[0003]
Recording data sent from a host (not shown) is sent to the R / W signal processing circuit 33 via the I / F circuit 7 and the controller 4, and the write data generation circuit 38 converts the write data into a recording code suitable for the magnetic recording medium 1. After the conversion, the magnetic head 10 is driven by the R / W amplifier 32 and written on the magnetic recording medium 1. The data read from the magnetic recording medium 1 by the magnetic head 10 is amplified by the R / W amplifier 32, decoded by the read data reproducing circuit 9 of the R / W signal processing circuit 33, and It is sent to the host via the / F circuit 7.
[0004]
The positioning of the magnetic head 10 on the magnetic recording medium 1 and the rotation of the magnetic recording medium 1 are controlled by the servo control circuit 6 and the microcomputer 5. In the data surface servo method, part of data read from the magnetic recording medium 1 is servo data, and the servo data signal H is extracted by a read data reproducing circuit 9 and used for positioning control of the magnetic head 10. .
[0005]
FIG. 26 is a block diagram showing an example of the R / W amplifier 32 and the R / W signal processing circuit 33 in FIG.
[0006]
In the figure, an R / W amplifier 32 is composed of a read amplifier / write driver 11, a frequency dividing circuit 12, a read / write selector 13, a read buffer amplifier 14, and a write current source circuit 15. The read amplifier / write driver 11 is connected to the magnetic head 10 and has the same number of amplifiers and drivers as the magnetic head. The R / W signal processing circuit 33 includes a write data generation circuit 38 and a read data reproduction circuit 9, and the write data generation circuit 38 further includes a write correction circuit 38a and an encoding circuit 38b.
[0007]
Recording data E sent from the host via the I / F circuit 7 and the controller 4 in FIG. 25 is encoded by the encoding circuit 38b and is suitable for recording on a magnetic recording medium such as 1-7RLLC or 8 / 9GCR in FIG. The data is converted into a recording code as shown in (a) and is processed into a data pulse signal C having an edge phase shifted for each data pattern by a write correction circuit 38a to reduce a peak shift due to magnetization interference or the like, and R / W The signal is sent to the amplifier 32. This data pulse signal C is a serial RZ (Return-to-Zero) code as shown in FIG.
[0008]
In the R / W amplifier 32, the data pulse signal C is converted into a NRZI (Non-Return-to-Zero-Inverted) code K as shown in FIG. A corresponding current pulse is supplied from the write driver 11 to the magnetic head 10. Thereby, data is recorded on the magnetic recording medium 1 of FIG.
[0009]
In general, since the R / W amplifier 32 is arranged near the magnetic head 10, the R / W amplifier 32 and the R / W signal processing circuit 33 are separate ICs (integrated circuits). They are connected by cables (hereinafter referred to as film cables).
[0010]
The read / write selector 13 is a switching circuit for switching between a read operation and a write operation. The read / write selector 13 stops the write driver at the time of reading, and stops the read amplifier at the time of writing. The write current source circuit 15 is a current source circuit for setting the output current of the write driver.
[0011]
The read buffer amplifier 14 is a buffer amplifier for amplifying the analog read data signal from the read amplifier 11 and transmitting the amplified read data signal to the read data reproducing circuit 9. The read data reproducing circuit 9 is a circuit that reproduces the read data from the read signal D from the read buffer amplifier 14, decodes the recording code into the original data, and outputs it to the controller 4 in FIG.
[0012]
[Problems to be solved by the invention]
In magnetic disk devices and the like, the speed of data transfer has been increasing year by year. If the speed is further increased in the future, in the above-described conventional technology, the IC of the R / W signal processing circuit 33 and the IC of the R / W amplifier 32 are not The transfer of the write data signal during the period becomes a bottleneck for speeding up.
[0013]
The film cable used for connection between these ICs has a low transmission capacity and is likely to cause waveform distortion of a high-frequency pulse signal. This is due to the fact that the shape is easily changed to facilitate mounting on a magnetic recording / reproducing device, the cost of the cable is reduced, and the characteristic impedance of the cable is increased, and the loss of conductors and insulators is increased. Or to do.
[0014]
FIG. 28 shows a write data pulse signal waveform of a conventional magnetic disk device. For example, (1, 1, 0, 0, 1) of (1, 1, 0, 0, 1) after being converted into a recording code as shown in FIG. When the write data train is transmitted at a high speed, the ideal pulse waveform is as shown in FIG. 28B, but actually, the waveform is distorted as shown by the solid line in FIG. 28C. It becomes. When the read signal whose waveform has been blunted in this way is shaped by the R / W amplifier 32, the read / write signal shown in FIG. 28D is obtained due to the density of the original data pattern (change in the interval of "1" bits) shown in FIG. As shown in (1), the phase relationship between the rising edge and the falling edge of the obtained pulse signal is shifted. In addition, the amplitude also decreases, and the level margin decreases, which causes a data error.
[0015]
In magnetic disk devices and the like, the speed of data transfer has been increased year by year, and the data transfer rate has been increased to 10 MB / sec or more, and the specifications for the timing margin have become strict. In the current magnetic disk drive, since the RZ code format is used for the write data transmission between the R / W signal processing IC and the R / W amplifier IC, the write data frequency at a transfer rate of 10 MB / sec is 8 / 90 MHz for 9 GCR and 60 MHz for 1-7 RLLC.
[0016]
On the other hand, the write data transmission path between the R / W signal processing IC and the R / W amplifier IC of the current magnetic disk drive is provided with a film cable having a length of about 100 mm and a connector. Considering the substrate wiring and the input / output terminals of the IC, the inductance component is 100 nH and the capacitance component is 20 pF or more. Therefore, the transmission frequency limit is about 100 MHz even at the ECL level. Therefore, the current system cannot support high-speed data transfer of 20 MB / sec or more.
[0017]
In addition, even when a high-performance cable is used, a high-speed buffer is required to be driven, which increases power consumption and increases costs.
[0018]
By the way, conventionally, the write data between the R / W signal processing circuit 33 and the R / W amplifier 32 between the ICs has been transferred in a TTL or ECL level voltage format. FIG. 29 shows an example of the transfer at the ECL level. In the R / W signal processing circuit 83, an ECL output circuit 1001 is provided on the output side of the write data generation circuit 38, and in the R / W amplifier 82, An ECL input circuit 1002 is provided on the side to transmit the write data signal C82 on the film cable 2013 at the ECL level.
[0019]
29, portions and signals corresponding to those in FIG. 25 are denoted by the same reference numerals. The R / W signal processing circuit 83 has a register (not shown), and can switch the characteristics of each unit. The contents of this register can be set programmably by a control signal S4 from the microcomputer 5.
[0020]
Also, the transfer of the read data signal D between the R / W signal processing circuit 83 and the R / W amplifier 82 has been performed in the form of a voltage at the analog signal level.
[0021]
Here, since the transmission capability of the film cable 2013 is low, the waveform rounding tends to occur particularly in the high-frequency pulse waveform write data C82.
[0022]
Therefore, in order to realize high speed, it is necessary to lower the impedance of the film cable 2013 and increase the driving capability of the output buffer, but this leads to an increase in power consumption. For example, when transmitting at an ECL level of 0.8 V amplitude using a 50Ω film cable, the ECL output circuit 1001 requires about 100 mW of power consumption per circuit.
[0023]
However, with the miniaturization of magnetic disk devices, the demand for lower power consumption for each circuit is increasing year by year. For example, the user's demand for the power consumption of the entire R / W signal processing circuit 83 is about 500 mW or less, and this cannot be achieved if the ECL output circuit 1001 consumes 100 mW.
[0024]
In the case of transmitting a high-speed pulse signal, if the driving capability is increased, it becomes a noise source, adversely affects peripheral circuits, and causes a transmission error or the like to deteriorate device performance.
[0025]
Further, a terminating resistor is added for impedance matching. However, since the R / W amplifier 82 is disposed on the film cable 2013 near the magnetic head 10, there is little space for mounting external components, and therefore, It is necessary to reduce the number of parts as much as possible. Even when a terminating resistor is incorporated in the R / W amplifier 82, the resistance value is limited, so that optimum impedance matching may not be performed.
[0026]
By the way, in the field of communication, signals have been conventionally transmitted and received in the form of current. One example is described in a paper entitled "Low-Power Bipolar Current Mode I / O Circuit" published in the 1994 IEICE Autumn Meeting. ing.
[0027]
In the field of communications, the characteristics of cables used as transmission lines are standardized, and target cables can be specified.However, there are various types of film cables used in magnetic disk devices, and The characteristics are different. In the technique described in the above-mentioned paper, no consideration is given to a change in the characteristics of the transmission line.
[0028]
An object of the present invention is to solve such a problem, speed up data between an R / W signal processing circuit and an R / W amplifier, and reduce power consumption to suppress an increase in cost. And a circuit used for the same.
[0029]
[Means for Solving the Problems]
In order to achieve the above object, a magnetic recording / reproducing apparatus according to the present invention uses a write data generation circuit of an R / W signal processing circuit in an interleaved format and exchanges data with an R / W amplifier via a plurality of signal lines. Further, the R / W amplifier according to the present invention is provided with a circuit for synthesizing the interleaved write data from the R / W signal processing circuit, and forms an IC.
[0030]
A divide-by-2 circuit is provided at the output section of the write data generation circuit, so that write data can be exchanged using the NRZI code.
[0031]
A differential buffer and a receiver are provided so that write data can be transferred by a differential signal.
[0032]
In order to achieve the above object, according to the present invention, a current format output circuit is provided in a write data output unit of a R / W signal processing circuit, and a current format input circuit is provided in a write data input unit of an R / W amplifier, It is possible to transfer write data between the R / W signal processing circuit and the R / W amplifier in a current format.
[0033]
A current format output circuit is provided in the read data output section of the R / W amplifier, and a current format input circuit is provided in the read data input section of the R / W signal processing circuit, so that the R / W signal processing circuit is connected to the R / W amplifier. It is now possible to transfer read data in the form of current.
[0034]
A bias current adjusting circuit is provided in the current type output circuit so that the output bias current can be adjusted.
[0035]
A current switching circuit is provided in the current type output circuit, so that the output current can be switched.
[0036]
A register is provided so that the current switching circuit can be programmed by a microcomputer or the like.
[0037]
An output amplitude limiter is provided in the current type input circuit.
[0038]
[Action]
According to the present invention, the write data signal is transferred between the R / W amplifier and the R / W signal processing circuit using a plurality of signal lines by the interleave format, so that the frequency of the signal handled by one signal line is reduced. be able to.
[0039]
Further, by transmitting and receiving the write data signal between the R / W amplifier and the R / W signal processing circuit using the NRZI code, the frequency of the signal can be reduced.
[0040]
Therefore, even if the R / W amplifier is formed into an IC and connected to the R / W signal processing circuit through an inexpensive transmission line, the transmitted write data signal is shifted in the phase relationship between the rising and falling edges due to waveform distortion. Does not occur.
[0041]
Further, according to the present invention, the transfer of the write data signal between the R / W amplifier and the R / W signal processing circuit can be performed in a current format, so that the signal amplitude can be reduced and the output of the R / W signal processing circuit can be reduced. The power consumption of the circuit can be reduced.
[0042]
In addition, by passing the read data signal between the R / W amplifier and the R / W signal processing circuit in the form of current, the signal amplitude can be reduced, so that the power consumption of the output circuit of the R / W amplifier can be reduced.
[0043]
In addition, since driving is performed with a small amplitude, the amount of generated noise can also be reduced, and the mixing of noise into peripheral circuits can be suppressed.
[0044]
Further, the input impedance of the current type input circuit can be adjusted by the bias current, impedance matching can be achieved without adding a terminating resistor, and the number of components can be reduced.
[0045]
In addition, since matching can be achieved with respect to an arbitrary characteristic impedance, it can be used for various types of film cables and has a high degree of freedom.
[0046]
Further, since the output amplitude of the current type input circuit is limited, the circuit is not saturated even when a large current is input.
[0047]
【Example】
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a first embodiment of a magnetic recording / reproducing apparatus according to the present invention, wherein 2 is an R / W amplifier, 3 is an R / W signal processing circuit, 8 is an interleave write data generation circuit, Parts corresponding to those in FIG. 25 are denoted by the same reference numerals, and redundant description will be omitted.
[0048]
In this figure, this embodiment comprises a magnetic recording medium 1, a magnetic head 10, an R / W amplifier 2, an R / W signal processing circuit 3, a controller 4, a microcomputer 5, a servo control circuit 6, and an I / F circuit 7. Is done. The R / W signal processing circuit 3 includes an interleave write data generation circuit 8 and a read data reproduction circuit 9.
[0049]
FIG. 2 is a block diagram showing a specific example of the R / W amplifier 2 and the R / W signal processing circuit 3 in FIG. 1. Reference numeral 16 denotes a synthesizing circuit, which corresponds to FIG. 1 and FIG. Have the same reference numerals.
[0050]
Referring to FIG. 1, the R / W amplifier 2 includes a read amplifier / write driver 11, a frequency dividing circuit 12, a read / write selector 13, a read buffer amplifier 14, a write current source circuit 15, and a combining circuit 16. That is, the configuration is such that the synthesizing circuit 16 is added to the conventional R / W amplifier 32 shown in FIG. 26, and the interleaved write data generation circuit 8 is used for the R / W signal processing circuit 3. It is because of that. As in the case of the conventional R / W amplifier 32 shown in FIG. 26, the read amplifier / write driver 11 of the R / W amplifier 2 is connected to the magnetic head 10, and the same number or more amplifiers and drivers as the magnetic head are provided. have.
[0051]
FIG. 3 is a block diagram showing a specific example of the interleave write data generation circuit 8 in FIGS. 1 and 2, and this specific example includes an encoding circuit 8b, a write correction circuit 8a, and an interleave switch 8c.
[0052]
Next, the operation of the first embodiment will be described with reference to FIG. 4 showing signals of respective parts in FIG. 2 and FIG.
[0053]
Recording data E sent from the host via the I / F circuit 7 and the controller 4 in FIG. 1 is supplied to the R / W signal processing circuit 3, and is encoded by the encoding circuit 8b shown in FIG. It is converted into a recording code I suitable for recording on the magnetic recording medium 1 (FIG. 1) such as / 9GCR. The recording data E may be transferred as parallel data, in which case it is advantageous for speeding up. The data sequence I of the recording code is supplied to the write correction circuit 8a, and processed into a data pulse signal in which the phase of the edge is shifted back and forth by a data pattern in order to reduce a peak shift due to magnetization interference or the like. This data pulse signal is supplied to the interleave switch 8c, and pulses for the "1" bit of the data pulse signal (hereinafter, referred to as "1" pulses) are alternately distributed every other, and every other "1" pulse , And an interleaved write data pulse signal C2 having every other “1” pulse, and transmitted to the R / W amplifier 2 respectively. These interleaved write data pulse signals C1 and C2 are interleaved RZ (Return-to-Zero) codes in which every other “1” pulse shown in FIG. 4 is thinned out alternately.
[0054]
FIG. 5 is a circuit diagram showing a specific example of the interleave switch 8c in FIG. 3, wherein 8c1 and 8c2 are AND gates, 8c3 is a D-type flip-flop circuit (hereinafter, referred to as D-FF), and 8c4 is an inverter. .
[0055]
FIG. 6 is a timing chart showing signals of respective parts in FIG. 5, and signals corresponding to the signals in FIG. 5 are denoted by the same reference numerals.
[0056]
5 and 6, the data pulse signal C from the write correction circuit 8a in FIG. 3 is supplied to the AND gates 8c1 and 8c2, is inverted by the inverter 8c4, and is supplied as the clock ck of the D-FF 8c3. The D-FF 8c3 is triggered by the rising edge of the clock ck, that is, the falling edge of the data pulse signal C, and is a gate pulse X2 which is a QB output whose level is inverted with respect to the Q output of the D-FF 8c3. As a D input.
[0057]
Therefore, assuming that the Q output of the D-FF 8c3 is "L" (low level) and the QB output is "H" (high level), the "H" gate pulse X2, which is the QB output, is supplied to the AND gate 8c1. The “L” gate pulse X1, which is the Q output, is supplied to the AND gate 8c2. Therefore, the AND gate 8c1 turns on and the AND gate 8c2 turns off.
[0058]
When the "1" pulse of the data pulse signal C is supplied in such a state, the "1" pulse passes through the AND gate 8c1, and the D-FF 8c3 sets the "H" level at the falling edge of the "1" pulse. The input is fetched, the Q output becomes "H", and the QB output becomes "L". Therefore, the AND gate 8c1 turns off and the AND gate 8c2 turns on.
[0059]
Thereafter, when the "1" pulse of the data pulse signal C is supplied, the "1" pulse passes through the AND gate 8c2, and the D-FF 8c3 is set to the "L" D input at the falling edge of the "1" pulse. And its Q output becomes "L" and its QB output becomes "H". Therefore, the AND gate 8c1 turns on and the AND gate 8c2 turns off.
[0060]
Hereinafter, the same operation is performed, and the "1" pulse of the data pulse signal C sequentially supplied alternately passes through the AND gates 8c1 and 8c2. Therefore, an interleaved write data signal C1 composed of every other "1" pulse of the data pulse signal C from the AND gate 8c1 is interleaved with another interleaved "1" pulse of the data pulse signal C from the AND gate 8c2. The write data signal C2 is obtained respectively.
[0061]
Here, as the interleaving method, a data pulse signal as shown in FIG. 7A is alternately distributed for each bit to form a data pulse signal as shown in FIGS. 7B and 7C. In the case of a recording code in which “1” bits are not continuous, such as 1-7RLLC, even if interleaving is performed, the frequency of the densest pattern does not change and there is no effect. However, as in 8/9 GCR, “1” is not effective. This is effective for a recording code in which bits are continuous.
[0062]
In this embodiment, the case where the number of interleaved data is two has been described, but the case where the number of interleaved data is three or more can be easily realized by the same method.
[0063]
In the first embodiment, as described above, the interleave write data generation circuit 8 generates two or more interleave write data pulse signals by alternately thinning out every other "1" pulse of the write data. Alternatively, two or more interleaved write data pulse signals are generated by alternately thinning out write data every other bit.
[0064]
In the R / W amplifier 2, these two interleaved write data pulse signals C1 and C2 are synthesized by the synthesis circuit 16, and the original data pulse signal J is restored. This combining circuit 16 can be realized by, for example, an OR circuit. This data pulse signal J is frequency-divided by a divide-by-2 circuit 12 and converted into a signal K of NRZI (Non-Return-to-Zero-Inverted) code, and a current pulse corresponding to this signal K is supplied from the write driver 11 to the magnetic field. The data is supplied to the head 10 and data is recorded on the magnetic recording medium 1.
[0065]
FIG. 8 is a block diagram showing another specific example of the interleave write data generation circuit 8 in FIGS.
[0066]
In this specific example, an interleave switch 8c is provided at the next stage of the encoding circuit 8b, and after the output signal of the encoding circuit 8b is interleaved by the interleave switch 8c as described above, each obtained interleave write data pulse signal is written. The correction circuits 8a1 and 8a2 perform the same correction processing as the write correction circuit 8a in FIG.
[0067]
This configuration has an advantage that the operation speed of the write correction circuits 8a1 and 8a2 can be reduced.
[0068]
FIG. 9 is a block diagram showing a specific configuration of the R / W amplifier 42 and the R / W signal processing circuit 43 in the second embodiment of the magnetic recording / reproducing apparatus according to the present invention. Are denoted by the same reference numerals, and redundant description is omitted.
[0069]
In the figure, the R / W amplifier 42 comprises a read amplifier / write driver 11, a read / write selector 13, a read buffer amplifier 14, a write current source circuit 15 and a buffer 17, and the R / W signal processing circuit 43 It comprises a frequency dividing circuit 19, a write data generating circuit 18 and a read data reproducing circuit 9.
[0070]
26, the write data generation circuit 18 of the R / W signal processing circuit 43 is the same as the write data generation circuit 38 of the R / W signal processing circuit 33 shown in FIG. The write data after recording code conversion (FIG. 10) obtained from the encoding circuit 38b in FIG. 26) is corrected as described above by the write correction circuit (corresponding to the write correction circuit 38a in FIG. 26). As a result, a write data pulse signal C shown in FIG. 10 is obtained. This write data pulse signal C is frequency-divided by the divide-by-2 circuit 19 and sent to the R / W amplifier 42 as the NRZI code write data pulse signal K as shown in FIG.
[0071]
As described above, the transfer of the write data pulse signal K between the R / W amplifier 42 and the R / W signal processing circuit 43 is performed by the NRZI code, so that the write data can be transmitted at a low frequency, and Higher speed can be accommodated, and power consumption can be reduced by lowering the operating frequency.
[0072]
FIG. 11 is a diagram in which the arrangement order of the write data generation circuit 18 and the divide-by-2 circuit 19 in FIG. 9 is changed, and the divide-by-2 circuit 19 is arranged between the encoding circuit 20 and the write correction circuit 21. is there.
[0073]
According to this configuration, the recording data E from the controller 4 (FIG. 1) is converted into a code suitable for recording by the encoding circuit 20, and then becomes an NRZI code signal by the divide-by-2 circuit 19. 26, and is transmitted to the R / W amplifier 42 after being corrected as in the write correction circuit 38a in FIG. The advantage of this configuration is that the frequency of the write data pulse signal handled by the write correction circuit 21 can be reduced.
[0074]
By the way, it is more preferable that the write data pulse signal K be a differential signal. FIG. 12 shows a main part of the R / W signal processing circuit 53 in a third other embodiment of the magnetic recording and reproducing apparatus according to the present invention. FIG.
[0075]
In the figure, in the R / W signal processing circuit 53, the differential buffer 22 is provided at the output stage of the divide-by-2 circuit 19, and the differential receiver 23 is provided at the input stage of the R / W amplifier 52. The transfer of the differential write data pulse signals K1 and K2 is performed between the differential buffer 22 and the differential receiver 23.
[0076]
Here, the effect of the differentialization of the write data pulse signal K will be described with reference to FIG.
[0077]
Now, as shown in FIG. 13, the write data pulse signal K of the NRZI code generated by the divide-by-2 circuit 19 in FIG. 9 or FIG. This signal is inverted by the "1" pulse in the column. When such write data pulse signal K is transmitted to the R / W amplifier 42 as it is as shown in FIG. 9, the waveform of the transmitted write data pulse signal K0 has a rising edge or a rising edge as shown in FIG. The falling edge becomes dull. In such a single signal line, if the waveform of the write data pulse signal K0 is shaped by the buffer 17 (FIG. 9) of the R / W amplifier 42 due to the rounding of the waveform, the phase relationship between the rising edge and the falling edge is also reduced. The NRZI code L deviated from the phase relationship between the rising and falling edges of the write data pulse signal K is obtained. In the NRZI code, since these edges are used as data, a shift in the phase relationship causes a data error, thereby deteriorating the performance of the device.
[0078]
On the other hand, as shown in FIG. 12, differential write data pulse signals K1 and K2, which are a pair of the write data pulse signal K0 and its inverted one, are transmitted from the R / W signal processing circuit 53 to the R / W amplifier 52. In the case of transmission, even if the waveforms of these differential write data pulse signals K1 and K2 become as described above, the differential receiver 23 of the R / W amplifier 52 outputs these differential write data pulse signals K1 and K2. Since the inverted signal M is obtained when the waveforms cross each other (that is, become equal), the obtained signal M is different from the ideal waveform write data pulse signal K generated by the divide-by-2 circuit 19. Although the phase is shifted as a whole, the timing relationship between the rising edge and the falling edge is almost the same as that of the write data pulse signal K. Thus, occurrence of a data error or the like can be prevented.
[0079]
The transmission of the write data pulse signal by the differential method can be applied to the embodiment shown in FIGS. 1 and 9 and the same effect can be obtained.
[0080]
FIG. 14 is a block diagram showing a specific configuration of an R / W amplifier 62 and an R / W signal processing circuit 63 of a fourth alternative embodiment of the magnetic recording / reproducing apparatus according to the present invention. 2 are denoted by the same reference numerals, and redundant description will be omitted.
[0081]
FIG. 15 is a diagram showing signals of respective units in FIG. 14, and signals corresponding to the signals in FIG. 14 are denoted by the same reference numerals.
[0082]
In this embodiment, similarly to the first embodiment shown in FIG. 1, the transfer of the write data pulse signal between the R / W amplifier 62 and the R / W signal processing circuit 63 is performed in an interleaved and NRZI code. Things.
[0083]
14 and 15, the interleave write data generation circuit 8 generates the interleave write data pulse signals C1 and C2 from the write data sequence after the recording code conversion, as described in FIG. , 25 and converted into interleaved write data signals C3 and C4 of NRZI code. These interleaved write data signals C3 and C4 are transmitted to the R / W amplifier 62, and are combined by the combining circuit 26 to become a signal N. This combining circuit 26 can be realized by, for example, a mismatch circuit (exclusive OR circuit). The write driver 11 supplies a current pulse corresponding to the composite signal N to the magnetic head.
[0084]
Also in the fourth embodiment, the write data pulse signals C3 and C4 may be the differential write data pulse signals described with reference to FIGS. Thus, it is possible to prevent a change in the timing relationship between the rising edge and the falling edge of the write data pulse signals C3 and C4.
[0085]
In each of the first to fourth embodiments described above, the R / W amplifier and the R / W signal processing circuit may be integrated into an IC, and these ICs may be connected by an inexpensive transmission line having a low transmission capability. Even in this case, high-speed transmission of the write data pulse signal is possible without causing the waveform to be rounded.
[0086]
FIG. 16 is a block diagram showing a fifth embodiment of the magnetic recording / reproducing apparatus according to the present invention, wherein 2001 is a current format output circuit, 2002 is a current format input circuit, 2003 is a current format output circuit, and 2004 is a current format input circuit. This is a circuit, and portions corresponding to FIG. 29 are denoted by the same reference numerals, and redundant description will be omitted.
[0087]
In the figure, the R / W signal processing circuit 73 includes a current format output circuit 2001 and a current format input circuit 2004, and the R / W amplifier 72 includes a current format input circuit 2002 and a current format output circuit 2003. Is provided.
[0088]
In the case of transfer of the write data signal C5 from the R / W signal processing circuit 73 to the R / W amplifier 72, the write data C generated by the write data generation circuit 38 outputs the write data in the current format by the current format output circuit 2001. It is converted to C5, output from the R / W signal processing circuit 73, and sent to the R / W amplifier 72 via the film cable 2013. In the R / W amplifier 72, the write data C5 is received by the current format input circuit 2002, converted into write data S21 in voltage format, and supplied to the divide-by-2 circuit 12.
[0089]
When the read data signal D2 is transferred from the R / W amplifier 72 to the R / W signal processing circuit 73, the read data S22 output from the read buffer amplifier 14 is read by the current format output circuit 2003 in the current format read data D2. Is output from the R / W amplifier 72 and sent to the R / W signal processing circuit 73 via the film cable 2013. In the R / W signal processing circuit 73, the read data D 2 is received by the current format input circuit 2004, converted into voltage format read data D, and supplied to the read data reproduction circuit 9.
[0090]
FIG. 17 is a configuration diagram showing a specific example of a current format output circuit 2001 in the R / W signal processing circuit 73 and a current format input circuit 2002 in the R / W amplifier 72, where 2101 is a level converter, and I2101 is A current source, 2102 is a current switch, 2103 is a current-voltage converter, 2104 is a level converter, Q2101 to Q2104 are transistors, R2101 and R2102 are resistors, and VB2101 is a voltage source. Is attached.
[0091]
In the figure, a current format output circuit 2001 includes a level converter 2101 and a current switch 2102, and write data C from a write data generation circuit 38 (FIG. 16) is converted into a level in the current format output circuit 2001. After being level-converted by the amplifier 2101, it is converted into write data C5a and C5b in the current format by the current switch 2102 including the transistors Q2101 and Q2102 and the current source I2101, and the current format of the R / W amplifier 72 via the film cable 2013. It is supplied to the input circuit 2002.
[0092]
The current format input circuit 2002 includes a current-voltage converter 2103 and a level converter 2104. The current-voltage converter 2103 includes transistors Q2103, Q2104, resistors R2101, R2102, and a voltage source VB2101. ing.
[0093]
The write data signal C5 in the current format input to the R / W amplifier 72 via the film cable 2013 is input from the emitter terminal of the transistor Q2103 or Q2104, is converted to the voltage format by the resistor R2101 or R2102, and then is level-converted. The signal level is converted to a signal level suitable for the internal circuit by the device 2104. The potential of the emitter terminals of the transistors Q2103 and Q2104 serving as the input terminals of the current type input circuit 2002 can be suppressed to a change of several tens mV because the base terminal is connected to the voltage source VB2101. As a result, data can be transmitted with a small amplitude.
[0094]
The input impedance is an AC emitter resistance and is determined by the input current. For example, when the characteristic impedance of the film cable 2013 is set to 50Ω, the input current can be set to about 50Ω by setting the input current to 0.5 mA, and impedance matching can be achieved without adding a terminating resistor. Can be.
[0095]
FIG. 18 is a block diagram showing another specific example of the current format output circuit 2001 of the R / W signal processing circuit 73 in FIG. 16 together with the current format input circuit 2002 shown in FIG. 17, where 2203 is a register, and I2201 is The variable current source is the same as that shown in FIG.
[0096]
In this example, a current type output circuit 2201 uses a variable current source I 2201 as a current source in a current switch 2202, further includes a register 2203, and controls data of the register 2203 from the microcomputer 5. By setting with the signal S4, the output current value can be switched programmably.
[0097]
Thus, the current value of the write data C5 can be optimized according to the characteristic impedance of the intervening film cable 2013, and the impedance matching can be accurately performed without adding a terminating resistor.
[0098]
FIG. 19 is a configuration diagram showing still another specific example of the current format output circuit 2001 of the R / W signal processing circuit 73 in FIG. 16 together with the current format input circuit 2002 shown in FIG. 17, where R2401 and R2402 are resistors. , VB2401 are voltage sources, and portions corresponding to FIGS. 17 and 18 are denoted by the same reference numerals, and redundant description is omitted.
[0099]
In this figure, in this specific example, resistors R2401 and R2402 are added to the output side of a current switch 2402 as sending-end resistors, and these resistors R2401 and R2402 are connected to a voltage source VB2401. By matching the resistance values of the resistors R2401 and R2402 with the characteristic impedance of the transmission line, impedance matching on the transmitting end side can be achieved. Further, the bias value of the output current can be determined by the voltage of the voltage source VB2401, and adjustment is performed so that an optimal bias current can be obtained for the voltage source VB2101 of the current type input circuit 2002.
[0100]
FIG. 20 is a configuration diagram showing still another specific example of the current format output circuit 2001 of the R / W signal processing circuit 73 in FIG. 16 together with the current format input circuit 2002 shown in FIG. , I2502 are variable current sources, and R2501 is a resistor. The parts corresponding to those in FIGS. 17 and 18 are denoted by the same reference numerals, and redundant description is omitted.
[0101]
In this figure, in this specific example, the output terminal is short-circuited via a resistor R2501 as a transmitting end resistor, and variable current sources I2501 and I2502 are provided at the output terminal. It is controlled by.
[0102]
In this specific example, impedance matching can be achieved by adjusting the resistance R2501 to the characteristic impedance of the transmission line, and the output bias current can be controlled by the variable current sources I2501 and I2502.
[0103]
In the specific example shown in FIG. 19, it is necessary to adjust the voltage of the voltage source VB2401 depending on the voltage of the voltage source VB2101 of the connected current format input circuit 2002. However, in this specific example shown in FIG. The output bias current can be set without depending on the connection destination. Note that the resistor R2501 may be externally provided.
[0104]
FIG. 21 is a configuration diagram showing another specific example of the current format input circuit 2002 in FIG. 16, where R2601 and R2602 are variable resistors, 2603 is a current-to-voltage converter, and the portions corresponding to the above-mentioned drawings are the same. The sign is attached.
[0105]
In this figure, in this specific example, the resistors R2601 and R2602 in the current / voltage converter 2603 are variable resistors. When the output current of the current-type output circuit 2001 (FIG. 16) is largely changed, if the resistance value of the current-type input circuit 2002 is not appropriate, an operation failure such as saturation of the circuit occurs. This specific example can solve this problem by making the resistance values of the resistors R2601 and R2602 variable.
[0106]
Further, as another configuration of the current type input circuit 2002, the same problem can be solved by connecting diodes D2701 and D2702 in parallel with the resistors R2101 and R2102 as shown in FIG. In such a configuration, the output amplitude of the current-to-voltage converter 2703 is limited by the diodes D2701 and D2702, thereby preventing the circuit from being saturated.
[0107]
In this embodiment, the code format of the write data may be an RZ code or an NRZI code, and does not depend on the code format.
[0108]
Next, referring to FIG. 16, the operation of each circuit at the time of transfer of read data between the R / W signal processing circuit 73 and the R / W amplifier 72 will be described.
[0109]
The read data B read from the magnetic recording medium 1 by the magnetic head 10 is amplified by the read buffer amplifier 14 in the R / W amplifier 72 and then output as current-type read data D2 by the current-type output circuit 2003. , And supplied to the R / W signal processing circuit 73 via the film cable 2013. In the R / W signal processing circuit 73, the read data signal D 2 is converted from the current format to the voltage format by the current format input circuit 2004 and sent to the read data reproduction circuit 9.
[0110]
FIG. 23 is a configuration diagram showing a specific example of the current format output circuit 2003 and the current format input circuit 2004 in FIG. 16, where 2301 is a buffer amplifier, 2302 is a current output amplifier, 2303 is a current-voltage conversion circuit, 2304 Is a buffer amplifier, Q2301 to Q2304 are transistors, R2301 to R2303 are resistors, I2301 and I2302 are current sources, and VB2301 is a voltage source.
[0111]
In the figure, a current format output circuit 2003 includes a buffer amplifier 2301 and a current output amplifier 2302. The current output amplifier 2302 is realized by a gm amplifier including a transistor Q2301, a transistor Q2302, a resistor R2301, and current sources I2301 and 2302. be able to.
[0112]
The current format input circuit 2004 includes a current-voltage conversion circuit 2303 and a buffer amplifier 2304. The read data D2a and D2b sent in the current format are converted into the voltage format by the current / voltage conversion circuit 2303, and then sent to the read data reproduction circuit 9 via the buffer amplifier 2304. The current-voltage conversion circuit 2303 is composed of a grounded base circuit, like the current-voltage conversion circuit 2103 shown in FIG. 17, so that the potential change of the input terminal can be suppressed to several tens of mV, and the R / W amplifier The read data signal D2 between the R / W signal processing circuit 73 and the R / W signal processing circuit 73 can be transmitted with a small amplitude.
[0113]
FIG. 24 is a block diagram showing another specific example of the current format output circuit 2003 and the current format input circuit 2004 in FIG. 16, wherein I2901 and I2902 are variable current sources, R2901 is a resistor, and R2902 and R2903 are variable resistors. The same reference numerals are given to portions corresponding to those in FIG.
[0114]
In the figure, in a current format output circuit 2953, a resistor R2901 as a sending end resistor is added to the output side, and variable current sources I2901 and I2902 are used. By matching the resistance value of the resistor R2901 with the characteristic impedance of the film cable 2013 as the transmission path, impedance matching on the transmitting end side can be achieved. The bias value of the output current can be switched by the variable current sources I2901 and I2902, and adjustment can be performed so that an optimum bias current is obtained.
[0115]
In the current format input circuit 2954, variable resistors R2902 and R2903 are used as output load resistors of the current-voltage converter 2903. Thereby, the resistance values of the variable resistors R2902 and R2903 can be set to optimal values according to the output current value of the current format output circuit 2953, and the amplitude adjustment such as limiting the output amplitude to prevent the circuit from being saturated. Can be.
[0116]
【The invention's effect】
As described above, according to the present invention, it is possible to transfer a write data signal between an R / W amplifier and an R / W signal processing circuit, which are bottlenecks, at a low frequency, thereby increasing the speed of a magnetic recording / reproducing apparatus. Power consumption can be reduced.
[0117]
According to the present invention, the write data frequency can be reduced to に よ り by using an interleaved data format or an NRZI code format, and 現行 or less by combining both types with respect to the current system. And can sufficiently cope with high-speed data transfer of 20 MB / sec or more.
[0118]
Furthermore, according to the present invention, the transfer of a write data signal or a read data signal between the R / W amplifier and the R / W signal processing circuit, which is a bottleneck in high-speed operation, can be performed with a small amplitude, and the circuit can be operated at low speed. Power consumption can be reduced. For example, comparing the current consumption of the output circuit when using a 50Ω film cable, the power consumption of the output circuit when passing write data at the ECL level (0.8 V amplitude) of the related art is about 100 mW. According to the present invention, the output current can be reduced to 2 mA or less, and the power consumption can be reduced to about 20 mW and about 1/5 of the ECL level at about 50 mV amplitude.
[0119]
Furthermore, according to the present invention, the amount of noise can be reduced by transferring data with a small amplitude.
[0120]
Furthermore, according to the present invention, since impedance matching can be achieved without a terminating resistor, external components can be reduced and cost can be reduced. In particular, it is possible to save the space of the R / W amplifier IC having a small space for mounting components.
[0121]
Furthermore, according to the present invention, since the output current can be set programmably, the impedance matching can be finely adjusted, and the degree of freedom of the film cable to be used and the connection destination circuit is high, and the usability is improved.
[0122]
Furthermore, according to the present invention, since the output amplitude of the current type input circuit can be adjusted or limited, the saturation of the circuit can be prevented, and the setting range of the output current of the current type output circuit to be connected can be widened.
[0123]
Further, with the above effects, it is possible to improve the performance of the IC and the magnetic recording / reproducing apparatus, such as high speed, low power consumption, and miniaturization, and to reduce the cost.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a magnetic recording / reproducing apparatus according to the present invention.
FIG. 2 is a block diagram showing a specific example of an R / W amplifier and an R / W signal processing circuit in FIG. 1;
FIG. 3 is a block diagram showing a specific example of an interleave write data generation circuit in FIG. 2;
FIG. 4 is a diagram illustrating signals of respective units in FIG. 3;
FIG. 5 is a circuit configuration diagram showing a specific example of an interleave switch in FIG. 3;
FIG. 6 is a diagram illustrating signals of respective units in FIG. 5;
FIG. 7 is a diagram showing another specific example of the interleave system in the first embodiment shown in FIG. 1;
FIG. 8 is a block diagram showing another specific example of the interleave write data generation circuit in FIG. 2;
FIG. 9 is a block diagram showing a configuration of an R / W amplifier and an R / W signal processing circuit in a second embodiment of the magnetic recording / reproducing apparatus according to the present invention.
FIG. 10 is a diagram showing signals of respective units in FIG. 9;
FIG. 11 is a block diagram showing a modification of the second embodiment shown in FIG.
FIG. 12 is a block diagram showing a configuration of a main part of an R / W amplifier and an R / W signal processing circuit in a third embodiment of the magnetic recording / reproducing apparatus according to the present invention.
FIG. 13 is an operation explanatory diagram of the third embodiment shown in FIG.
FIG. 14 is a block diagram showing a configuration of an R / W amplifier and an R / W signal processing circuit in a fourth embodiment of the magnetic recording / reproducing apparatus according to the present invention.
FIG. 15 is a diagram showing signals of respective units in FIG. 14;
FIG. 16 is a block diagram showing a fifth embodiment of the magnetic recording / reproducing apparatus according to the present invention.
17 is a configuration diagram showing a specific example of a current format output circuit of the R / W signal processing circuit and a current format input circuit of the R / W amplifier in FIG. 16;
18 is a configuration diagram showing another specific example of the current format output circuit of the R / W signal processing circuit in FIG.
19 is a configuration diagram showing still another specific example of the current format output circuit of the R / W signal processing circuit in FIG.
20 is a configuration diagram illustrating still another specific example of the current format output circuit of the R / W signal processing circuit in FIG.
21 is a configuration diagram showing another specific example of the current format input circuit of the R / W amplifier in FIG.
22 is a configuration diagram showing still another specific example of the current format input circuit of the R / W amplifier in FIG.
23 is a configuration diagram showing a specific example of a current format input circuit of the R / W signal processing circuit and a current format output circuit of the R / W amplifier in FIG.
24 is a configuration diagram showing another specific example of the current format input circuit of the R / W signal processing circuit and the current format output circuit of the R / W amplifier in FIG.
FIG. 25 is a block diagram showing an example of a conventional magnetic recording / reproducing apparatus.
26 is a block diagram illustrating an example of an R / W amplifier and an R / W signal processing circuit in FIG.
FIG. 27 is a diagram showing an ideal waveform of write data transmitted from the R / W signal processing circuit in FIG. 26 to the R / W amplifier.
28 is a diagram showing an actual waveform of write data transmitted from the R / W signal processing circuit in FIG. 26 to the R / W amplifier.
FIG. 29 is a block diagram showing another example of a conventional magnetic recording / reproducing device.
[Explanation of symbols]
1 Magnetic recording medium
2 R / W amplifier
3 R / W signal processing circuit
4 Controller
5 microcomputer
6 Servo control circuit
7 I / F circuit
8 Interleaved data generation circuit
8a, 8a1, 8a2 Write correction circuit
8b encoding circuit
8c interleave switch
9 Read data reproduction circuit
10 Magnetic head
11 Read amplifier write driver
12 Divide-by-2 circuit
13 Read / Write Selector
14 Read buffer amplifier
15 Write current source circuit
16 Synthesis circuit
17 Buffer
18 Write data generation circuit
19 Divide-by-2 circuit
20 Encoding circuit
21 Write correction circuit
22 Differential buffer
23 Differential receiver
24,25 frequency divider circuit
26 Synthesis circuit
2001, 2003 Current type output circuit
2002, 2004 Current type input circuit
2013 Film cable
2101 Level translator
2102 Current switch
2103 Current-voltage converter
2104 Level Translator
2203 register
2301 buffer amplifier
2302 Current output amplifier
2303 Current-voltage converter
2304 buffer amplifier

Claims (6)

In a magnetic recording / reproducing apparatus for transmitting data between a read / write signal processing circuit and a read / write amplifier and recording / reproducing the data on / from a magnetic recording medium by the read / write amplifier,
The read / write signal processing circuit is provided with an interleave write data generation circuit for generating write pulse signals having an interleave relationship from each other from a data pulse signal;
A combination circuit for combining the write pulse signal and restoring the original data pulse signal in the read / write amplifier;
The read / write signal processing circuit is connected to the read / write amplifier via a plurality of signal lines, and each of the interleaved write pulse signals is transmitted from the read / write signal processing circuit to the read / write amplifier. Transmitted using the plurality of signal lines ,
A signal transmitted between the read / write amplifier and the read / write signal processing circuit is a differential signal . In claim 1,
A magnetic recording / reproducing apparatus according to claim 1, wherein a signal transmitted between said read / write amplifier and said read / write signal processing circuit is an NRZI code format signal. In a magnetic recording / reproducing apparatus for transmitting data between a read / write signal processing circuit and a read / write amplifier and recording / reproducing the data on / from a magnetic recording medium by the read / write amplifier,
The read / write signal processing circuit includes a write data generation circuit, and a circuit for multiplying an output cycle of the write data generation circuit by n times,
A differential buffer is provided on an output side of a circuit for multiplying the cycle of the read / write signal processing circuit by n;
A differential receiver for receiving the output of the differential buffer in the read / write amplifier;
A magnetic recording / reproducing apparatus , wherein a differential signal is transmitted between the read / write signal processing circuit and the read / write amplifier . In claim 3,
The magnetic recording / reproducing apparatus according to claim 1, wherein an output of the circuit for multiplying the cycle by n transmitted between the read / write amplifier and the read / write signal processing circuit is a signal in an NRZI code format . In a magnetic recording / reproducing apparatus for transmitting data between a read / write signal processing circuit and a read / write amplifier and recording / reproducing the data on / from a magnetic recording medium by the read / write amplifier,
An interleave write data generation circuit for generating, from the data pulse signal, write pulse signals having an interleaved relationship with each other, a read / write signal processing circuit comprising: an n-fold cycle of the write pulse signal output from the interleave write data generation circuit; And two frequency divider circuits,
A combining circuit for combining the output signals of the two circuits for multiplying the period by n to restore the original data pulse signal;
The read / write signal processing circuit is connected to the read / write amplifier by a plurality of signal lines, and each of output signals of the two circuits for multiplying the cycle by n is used to output the read / write signal from the read / write signal processing circuit. Transmitted to the write amplifier using the plurality of signal lines,
A signal transmitted between the read / write amplifier and the read / write signal processing circuit is a differential signal . In claim 5,
A magnetic recording / reproducing apparatus according to claim 1, wherein a signal transmitted between said read / write amplifier and said read / write signal processing circuit is an NRZI code format signal .

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