JP3599873B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a technology for highly integrating a semiconductor integrated circuit. The present invention proposes a semiconductor device suitable for high integration, particularly for a field-effect element, and describes a manufacturing method thereof. The semiconductor device according to the present invention is used particularly for a nonvolatile semiconductor memory device having a floating gate.
[0002]
[Prior art]
Conventional semiconductor devices are formed in a planar manner. For example, in the example of a field-effect element (MOS (or MIS) field-effect transistor (FET)), a structure in which a source, a drain, and a channel are arranged roughly in a plane and a drain current flows in parallel to a substrate. And it was. However, in such a planar (planar type) element, reduction of the element area is naturally limited. For this reason, in order to achieve higher integration, studies have been made on a technique of forming a planar type element in multiple layers and a non-planar element structure itself. As an example of the latter, there is a vertical channel type MOSFET proposed by the present inventors (JP-A-6-13627). In this device, a drain is arranged above (or below) a source so that a drain current flows substantially vertically. With such a structure, high integration of the element can be achieved.
[0003]
[Problems to be solved by the invention]
The above-mentioned Japanese Patent Application Laid-Open No. 6-13627 relates to a nonvolatile semiconductor memory. That is, the feature is that the floating gate and the control gate are formed on the side surface of the convex portion formed on the semiconductor substrate by an anisotropic etching method. However, only the basic element structure was shown. An object of the present invention is to provide a more optimal structure and a manufacturing method for an element having such a structure, and to disclose a preferable mode also for a NAND nonvolatile memory.
[0004]
[Means for Solving the Problems]
The method for manufacturing a semiconductor device according to the present invention includes the following steps.
(1) a step of forming a projection by etching a semiconductor substrate; (2) a step of forming an insulating film on an exposed surface of the semiconductor substrate; (3) a step of forming a first conductive film; and (4) a step of forming a first conductive film. Forming a film to be a floating gate on the side surface of the projection by etching the first conductive film by an anisotropic etching method.
(5) Step of forming an insulating film on the surface of the floating gate (6) Step of selectively oxidizing the semiconductor substrate and / or the first conductive film to obtain an oxide for element isolation (7) Second (8) Step of selectively forming a mask on the second conductive film (9) Etching the second conductive film by an anisotropic etching method Forming a control gate on the side surface of the portion by covering the floating gate and, at the same time, obtaining a gate of a planar type MOS transistor.
Here, step (6) may be between steps (3) and (4) or between steps (4) and (5). The step of doping the impurity imparting one conductivity type (doping step) is preferably performed after step (9). By doing so, the source and drain (impurity region) of the planar MOSFET can be formed in a self-aligned manner with respect to the gate. Furthermore, in order to implement multilayer wiring in the same manner as in the known technique, an interlayer insulator may be formed after step (9) to form an upper layer wiring.
In the step (6), a so-called local oxidation method (LOCOS) may be used, or a technology developed therefrom may be used. As a method of forming the insulating film in the steps (2) and (5), a thermal oxidation method, a thermal nitridation method, or a vapor deposition method may be used.
[0007]
The first conductive film formed in the step (3) is a film that becomes a floating gate after the etching step (4). Generally, as a result of the anisotropic etching in the step (4), a continuous first conductive film is left on one side surface of one projection.
However, when a plurality of elements are formed on one side surface, the floating gate needs to be separated (insulated) for each element. The step (6) is for simultaneously forming the oxide for element isolation and isolating the floating gate for each element.
[0008]
Although it has been described above that the step (6) may be between the steps (3) and (4) or between the steps (4) and (5), each case will be briefly described below. First, in the case between the steps (3) and (4), the first film is divided first by the oxide for element isolation, and then formed on the side surface of the projection by the step (4). As a result, a floating gate divided for each element can be obtained as a result.
In addition, when the step is between the steps (4) and (5), the oxidation mask (usually silicon nitride) is in direct contact with the semiconductor substrate and the first conductive film in the selective oxidation, so that there is a danger of peeling. There is, but not impossible. For this reason, the position of step (6) may be between steps (3) and (4) or between steps (4) and (5).
[0009]
The above is the description of the general manufacturing method of the present invention. Next, a special case will be described. When applying the manufacturing process of the present invention to the configuration of the NAND nonvolatile memory which is a promising application example of the present invention, attention should be paid to the element isolation technology. JP-A-6-13627 is not limited to a NAND type circuit. The NAND type circuit can reduce the number of contacts with the upper layer wiring per memory cell (bit line in the case of NAND type, and ground line if necessary) as compared with the conventional matrix type circuit.
[0010]
In a normal NAND circuit, the unit memory block is composed of four or more, preferably eight or more memory cells (memory transistors), which are connected in series. Each block is provided with at least two select transistors with a memory cell interposed therebetween. The number of contacts with the bit line is one for each source of each select transistor, that is, two contacts for each block. By sharing a contact with an adjacent block, one contact can be used for each block. When one block is made up of four or eight memory cells, the number of contacts is 1/4 or 1/8 per memory cell.
[0011]
In contrast, a typical matrix memory circuit requires at least one contact for each memory cell. Such a large number of contacts is disadvantageous from the viewpoint of high integration of a circuit.
In order to apply the present invention to a NAND type circuit, first, in step (6), it is required to form a plurality of oxides for element isolation in a direction substantially perpendicular to the word line. Of course, in the step (1), it is necessary to form a groove in a direction parallel to the word line, that is, to obtain a linear projection.
[0012]
Element isolation is not required between serial memory cells or select transistors, but is required between transistors that are not. Therefore, the insulator for element isolation in the step (6) is formed at the same interval for each transistor row. In the present invention, since two elements are formed on the side surface of one linear projection, two word lines are formed for one linear projection. Since the word line and the transistor row intersect, the insulator for element isolation and the linear projection (or groove) intersect.
[0013]
Next, in the NAND type circuit, a selection transistor (a transistor having a normal structure without a floating gate) is required in addition to the memory cell. In the present invention, a planar MOSFET may be used as the selection transistor. Since the first conductive film on the portion where the planar MOSFET is formed is etched in the step (4), all the planar MOSFETs become ordinary transistors (transistors without a floating gate).
[0014]
The impurity region of the select transistor is required to be in contact with a bit line or a ground line. For this reason, it is more advantageous to form the contact hole when the select transistor is provided on the surface of the projection than at the groove. The fabrication of the planar MOSFET may be performed according to a method described later.
By making the selection transistor a planar transistor, it is not necessary to form a contact at the projection where the vertical channel element is formed. This is advantageous in the following points. That is, the width of the convex portion that does not require such a contact may be designed according to the minimum design rule. If you need contact. Its width will be required at least twice the minimum design rule.
[0015]
In the case where a semiconductor device is manufactured by using the present invention, in some cases, in a peripheral circuit or the like, in addition to a select transistor, some elements may be required to be formed by a conventional planar type. Further, in principle, in the present invention, since the second conductive film other than the side surface of the convex portion is entirely etched, it is difficult to form a contact between the control gate and the upper layer wiring as it is. Therefore, step (8) is required for such a purpose.
[0016]
After the step, if the anisotropic etching is performed in step (9), the portion where the mask is formed is not etched. That is, as a result of the step (9), the second conductive film other than the side surface of the convex portion or the portion of the mask is etched. The gate / wiring of the planar type MOSFET and the contact formation portion at the last end of the control gate are portions to be masked.
[0017]
The source and drain of the planar MOSFET may be formed after the gate is formed, that is, after the step (9). In the doping step, the following conditions must be satisfied between the effective depth δ of the source and the drain and the etching depth (groove depth) d in the step (1).
d> δ
If this is not satisfied, the impurity will be diffused below the convex portion, and a vertical channel cannot be substantially formed.
[0018]
As described above, one photolithography step is added to manufacture a planar MOSFET other than the vertical channel element. In the step (4), the first conductive film formed on the plane is entirely etched unless a mask is provided, so that a floating gate cannot be formed on the planar MOSFET.
[0019]
【Example】
Embodiment 1 FIG. 1 shows an embodiment of the present invention. Example 1 This example is for describing the basics of manufacturing a semiconductor device such as a nonvolatile memory device using the present invention. FIG. 1 shows fabrication cross sections of three typical parts. That is, from the left, a portion where a planar element is provided, a portion where an oxide for element isolation is provided, and a portion where a vertical channel element is provided.
[0020]
First, as shown in FIG. 1A, a plurality of grooves (or concave portions) 13 are formed on a semiconductor substrate 11, and convex portions 12 are formed. The height of the protrusion 12 is the same as the surface of the original semiconductor substrate. The depth of the groove 13 has a great relationship with the channel length of the vertical channel element to be formed. In the figure, in order to make the boundary with the semiconductor substrate easy to understand, the boundary portion and the surface portion are shown with diagonal lines, but this does not mean that the composition, conductivity, etc. of this portion are different from other portions. Absent. The above steps correspond to step (1).
Next, an oxide film 14 is formed on the semiconductor surface formed as described above by a known method such as thermal oxidation (corresponding to step (2)). (Fig. 1 (A))
[0021]
Then, the first conductive film 15 is formed using a semiconductor material or the like by a known film forming technique (corresponding to step (3)). In this case, it is necessary to adopt a film forming technique having a high covering property such that a film is sufficiently formed also on the side surface of the convex portion. Further, the thickness of the coating is preferably １ ／ to 溝 of the depth of the groove 13. (FIG. 1 (B))
Next, the coating 15 is etched by a known anisotropic etching method (corresponding to step (4)). As a result, the coating 16 to be a floating gate is left only on the side surface of the projection, and the other portions are etched. This coating 16 is continuous along the groove. (Fig. 1 (C))
[0022]
Further, an insulating film 17 is formed on the surface of the film 16 by a known film forming technique such as a thermal oxidation method (corresponding to step (5)). (Fig. 1 (D))
Next, a selective oxidation step (corresponding to step (6)) is performed. In this case, first, a silicon nitride film is used as an oxidation resistant mask. That is, as shown in the figure, the oxidation-resistant mask 18 is formed except for a portion where an oxide is formed (that is, a portion where an element is formed on a semiconductor). (FIG. 1 (E))
[0023]
Thereafter, a thick oxide film 19 is formed on the unmasked portion by a thermal oxidation method, preferably a steam thermal oxidation method. After the oxidation step, the oxidation-resistant mask 18 is etched, and the selective oxidation step ends. (FIG. 1 (F))
[0024]
Then, the second conductive film 20 is formed using a semiconductor material or a metal material by a known film forming technique (corresponding to step (7)). Also in this case, it is necessary to employ a technique excellent in step coverage, and the thickness of the film is preferably 被膜 to の of the depth of the groove 13. Then, a mask 21 is selectively formed on the second conductive film 20 by a known photolithography method (corresponding to step (8)). The mask is formed in the portion where the wiring is formed using the gate of the planar type MOS transistor and the second conductive film. (Fig. 1 (G))
[0025]
Further, the second conductive film 20 is etched by a known anisotropic etching method (corresponding to step (9)). As a result, the control gate 23 is left on the side surface of the projection, and at the same time, the gate of the planar type MOS transistor is formed. Other parts are etched. In particular, the control gate 23 is formed on the floating gate 16 as is apparent in the right part of the figure, and the control gate 23 is formed on the side surface of the projection also in the part without the floating gate as in the center part of the figure. It is formed. That is, the control gate 23 is formed along the groove 13. (Fig. 1 (H))
[0026]
Further, an impurity region is formed by a known impurity diffusion technique such as an ion implantation method. As a result, an impurity region 25 is formed on the top of the protrusion 12 and an impurity region 26 is formed on the bottom of the groove 13. Further, an impurity region 24 of the planar type MOS transistor is also formed. (Fig. 1 (I))
Thus, a semiconductor device having a memory cell of a nonvolatile memory device can be formed.
[0027]
Embodiment 2 The present embodiment relates to a manufacturing process and a circuit configuration of a NAND nonvolatile memory device using the present invention. This embodiment will be described with reference to FIGS. 2A and 2B show a main part of the semiconductor device of the present embodiment viewed from above in the order of manufacturing steps. A rectangular portion surrounded by a dotted line in the figure is a unit memory block. In this embodiment, the unit memory block includes two selection transistors and four memory cells. FIGS. 3 and 4 show cross sections of the portions indicated by XX ′ and YY ′ in FIG. 2 in the order of manufacturing steps. FIG. 6 shows an example of the arrangement of bit lines and ground lines in this embodiment, and FIG. 5 is a circuit diagram corresponding thereto. Hereinafter, description will be made in the order of steps.
[0028]
First, a groove 33 is formed in a semiconductor substrate 31 in the same manner as in the first embodiment, and a protrusion 32 is obtained. Further, an oxide film 34 is formed on the semiconductor surface by a known method such as thermal oxidation. In FIG. 2, only the portion having the same height as the original semiconductor substrate is defined as a hatched portion. In FIGS. 3 and 4, the boundary portion and the surface portion with the semiconductor substrate are indicated by oblique lines for the same reason as in FIG. (FIG. 2 (A), FIG. 3 (A), FIG. 4 (A))
[0029]
Then, a first conductive film is formed using a semiconductor material or the like by a known film forming technique, and is etched by a known anisotropic etching method in the same manner as in Example 1. The coating 36 to be a floating gate is obtained only on the side surfaces of the projections. This coating 36 is continuous along the groove 33. (FIG. 3 (B), FIG. 4 (B))
[0030]
Further, an insulating film is formed on the surface of the film 36 by a known film forming technique such as a thermal oxidation method. Then, as in the first embodiment, selective oxidation is performed using a silicon nitride film as an oxidation resistant mask. That is, as shown in FIG. 2B, an oxidation-resistant mask 38 is formed perpendicular to the groove 33. (FIG. 2 (B), FIG. 3 (C), FIG. 4 (C))
[0031]
Thereafter, a thick oxide film 39 is formed on the unmasked portion by a thermal oxidation method, preferably a steam thermal oxidation method. An oxide is not formed in the XX ′ section (FIG. 3) because the mask is masked, but an oxide is formed in the YY ′ section (FIG. 4). Although not evident in FIG. 2, this oxide 39 is also formed in the trench 33, as is clear from FIG. That is, in FIG. 2, the upper and lower elements can be separated. In addition, by this oxidation step, the coating 36 that has been continuous along the groove 33 until then is cut. (FIG. 2 (C), FIG. 3 (D), FIG. 4 (D))
[0032]
Next, the second conductive film 40 is formed using a semiconductor material or a metal material by a known film forming technique. Then, masks 41a and 41b are selectively formed on the second conductive film 40 by a known photolithography method. The mask is formed in the portion where the gate of the select transistor (planar MOS transistor) is formed. (FIG. 3 (E), FIG. 4 (E))
[0033]
Further, the second conductive film 40 is etched by a known anisotropic etching method. As a result, the control gates 43a to 43d are left on the side surfaces of the projections, and the gates 42a and 42b of the selection transistor are formed. Other parts are etched. (FIG. 3 (F), FIG. 4 (F))
Then, an impurity region is formed by a known impurity diffusion technique such as an ion implantation method. As a result, impurity regions 45a to 45d and 44a, 44b are formed at the top of the convex portion, and impurity regions 46a, 46b are formed at the bottom of each groove. (Fig. 3 (G))
[0034]
Thereafter, an interlayer insulator 47 is formed by using a known technique, and contact holes 48a and 48b communicating with the impurity regions 44a and 44b are formed in the interlayer insulator 47, thereby forming an upper layer wiring (eg, a ground line) such as a bit line or a ground line. 49a and 49b are formed. FIG. 2D shows the locations where the contact holes are formed. Thus, a selection transistor and a memory cell can be formed. (FIG. 2 (D), FIG. 3 (H), FIG. 4 (G))
[0035]
There are two possible methods for arranging the upper wiring such as the bit line and the ground line. First, as shown in FIG. 6A, a method of arranging an upper layer wiring in parallel with and above the element isolation oxide 39. The circuit diagram is shown in FIG. However, according to this method, as shown in the drawing, the distance between the adjacent upper wiring and the other upper wiring cannot be set to be equal to or less than the minimum design rule due to the fear of contact with another upper wiring. Therefore, it is difficult to form a contact completely covering the contact hole. (FIG. 5 (A), FIG. 6 (A))
[0036]
In order to solve this problem, the upper-layer wiring may be arranged obliquely as shown in FIG. A circuit diagram in this case is shown in FIG. Alternatively, the upper layer wiring may be arranged in a zigzag manner. Thus, the wiring can be arranged so as to completely cover the contact hole. (FIG. 5 (B), FIG. 6 (B))
[0037]
Thus, a nonvolatile memory device can be formed.
In the above example, the ground line is formed in parallel with the bit line. However, the ground line may be formed as an impurity region formed on the substrate.
That is, when an oxide for element isolation is formed, as shown in FIG. 7, an impurity region 44c is formed in one of regions where a planar type MOS transistor is formed so as to extend from the top to the bottom of the drawing. What should I do?
[0038]
FIG. 7 shows a state in which the gate, control gate, and the like have been removed from the device after completion of doping. The impurity region 44d corresponds to the impurity region 44b in FIG. A contact is provided. On the other hand, no contact is provided for each memory block in the impurity region 44c, and the impurity region extending from the top to the bottom of the drawing becomes a ground line. By doing so, the resistance of the ground wire increases, but the number of contacts can be halved. (FIG. 7)
[0039]
【The invention's effect】
According to the present invention, a highly integrated semiconductor device can be manufactured. The present invention provides a remarkable technical advance especially in the integration of a NAND type nonvolatile memory device. Thus, the present invention is an industrially useful invention.
[Brief description of the drawings]
FIG. 1 is a diagram showing a manufacturing process of a semiconductor device of Example 1.
FIG. 2 shows a manufacturing process of the semiconductor device of Example 2. (View from above)
FIG. 3 shows a manufacturing process of the semiconductor device of Example 2. (Cross section)
FIG. 4 shows a manufacturing process of the semiconductor device of Example 2. (Cross section)
FIG. 5 is a circuit diagram of a semiconductor device according to a second embodiment.
FIG. 6 is a diagram illustrating an arrangement of upper wiring layers of the semiconductor device according to the second embodiment;
FIG. 7 is a view showing the arrangement of element isolation insulators, impurity regions, and contacts of the semiconductor device of Example 2.
[Explanation of symbols]
11 ... semiconductor substrate 12 ... convex part 13 ... groove (or concave part)
14 ... insulator film 15 ... first conductive film 16 ... etched first conductive film 17 ... insulator film 18 ... oxidation resistant mask 19 ... Element isolation oxide 20 Second conductive film 21 Mask 22 Planar MOS transistor gate 23 Control gate 24, 25, 26 Impurity region

Claims (8)

Forming a protrusion on the semiconductor substrate,
Forming a first insulating film on the surface of the semiconductor substrate;
Forming a first conductive coating on the surface of the first insulating coating;
With respect to the first conductive coating, have rows anisotropic etching, it is left a conductive coating on the convex side surface,
Forming a second insulating film on the surface of the conductive film on the side surface of the convex portion;
Forming a first mask covering a portion where the planar type MOS transistor is formed and the convex portion;
Forming an oxide for element isolation in a portion not covered with the first mask;
Removing the first mask;
Forming a second conductive coating,
Forming a second mask on the second conductive film on a portion to be a gate electrode of a planar type MOS transistor;
With respect to the second conductive coating, it has rows anisotropic etching, at the same time to form a control gate via the second insulating film on the side surface of the conductive film of the convex portion side surface, the planar Forming the gate electrode of the MOS transistor,
A method for manufacturing a semiconductor device, comprising introducing an impurity imparting one conductivity type into the semiconductor substrate. Forming a protrusion on the semiconductor substrate,
Forming a first insulating film on the surface of the semiconductor substrate;
Forming a first conductive coating on the surface of the first insulating coating;
Selectively oxidize to form oxides for device isolation,
With respect to the first conductive coating, have rows anisotropic etching, it is left a conductive coating on the convex side surface,
Forming a second insulating film on the surface of the conductive film on the side surface of the convex portion;
Forming a second conductive coating,
Forming a second mask on the second conductive film on a portion to be a gate electrode of a planar type MOS transistor;
With respect to the second conductive coating, it has rows anisotropic etching, at the same time to form a control gate via the second insulating film on the side surface of the conductive film of the convex portion side surface, the planar Forming the gate electrode of the MOS transistor,
A method for manufacturing a semiconductor device, comprising introducing an impurity imparting one conductivity type into the semiconductor substrate. Forming a protrusion on the semiconductor substrate,
Forming a first insulating film on the surface of the semiconductor substrate;
Forming a first conductive coating on the surface of the first insulating coating;
With respect to the first conductive coating, have rows anisotropic etching, it is left a conductive coating on the convex side surface,
Selectively oxidize to form oxides for device isolation,
Forming a second insulating film on the surface of the conductive film on the side surface of the convex portion;
Forming a second conductive coating,
Forming a second mask on the second conductive film on a portion to be a gate electrode of a planar type MOS transistor;
With respect to the second conductive coating, it has rows anisotropic etching, at the same time to form a control gate via the second insulating film on the side surface of the conductive film of the convex portion side surface, the planar Forming the gate electrode of the MOS transistor,
A method for manufacturing a semiconductor device, comprising introducing an impurity imparting one conductivity type into the semiconductor substrate. Forming a protrusion on the semiconductor substrate,
Forming a first insulating film on the surface of the semiconductor substrate;
Forming a first conductive coating on the surface of the first insulating coating;
Anisotropic etching is performed on the first conductive film to leave a conductive film on the side surface of the convex portion,
Forming a second insulating film on the surface of the conductive film on the side surface of the convex portion;
Selectively oxidize to form oxides for device isolation,
Forming a second conductive coating,
Forming a second mask on the second conductive film on a portion to be a gate electrode of a planar type MOS transistor;
Anisotropic etching is performed on the second conductive film to form a control gate on the side surface of the conductive film on the side surface of the convex portion via the second insulating film. Forming the gate electrode of the transistor,
A method for manufacturing a semiconductor device, comprising introducing an impurity imparting one conductivity type into the semiconductor substrate. Forming a protrusion on the semiconductor substrate,
Forming an insulating coating on the semiconductor substrate surface,
Forming a first conductive coating,
Anisotropically etching the first conductive film to form a film to be a floating gate on a side surface of the projection;
Forming an insulating coating on the surface of the floating gate,
Selectively oxidize to form oxides for device isolation,
Forming a second conductive coating,
Selectively forming a mask on the second conductive film,
Anisotropically etching the second conductive film to form a control gate and a gate electrode of a planar type MOS transistor on a side surface of the convex portion so as to cover the floating gate;
A method for manufacturing a semiconductor device, comprising introducing an impurity imparting one conductivity type into the semiconductor substrate. Forming a protrusion on the semiconductor substrate,
Forming an insulating coating on the semiconductor substrate surface,
Forming a first conductive coating,
Selectively oxidize to form oxides for device isolation,
Anisotropically etching the first conductive film to form a film to be a floating gate on a side surface of the projection;
Forming an insulating coating on the surface of the floating gate,
Forming a second conductive coating,
Selectively forming a mask on the second conductive film,
Anisotropically etching the second conductive film to form a control gate and a gate electrode of a planar type MOS transistor on the side surface of the projection, covering the floating gate;
A method for manufacturing a semiconductor device, comprising introducing an impurity imparting one conductivity type into the semiconductor substrate. Forming a protrusion on the semiconductor substrate,
Forming an insulating coating on the semiconductor substrate surface,
Forming a first conductive coating,
Anisotropically etching the first conductive film to form a film to be a floating gate on a side surface of the projection;
Selectively oxidize to form oxides for device isolation,
Forming an insulating coating on the surface of the floating gate,
Forming a second conductive coating,
Selectively forming a mask on the second conductive film,
Anisotropically etching the second conductive film to form a control gate and a gate electrode of a planar type MOS transistor on a side surface of the convex portion so as to cover the floating gate;
A method for manufacturing a semiconductor device, comprising introducing an impurity imparting one conductivity type into the semiconductor substrate. In any one of claims 1 to 7,
The method for manufacturing a semiconductor device, wherein the planar type MOS transistor is provided on an upper surface of a convex portion of the semiconductor substrate.

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