JP3595328B1 - Voltage conversion circuit - Google Patents

Abstract

An inexpensive voltage conversion circuit that is small and lightweight and does not generate harmful electromagnetic wave noise is provided.
Kind Code: A1 Four devices are connected between n holding capacitors C1 (1) connected in series for holding power and n−1 transfer capacitors C2 (3) for transferring power. A DC power supply (8) is connected to any two of the terminals TP (2) of the holding capacitor C1 (1) as a power supply source, and the terminal TP (2) At least one load (9) is connected between at least two arbitrary terminals, and the four signals are controlled by a control signal φ1 constituted by a square wave whose ON time is set shorter than OFF time. And two of the four switches are opened and closed by a control signal .phi.2 having a 180 degree phase relationship with .phi.1. Then, switch off the switch Re configured by MOSFET (10).
[Selection diagram] Fig. 1

Description

  The present invention relates to a voltage conversion circuit that can freely perform DC voltage step-up, step-down, and polarity conversion.

Conventionally, a so-called switching power supply has been used as a method of increasing, decreasing, and converting the DC voltage. The switching power supply converts the input DC voltage into an AC voltage once by performing high-speed switching with a switching element such as a power transistor, and then inputs this into a high-frequency transformer, converts it into a desired AC voltage, and then rectifies it. It is configured to return to DC voltage. By appropriately selecting the turn ratio between the primary winding and the secondary winding of the high-frequency transformer, the input DC voltage can be freely boosted, stepped down, and converted in polarity.
JP-A-5-64448

However, the conventional voltage conversion circuit has the following problems.
That is, the switching power supply needs to increase the switching frequency as much as possible in order to improve the transmission efficiency of the high-frequency transformer. Since the input DC voltage is switched at a high frequency of 100 kHz or more, a large high-frequency noise is generated. Occurs on the line. Since the high-frequency noise is emitted not only in the power output direction but also in the input direction, it is indispensable to insert a line filter on both the input and the output in order to block this. Further, the high-frequency transformer transmits electric power using a magnetic induction phenomenon, but has a disadvantage that magnetism easily leaks into the air. Therefore, the high-frequency transformer generates electromagnetic noise toward the air. The electromagnetic wave noise is known to cause malfunction in other adjacent circuits or is harmful to the human body.In order to prevent this, in the related art, it is necessary to completely shield the transformer with a magnetic housing. . These are major obstacles to reducing the size, weight, and cost of the voltage conversion circuit.

  SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide an inexpensive voltage conversion circuit that is small and lightweight and does not generate harmful electromagnetic noise.

  The present invention provides n (n is a natural number of 2 or more) holding capacitors C1 (1) (C11, C12... C1n) connected in series for holding power, and the holding capacitor C1 ( N) terminals TP (2) (TP1, TP2,... TPn, TPn + 1) provided at both ends of (1) and n-1 transfer capacitors C2 (3) for transferring power. ) (C21, C22,... C2n-1) and n-1 switches connected between minus terminals corresponding to the respective transfer capacitors C2 (3) and TP1 of the terminal TP (2). SA (4) (SA1, SA2,..., SAn-1), and n-th minus terminals of the transfer capacitor C2 (3) and n + 1-th of the terminal TP (2). n-1 Switch SB (5) (SB1, SB2,..., SBn-1) and nth positive terminal of the transfer capacitor C2 (3) and n + 1th terminal of the terminal TP (2). N-1 switches SC (6) (SC1, SC2,... SCn-1), n-th positive terminals of the transfer capacitor C2 (3), and n + 2-th terminals of the terminal TP (2). Between the n-1 switches SD (7) (SD1, SD2,..., SDn-1) respectively connected between the terminal TP (2) and the terminal TP (2). The connected DC power supply (8), at least one load (9) connected between at least two of the terminals TP (2), and the ON time is set shorter than the OFF time. Control composed of square waves A gate control circuit (11) which is a control circuit for generating a control signal .phi.2 having a phase relationship of 180 degrees with the signal .phi.1 and the control signal .phi.1, and the switch SA (4) corresponding to the control signal .phi.1; A voltage conversion circuit, which opens and closes a switch SC (6) and opens and closes the switches SB (5) and SD (7) in response to the control signal φ2.

  A second aspect of the present invention is a voltage conversion circuit, wherein each of the switches SA (4), SB (5), SC (6) and SD (7) is constituted by a MOSFET (10).

  According to the present invention, since no high-frequency transformer is used, large high-frequency noise does not occur on the circuit line, and there is no need to insert a line filter. In addition, since power is transmitted without using the magnetic induction phenomenon at all, there is no generation of electromagnetic noise, so that other adjacent circuits do not malfunction and are harmless to human bodies and safe. Further, the voltage conversion circuit according to the present invention does not need to be completely shielded by a magnetic housing, and thus has a great effect in reducing the size, weight, and cost.

  Hereinafter, embodiments of the present invention will be described.

  FIG. 1 shows a first embodiment of the voltage conversion circuit according to the present invention. In FIG. 1, n holding capacitors C1 (1) are connected in series (n is a natural number of 2 or more) in order to hold power and generate a multi-valued voltage, and C11, C12,. And the name. At each end of the holding capacitor C1 (1), n + 1 terminals TP (2) are provided for inputting or extracting power, and are sequentially named TP1, TP2,... TPn, TPn + 1. Is attached. In order to sequentially transmit power to the holding capacitor C1 (1), n-1 transfer capacitors C2 (3) are provided, and are named C21, C22,..., C2n-1.

  Here, as the material of the holding capacitor C1 (1) and the transmission capacitor C2 (3), for example, an aluminum electrolytic capacitor or the like may be used. Preferably, but practically, it is preferable to select between several hundred μF and several thousand μF.

  In order to sequentially transmit power from the transfer capacitor C2 (3) to the holding capacitor (1), four switches are provided for each transfer capacitor C2 (3). First, as a first switch, there are provided n-1 switches SA (4) for opening and closing between a terminal TP1 at the lowermost end of the holding capacitor (1) and a negative terminal of the transfer capacitor C2 (3). , And SAn-1 in that order.

  As a second switch, n-1 switches SB (5) are provided between each of the n-th negative terminals of the transfer capacitor C2 (3) and the n + 1-th terminal of the terminal TP (2). .., And SBn-1.

  As a third switch, n-1 switches SC (6) are provided between each of the n-th positive terminals of the transfer capacitor C2 (3) and the n + 1-th terminal of the terminal TP (2). , And SCn-1 in order.

  As a fourth switch, n-1 switches SD (7) are provided between each of the n-th positive terminals of the transfer capacitor C2 (3) and the n + 2th terminal of the terminal TP (2). , And are sequentially named SD1, SD2,..., SDn-1.

  The first switch SA (4) and the third switch SC (6) are formed by a square wave generated by the gate control circuit (11), which is set to be on for a shorter time than for off. The second switch SB (5) and the fourth switch SD (7) are simultaneously opened / closed in response to the control signal φ1 and correspond to the control signal φ2 having a 180 ° phase relation with the control signal φ1. It is opened and closed at the same time.

  Here, the switches SA (4), SB (5), SC (6), SD (7) are each constituted by a MOSFET (10), and the control signal φ1 or the control signal φ1 is connected to the gate terminal of each MOSFET (10). By inputting φ2, the current flowing between the source terminal and the drain terminal of each of the MOSFETs (10) can be turned ON / OFF at a high speed correspondingly.

  As the performance of the MOSFET (10), the power passing efficiency can be improved by selecting a power MOSFET having a small ON resistance, a large electric breakdown voltage between the source and drain terminals, and a high switching speed.

FIG. 5 shows a time chart of the control signals φ1 and φ2 generated by the gate control circuit (11). The control signals φ1 and φ2 are respectively continuous and are turned ON once each during the repetition period T. However, φ1 and φ2 have a 180 ° phase relation, and φ2 is OFF while φ1 is ON. , Φ1 are OFF while φ2 is ON. Here, the fact that a 180 ° phase relation is established means that the rising waveform portions of φφ1 and φ2 are shifted by T / 2 on the time chart by turning ON / OFF complementarily to each other. is there.

  Further, both the control signals φ1 and φ2 are set to be shorter in the ON time than in the OFF time. That is, as shown in FIG. 5, the time from the moment when φ1 is turned off to the time when φ2 is turned on and the time from the moment when φ2 is turned off to the time when φ1 is turned on are determined by the interval of ΔT by the pulse width expansion circuit. Are opened so that φ1 and φ2 are never turned on at the same time. The reason is that if φ1 and φ2 are simultaneously turned on even for a moment, all of the switches will be in a closed state, so that both ends of each of the capacitors will be short-circuited and a large power loss will occur. It is because.

  Here, the smaller the values of T and ΔT, the smaller the fluctuation in the current flowing through the load (9). However, if the values of T and ΔT are too small, the so-called switching loss increases, and the power passing efficiency deteriorates. It is preferable to select a switch within a practical range in accordance with the response speed of the switches S1, S2, S3, and S4. Specifically, the value of T may be selected around 0.001 second (1 kHz), and ΔT may be selected to be about 1/10 of T.

  The control signals φ1 and φ2 are generated, for example, as follows. That is, as shown in FIG. 1, a basic square wave generated by an oscillation circuit (12) inside a gate control circuit (11) is divided into two, and one of them is directly used as a first pulse width expansion circuit (14). By passing through, ΔT is added to generate a control signal φ1. After the other is inverted by an inverter (13), the signal is passed through a second pulse width expansion / contraction circuit (15) to add the above-mentioned ΔT, thereby generating a control signal φ2. Of course, the method of generating the control signals φ1 and φ2 is not limited to this, and other conventional circuits may be used in combination.

  A DC power supply (8) is connected as a power supply source to any two of the terminals TP (2), and a load () is connected between any two of the terminals TP (2). 9) Although connected, a plurality of loads (9) can be connected as necessary. Depending on the position at which the DC power supply (8) and the load (9) are connected, the DC voltage of the DC power supply (8) is selected to be stepped up, stepped down, or converted in polarity.

  Here, the DC power supply (8) may be obtained by, for example, rectifying an AC voltage, or a storage battery or the like may be used. The load (9) is widely used as a DC power supply for home appliances such as televisions and radios, as well as information devices such as personal computers, telephones and facsimile machines, or power devices such as motors, solenoid valves and relays. .

  The above is the configuration of the voltage conversion circuit according to the present invention. Next, the operation principle will be described with reference to FIG. 2 in which the circuit is simplified.

  Here, a case where n = 3 will be described for the sake of simplicity. FIG. 2 illustrates a booster circuit that simultaneously supplies a voltage higher than the input voltage of the DC power supply (8) to two loads. The switches SA1, SB1, SC1, SD1, SA1, SB2, SC2, and SD2 are each constituted by the MOSFET (10), but are represented by switch symbols for simplicity of description, and the gate control circuit (11) is omitted.

  The negative terminal of each of the DC power supply (8), the load 1 (12) and the load 2 (13) is connected to a terminal TP1, and the terminal TP1 is used as a ground terminal which is a reference for each part voltage of the circuit. I have. The plus terminal of the DC power supply (8) is connected to the terminal TP2 to supply the voltage E. The positive terminals of the load 1 (12) and the load 2 (13) are connected to the terminals TP3 and TP4, respectively, and serve as power outlets.

  Now, when the control signal φ1 is ON and φ2 is OFF, the switches SA1, SC1, SA2, and SC2 are closed, and the switches SB1, SD1, SB2, and SD2 are open. At this time, a first closed circuit (16) is formed between the DC power supply (8) and the transfer capacitor C21, and a charging current i1 flows from the DC power supply (8) to the transfer capacitor C21. Thereby, the voltage across the transfer capacitor C21 rises to the same value as the voltage E of the DC power supply (8).

  Next, when the control signal φ1 is OFF and φ2 is ON, the switches SA1, SC1, SA2, and SC2 are open and the switches SB1, SD1, SB2, and SD2 are closed. At this time, a second closed circuit (17) is formed between the transfer capacitor C21 and the holding capacitor C12, and the charging current i2 flows from the transfer capacitor C21 to the holding capacitor C12. This causes the voltage across the holding capacitor C12 to rise to the same value as the voltage E across the transfer capacitor C21, so that the voltage at terminal TP3 is 2E with respect to ground.

  Further, the control signal φ1 is turned ON and φ2 is turned OFF again, the switches SA1, SC1, SA2, and SC2 are closed, and the switches SB1, SD1, SB2, and SD2 are open. At this time, a third closed circuit (18) is formed between the terminals TP1, TP2, TP3 and the transfer capacitor C22, and a charging current i3 flows from the TP3 to the transfer capacitor C22. As a result, the voltage across the transfer capacitor C22 rises to the same value as the voltage 2E between the terminals of the TP1 and TP3.

  Further, when the control signal φ1 is OFF and φ2 is ON again, the switches SA1, SC1, SA2, and SC2 are open, and the switches SB1, SD1, SB2, and SD2 are closed. At this time, a fourth closed circuit (19) is formed between the transfer capacitor C22 and the holding capacitor C13, and the charging current i4 flows from the transfer capacitor C22 to the holding capacitor C13. This causes the voltage across the holding capacitor C13 to rise to the same value as the voltage across the transfer capacitor C22, 2E, so that the voltage at terminal TP4 is 4E with respect to ground.

  Since the control signals φ1 and φ2 are continuous, the above operation is repeated, and the voltage at the terminal TP3 is always 2E and the voltage at the terminal TP4 is always 4E. By the way, since the load 1 (12) and the load 2 (13) are connected to the terminal TP3 and the terminal TP4, respectively, a voltage of 2E is supplied to the load 1 (12) and the load 2 (13) Is supplied with a voltage of 4E, and each load can work according to the supplied voltage.

  In this embodiment, when the power supply capability of the DC power supply (8) is sufficiently high, the holding capacitor C11 connected in parallel with the DC power supply (8) may be omitted.

  As described above, the second embodiment of the voltage conversion circuit according to the present invention can generate a voltage higher than the input DC voltage, that is, boost the voltage. Further, as is clear from the above description, when the number of the holding capacitors C1 is n, the input DC voltage can be boosted up to 2 (n-1) times at the maximum. This means that a large boost ratio can be obtained with a small number of n, which is one of the great features of the voltage conversion circuit according to the present invention.

  Next, FIG. 3 shows a second embodiment of the voltage conversion circuit according to the present invention. In the present embodiment, a step-up and step-down circuit for simultaneously supplying a higher voltage and a lower voltage to the two loads to the input DC power supply (8) will be described. The switches SA1, SB1, SC1, SD1, SA1, SB2, SC2, and SD2 are each constituted by the MOSFET (10), but are represented by switch symbols for simplicity of description, and the gate control circuit (11) is omitted.

  The negative terminal of each of the DC power supply (8), the load 1 (12) and the load 2 (13) is connected to a terminal TP1, and the terminal TP1 is used as a ground terminal which is a reference for each part voltage of the circuit. I have. The plus terminal of the DC power supply (8) is connected to the terminal TP3 to supply the voltage E. The positive terminals of the load 1 (12) and the load 2 (13) are connected to the terminals TP2 and TP4, respectively, and serve as power outlets.

  Now, when the control signal φ1 is ON and φ2 is OFF, the switches SA1, SC1, SA2, and SC2 are closed, and the switches SB1, SD1, SB2, and SD2 are open. At this time, a fifth closed circuit (20) is formed between the DC power supply (8) and the transfer capacitor C22, and a charging current i5 flows from the DC power supply (8) to the transfer capacitor C22. As a result, the voltage across the transfer capacitor C22 rises to the same value as the voltage E of the DC power supply (8).

  Next, when the control signal φ1 is OFF and φ2 is ON, the switches SA1, SC1, SA2, and SC2 are open and the switches SB1, SD1, SB2, and SD2 are closed. At this time, a sixth closed circuit (21) is formed between the transfer capacitor C22 and the holding capacitor C13, and the charging current i6 flows from the transfer capacitor C22 to the holding capacitor C13. This causes the voltage across the holding capacitor C13 to rise to the same value as the voltage E across the transfer capacitor C22, so that the voltage at terminal TP4 is 2E with respect to ground.

  At this time, a seventh closed circuit (22) is also formed between the holding capacitor C12 and the transfer capacitor C21, and the charging current i7 flows from the holding capacitor C12 to the transfer capacitor C21. By the way, since the holding capacitor C11 and the holding capacitor C12 are connected in series between TP1 and TP3 and the DC power supply (8) is connected in parallel, the voltage between both ends of the holding capacitor C12 is the two holding capacitors. The voltage divided by the capacitor, that is, E / 2. Therefore, the voltage across the transfer capacitor C21 is E / 2.

  Further, when the control signal φ1 is ON and φ2 is OFF again, the switches SA1, SC1, SA2, SC2 are closed, and the switches SB1, SD1, SB2, SD2 are opened. At this time, an eighth closed circuit (23) is formed between the transfer capacitor C21 and the holding capacitor C11, and the charging current i8 flows from the transfer capacitor C21 to the holding capacitor C11. As a result, the voltage between both ends of the holding capacitor C11 becomes the same value as E / 2 which is the voltage between both ends of the transfer capacitor C21, and the voltage of the terminal TP2 becomes E / 2 with respect to the ground.

  Since the control signals φ1 and φ2 are continuous, the above operation is repeated, and the voltage of the terminal TP2 is always E / 2 and the voltage of the terminal TP4 is always 2E. By the way, since the load 1 (12) and the load 2 (13) are connected to the terminal TP2 and the terminal TP4, respectively, the voltage of E / 2 is supplied to the load 1 (12), and the load 2 ( 13) is supplied with a voltage of 2E, and each load can work according to the supplied voltage.

  As described above, the second embodiment of the voltage conversion circuit according to the present invention can generate a higher voltage and a lower voltage than the input DC voltage, that is, step-up and step-down can be simultaneously performed. Further, as is apparent from the above description, when the number of the holding capacitors C1 is n, the input DC voltage can be reduced to at least 1 / (n-1) th power. This means that a large step-down ratio can be obtained with a small number of n, which is one of the major features of the voltage conversion circuit according to the present invention.

  Next, FIG. 4 shows a third embodiment of the voltage conversion circuit according to the present invention. In this embodiment, a step-up and polarity conversion circuit for simultaneously supplying a voltage higher than the voltage of the input DC power supply (8) and a voltage having the opposite polarity to two loads will be described. The switches SA1, SB1, SC1, SD1, SA1, SB2, SC2, and SD2 are each constituted by the MOSFET (10), but are represented by switch symbols for simplicity of description, and the gate control circuit (11) is omitted.

  The negative terminal of each of the DC power supply (8) and the load 1 (12) and the positive terminal of the load 2 (13) are connected to TP2, and the terminal TP2 is used as a ground terminal which is used as a reference for the voltage of each part of the circuit. are doing. The plus terminal of the DC power supply (8) is connected to the terminal TP3 to supply the voltage E. The terminal TP1 is connected to the minus terminal of the load 2 (13), and the terminal TP4 is connected to the plus terminal of the load 1 (12), which serve as power outlets.

  Now, when the control signal φ1 is OFF and φ2 is ON, the switches SA1, SC1, SA2, and SC2 are open, and the switches SB1, SD1, SB2, and SD2 are closed. At this time, a ninth closed circuit (24) is formed between the DC power supply (8) and the transfer capacitor C21, and a charging current i9 flows from the DC power supply (8) to the transfer capacitor C21. Thereby, the voltage across the transfer capacitor C21 rises to the same value as the voltage E of the DC power supply (8).

  Next, when the control signal φ1 is ON and φ2 is OFF, the switches SA1, SC1, SA2, and SC2 are closed, and the switches SB1, SD1, SB2, and SD2 are open. At this time, a tenth closed circuit (25) is formed between the transfer capacitor C21 and the holding capacitor C11, and a charging current i10 flows from the transfer capacitor C21 to the holding capacitor C13. As a result, the voltage between both ends of the holding capacitor C11 rises to the same value as the voltage E between both ends of the transmission capacitor C21. However, since the plus terminal of the holding capacitor C11 is connected to the ground terminal TP2, the voltage of TP1 becomes -E to earth.

  At this time, an eleventh closed circuit (26) is also formed between the holding capacitors C11 and C12 and the transmission capacitor C22, and the charging current i11 flows from the holding capacitors C11 and C12 to the transmission capacitor C22. By the way, as described above, the voltage between both ends of the holding capacitor C11 is already E, and the voltage between both ends is E because the DC power supply (8) is connected in parallel to the holding capacitor C12. . Therefore, the voltage 2E obtained by connecting these in series becomes the voltage across the transfer capacitor C22.

  Further, when the control signal φ1 is OFF and φ2 is ON again, the switches SA1, SC1, SA2, and SC2 are open, and the switches SB1, SD1, SB2, and SD2 are closed. At this time, a twelfth closed circuit (27) is formed between the transfer capacitor C22 and the holding capacitor C13, and the charging current i12 flows from the transfer capacitor C22 to the holding capacitor C13. Thereby, the voltage between both ends of the holding capacitor C13 becomes the same value as the voltage 2E between both ends of the transfer capacitor C22, and the voltage of the terminal TP4 becomes 3E with respect to the ground.

  Since the control signals φ1 and φ2 are continuous, the above operation is repeated, and the voltage at the terminal TP1 is always −E, and the voltage at the terminal TP4 is always 3E. By the way, since the load 2 (13) and the load 1 (12) are connected to the terminal TP1 and the terminal TP4, respectively, a voltage of -E is supplied to the load 2 (13), and the load 1 (12) is supplied. ) Will be supplied with a voltage of 3E, and each load can work according to the supplied voltage.

  In this embodiment, when the power supply capability of the DC power supply (8) is sufficiently high, the holding capacitor C12 connected in parallel with the DC power supply (8) may be omitted.

  As described above, the third embodiment of the voltage conversion circuit according to the present invention applies a voltage higher than the input DC voltage to the input DC power supply (8) and a voltage having the opposite polarity to the two loads. Simultaneous supply, ie, boosting and polarity conversion, is possible at the same time.

  As is apparent from the above description, the voltage conversion circuit according to the present invention is not limited to the above-described embodiment, but includes a step-up step, a step-down step, and a step-down step of the DC voltage according to the number n and the number of the loads (9). Various voltage conversion circuits that can perform conversion freely can be realized.

FIG. 2 is a circuit diagram showing a first embodiment of the voltage conversion circuit according to the present invention. FIG. 2 is a simplified circuit diagram showing a first embodiment of the voltage conversion circuit according to the present invention. FIG. 4 is a simplified circuit diagram showing a second embodiment of the voltage conversion circuit according to the present invention. FIG. 9 is a simplified circuit diagram showing a third embodiment of the voltage conversion circuit according to the present invention. FIG. 4 is a diagram showing a time chart of a gate control signal used in the voltage conversion circuit according to the present invention.

Explanation of reference numerals

1 Holding capacitor 2 Terminal TP
3 Transfer capacitor 4 Switch SA
5 Switch SB
6 Switch SC
7 Switch SD
8 DC power supply 9 Typical load 10 MOSFET
Reference Signs List 11 gate control circuit 12 oscillation circuit 13 inverter 14 first pulse width expansion / contraction circuit 15 second pulse width expansion / contraction circuit 16 first closed circuit 17 second closed circuit 18 third closed circuit 19 fourth closed circuit 20 Fifth closed circuit 21 sixth closed circuit 22 seventh closed circuit 23 eighth closed circuit 24 ninth closed circuit 25 tenth closed circuit 26 eleventh closed circuit 27 twelfth closed circuit

Claims (3)

N (n is a natural number of 2 or more) holding capacitors C1 (C11, C12... C1n) connected in series for holding power;
N + 1 input / output terminals TP (TP1, TP2,... TPn, TPn + 1) provided at both ends of the holding capacitor C1;
N-1 transfer capacitors C2 (C21, C22,... C2n-1) for transferring power;
Wherein the negative terminal of each of the transfer capacitors C2, the terminal each connected to the n-1 switches SA between one common reference terminal TP1 negative side of the TP (SA1 of the holding capacitor C1 , SA2, ... SAn-1),
Wherein the negative terminal of each of the transfer capacitors C2, the correspondence between each one of the terminals TP to between the holding capacitor C1, respectively connected the n-1 switch SB (SB1, SB2, ··· SBn- 1) and
Between each positive terminal of each of the transfer capacitors C2 and one corresponding terminal TP between each of the holding capacitors C1 , n-1 switches SC (SC1) connected together with each terminal of each of the switches SB. , SC2,... SCn-1);
One end is connected to each plus terminal of each transfer capacitor C2, and the other end is connected to the minus terminal of each holding capacitor C1 via each switch SC for each minus terminal of each transfer capacitor C2. N-1 switches SD (SD1, SD2,..., SDn-1) respectively connected to each positive terminal of the holding capacitor C1 ,
A DC power supply connected as a power supply source between any two of said respective terminals TP,
And at least one load connected between at least two of the respective terminals TP,
A control signal φ1 composed of a square wave whose ON time is set shorter than the OFF time, and a control signal which is turned ON complementarily to the control signal φ1 and whose ON time is set shorter than the OFF time. a gate control circuit for generating φ2, wherein the control signal φ1 opens and closes each of the switches SA and SC, and the control signal φ2 opens and closes each of the switches SB and each switch SD. Voltage conversion circuit 2. The voltage conversion circuit according to claim 1, wherein one common reference terminal TP1 to which each switch SA is connected is connected to a minus terminal of the DC power supply .   3. The voltage conversion circuit according to claim 1, wherein each of said switches is constituted by a MOSFET.

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