JP3595175B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a trench capacitor and a method of manufacturing the same.
[0002]
[Prior art]
Polycrystalline silicon containing impurities can be used as a buried electrode formed in the trench. In the case where the trench sidewall is nearly vertical or in the case of a bottle-shaped structure in which the inside swells with respect to the frontage, a void (seam) is generated inside the buried polysilicon after the buried polysilicon containing impurities. Sometimes. Thereafter, a thermal process is performed to activate the impurities. At this time, a phenomenon is observed in which Si atoms flow (migrate) and locally aggregate due to surface tension in the recrystallization process. . When this Si flow phenomenon occurs, a portion (vacancy) where the polycrystalline silicon film is not formed is generated on the surface of the capacitor insulating film formed on the inner wall of the trench, resulting in a decrease in capacitance and deterioration of the capacitor insulating film. I will.
[0003]
FIG. 7 is a cross-sectional view showing a state before and after heat treatment of a polycrystalline silicon film buried in a trench by a conventional method. FIG. 7A shows a state before the heat treatment, and FIG. 7B shows a state after the heat treatment. 7A, a trench 11 having a vertical side wall is formed in a silicon substrate 10, then a capacitor insulating film 12 is formed on the inner surface of the trench 11, and then the trench 11 having the capacitor insulating film 12 formed on the inner surface is formed. Polycrystalline silicon 13 containing impurities is embedded therein.
[0004]
In the prior art, a phenomenon in which the deposition rate of polycrystalline silicon in the lower portion of the trench 11 is lower than that in the upper portion of the trench 11 is observed. Voids 14 are formed in the holes.
[0005]
Thereafter, when heat treatment is performed, a phenomenon is seen in which Si atoms flow, locally aggregate and recrystallize. In this case, a portion 15 where polycrystalline silicon is not formed occurs on the surface of the capacitor insulating film 12, and as a result, the capacitance is reduced and the reliability of the insulating film is deteriorated due to the electric field concentration.
[0006]
As shown in FIG. 8, the same applies to a case where a trench 21 having a bottle-shaped structure whose inside is swelled with respect to the frontage is formed in a silicon substrate 20 and a capacitor insulating film 22 is formed on the inner surface thereof. The void 24 is remarkably generated in the central portion of the crystalline silicon film 23, and therefore, a portion 25 where polycrystalline silicon is not formed is generated in a wide range.
[0007]
[Problems to be solved by the invention]
The present invention has been made under the above circumstances, and has as its object to provide a semiconductor device having a trench capacitor in which no void is generated, the capacitance is not reduced, and the reliability of an insulating film is not deteriorated.
[0008]
It is another object of the present invention to provide a method of manufacturing a semiconductor device having a trench capacitor in which no void is generated, the capacitance is not reduced, and the reliability of the insulating film is not deteriorated.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a semiconductor substrate having a trench, a capacitor insulating film formed on an inner surface of the trench, and a capacitor embedded in the trench having a capacitor insulating film formed on the inner surface. And a capacitor electrode made of a conductive material containing impurities, wherein the conductive material forming the capacitor electrode has a concentration gradient such that a lower portion of the trench has a lower impurity concentration than a portion of the upper portion of the trench. And a semiconductor device having a trench capacitor.
[0010]
Further, the present invention includes the steps of forming a trench in a semiconductor substrate, forming a capacitor insulating film on the inner surface of the trench, a CVD method using a film-forming material gas and the dopant gas, the semiconductor substrate Is performed while rotating at a rotation speed of 2000 rpm or more, a conductive material containing impurities is buried in the trench in which the capacitor insulating film is formed on the inner surface, and the lower portion of the trench is more dense than the upper portion of the trench. Forming a capacitor electrode having a low impurity concentration .
[0011]
In the gist of the present invention, in particular, in the step of embedding polycrystalline silicon containing impurities, for example, As or P, in a trench having a high aspect ratio by, for example, LPCVD, the impurity concentration becomes lower as going from the upper part to the lower part in the trench. As described above, by giving a gradient to the impurity concentration of the buried polycrystalline silicon, the burying property of the polycrystalline silicon in the trench is improved, and the generation of voids is prevented.
[0012]
Also, in the present invention, by setting the impurity concentration in the polycrystalline silicon in the trench to 2 × 10 ²⁰ atoms / cm ³ or more, even if voids are generated in the buried polycrystalline silicon, Aggregation in the recrystallization process can be suppressed. As a result, a decrease in capacitance can be suppressed and the reliability of the capacitor insulating film can be improved. The upper limit of the impurity concentration is not particularly limited, but is usually about 1 × 10 ²¹ atoms / cm ^{3 .}
In LPCVD used for embedding polycrystalline silicon in a trench, the material gas used is SiH ₄ , and polycrystalline silicon is formed by thermal decomposition of SiH ₄ . At this time, AsH _{3 and} PH _{3 etc. are used} together with SiH _4. The doping gas has the effect of reducing the film formation rate. Therefore, the higher the flow rate of the doping gas, the lower the film formation rate.
[0013]
In the present invention, the film is formed such that the dopant concentration becomes lower as going from the upper portion to the lower portion of the trench. As a result, the film formation rate can be increased as it goes to the lower part of the trench. As a result, a film is formed in which the polycrystalline silicon is buried one by one from the bottom of the trench without being deposited much at the frontage of the trench.
[0014]
As described above, according to the present invention, since the polycrystalline silicon is gradually filled from the lower part of the trench, the frontage is not clogged at the upper part of the trench, it is difficult to form a void, and a good filling shape can be obtained.
[0015]
In addition, when a void is formed in the trench, a phenomenon is seen in which Si atoms of the polycrystalline silicon film flow in a subsequent thermal process and are locally aggregated in a recrystallization process. When the flow phenomenon of Si occurs, a portion where polycrystalline silicon is not formed occurs on the surface of the capacitor insulating film formed on the inner wall of the trench, and the capacitance is reduced. Such a problem can be prevented by setting the impurity concentration in polycrystalline silicon to 2 × 10 ²⁰ atoms / cm ³ as described above.
[0016]
In the semiconductor substrate, an impurity region in which As is diffused is formed in a region in contact with the inner surface of the trench groove, and this can be used as an electrode of the capacitor.
[0017]
In addition, it is preferable that the minimum line width of the trench is 0.2 μm or less and the ratio of the opening area of the trench to the surface area of the semiconductor substrate is 10% or more, because good filling can be performed.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a step of embedding polycrystalline silicon in a trench according to one embodiment of the present invention. In FIG. 1, after a trench 31 having a substantially vertical side wall is formed in a silicon wafer 30, a capacitor insulating film 32 is formed on the inner surface of the trench 31, and then a polycrystalline silicon film 33 as an electrode material is deposited in the trench 31. I do.
[0019]
The polycrystalline silicon film 33 can be formed by simultaneously introducing SiH ₄ and AsH ₃ into a reaction furnace. Before the description, a film formation phenomenon when only SiH ₄ is introduced into the reaction furnace. Will be described.
[0020]
Conventionally, when the upper and lower portions of the polycrystalline silicon film 33 in the trench are compared, the upper portion has a higher deposition rate. This is due to the influence of SiH ₂ (silylene) generated by thermal decomposition of SiH ₄ . SiH ₂ adheres to the silicon wafer 30 with a higher probability than SiH ₄ . The adhesion probability η of SiH _{4 on} the silicon wafer 30 at 700 ° C. is about 10 ⁻⁴ . That is, the reactivity is such that when the SiH ₂ molecule collides with the surface 10000 times, a reaction occurs once.
[0021]
In contrast, SiH ₂ has an adhesion probability η = 1. SiH ₂ as soon as the conflict once on the surface becomes a film. Therefore, the probability that the SiH _{2 that} has flown into the trench portion collides with the substrate at the frontage portion of the trench and adheres to the trench before reaching the lower portion of the trench is very high. For this reason, the film formation rate at the trench frontage is increased, and the trench frontage is closed before the lower part of the trench is formed.
[0022]
As a result, as shown in FIG. 7A, a void 14 is generated at the center of the trench. Therefore, it can be said that the coverage in the trench is deteriorated in the film formation mainly performed by SiH ₂ .
[0023]
SiH ₄ as compared with SiH _2, since adhesion to the wafer probability η is small and 1 10 ⁴ minutes, but the deposition rate is slow, even to the trench bottom well SiH ₄ spreads, at the trench upper and lower The difference in the film formation rate becomes smaller. Therefore, it can be said that a film mainly composed of SiH ₄ has good coverage in the trench. In other words, suppressing generation of SiH ₂ due to thermal decomposition of SiH ₄ can be said to be the key to improving the coverage in the trench.
[0024]
Therefore, when the present inventors rotate the wafer at a high speed, for example, at a rotation speed of about 3000 rpm, the high-temperature region layer where the decomposition of the source gas SiH ₄ starts and the concentration boundary layer are thinned, and the SiH ₄ is directly above the wafer. And found that pyrolysis did not occur until it came.
[0025]
FIGS. 2 and 3 show simulation results of the temperature distribution and the concentration distribution in the vicinity of the wafer when the wafer is rotated at 0 rpm (not rotated) and 2000 rpm, respectively. Here, the wafer is placed on a wafer support, and the wafer is heated from below by a heater.
2 and 3 show the temperature distribution and the concentration distribution, respectively, and show the case where the left half is 2000 rpm and the right half is 0 rpm. 2 and 3, the same pattern indicates the same temperature and concentration.
[0026]
From Figure 2, SiH ₄ flowing _from above, when rotating the wafer at 2000 rpm, how to arrive at the same gas temperature to the wafer near seen. On the other hand, when the wafer is not rotated, as compared with the case where the wafer is rotated at 2000 rpm, it can be seen that the region where the temperature changes above the wafer is thicker. In order to suppress the decomposition of SiH ₄ and the generation of SiH ₂ , it is necessary to make the region where the temperature changes, that is, the temperature boundary layer as thin as possible.
[0027]
Similarly, in FIG. 3, it can be seen that the boundary layer where the concentration changes is thinner when the wafer is rotated at 2000 rpm than when the wafer is not rotated. The fact that the concentration boundary layer is thin means that the vapor phase decomposition of SiH ₄ until it reaches the wafer can be prevented.
[0028]
As described above, it can be seen that by rotating the wafer at a high speed, thermal decomposition of SiH ₄ and generation of SiH ₂ can be suppressed. As a result, the film is formed mainly of SiH ₄ , and the coverage is improved.
[0029]
FIG. 4 schematically shows the effect of rotating the wafer at a high speed. Substrate or, if not, or rotated to a low speed rotation of the upper lobe, the next SiH ₂ partially decomposes the SiH _4, SiH ₂ was flying to the trench portion, before reaching the lower trench, the trench frontage part Collides with and adheres, and the trench frontage closes before the lower portion of the trench is formed. That is, the coverage on the inner surface of the trench is very poor.
[0030]
On the other hand, when the wafer is rotated at a high speed, _{a part} of the SiH ₄ is _{rarely decomposed into} SiH _{2, and} the SiH _{4 that} has flown into the trench portion is not only at the trench opening portion but also at the trench lower portion. And a uniform film can be formed.
[0031]
Next, consider a case where SiH ₄ and AsH ₃ are simultaneously introduced while the wafer is being rotated at a high speed of about 3000 rpm. When comparing the adhesion probability of SiH ₄ and AsH _{3 to} a silicon wafer, the adhesion probability of AsH _{3 is} η = 10 ^{−3 ,} whereas the adhesion probability of SiH ₄ is η = 10 ⁻⁴ , ^{which is} an order of magnitude higher. Therefore, it can be said that As is easily taken into the vicinity of the trench frontage.
[0032]
Therefore, _the concentration of AsH ₃ decreases from the upper part to the lower part of the trench, and a concentration gradient occurs. At this time, AsH ₃ has an effect of inhibiting adsorption of SiH _{4 to} the silicon wafer, so that SiH ₄ is more likely to adhere to the lower part of the trench than to the upper part. Therefore, as compared with the upper part of the trench, the film formation rate becomes faster toward the lower part of the trench (FIG. 1A).
[0033]
As described above, the present invention utilizes the difference between the adhesion probabilities of SiH ₄ and AsH _3. The gradient of the As concentration from the upper part to the lower part of the trench makes it possible to form the upper and lower parts of the trench. The film speed can be changed. When such a phenomenon is used, the polycrystalline silicon 33 is gradually buried from the lower part of the trench to the upper part, so that the frontage is not clogged at the upper part of the trench, so that a good buried shape is obtained without generating a void. I can do it. (FIG. 1 (b)).
[0034]
Since there are no voids, even when heat treatment is performed thereon, the phenomenon that silicon flows does not occur. As a result, polycrystalline Si can be formed on the entire surface of the capacitor insulating film 32.
[0035]
In this embodiment, a silicon wafer having a minimum line width of 0.20 μm or less and a trench opening ratio of 10% or more is rotated at a high speed of about 2000 to 10000 rpm in a CVD chamber maintained at a reduced pressure of several Torr to several hundred Torr. The wafer is heated to about 650 to 750 ° C. from below the wafer by a heater.
[0036]
Thereafter, 1 slm of SiH ₄ and 10 to 500 sccm of AsH ₃ were simultaneously introduced into the reactor, and polycrystalline silicon was formed. When the wafer was rotated at a high speed, the high-temperature region layer on the wafer surface was thinned. Furthermore, by utilizing the difference in the adhesion probability between SiH ₄ and AsH ₃ , the film formation rate at the lower part of the trench is faster than that at the upper part of the trench. As a result, it is possible to form a polycrystalline silicon film having good filling characteristics, in which a void is hardly formed, in the trench.
[0037]
Further, in the case of a bottle-shaped structure 21 as shown in FIG. 8 (a), the inside of which expands with respect to the frontage, even if an As concentration gradient is provided in the trench 21, the formation of the void 24 in the center of the trench is not caused. Inevitable. When the voids 24 are formed, the Si atoms of the polycrystalline silicon film 23 flow and undergo a local aggregation during the recrystallization process as shown in FIG. Can be seen. When this Si flow phenomenon occurs, a portion 25 where polycrystalline silicon is not formed occurs on the surface of the capacitor insulating film 22 formed on the inner wall of the trench, which causes a decrease in capacitance and further a deterioration in reliability of the capacitor insulating film 22. .
[0038]
Such Si flow can be avoided by doping As at a high concentration. It is known that the flow of Si can be suppressed by mixing a large amount of oxygen or carbon into polycrystalline silicon. The present inventors have expected As to have the same effect as oxygen or carbon, and have tried to mix As at a high concentration.
[0039]
FIG. 5 is a graph showing the occurrence or non-occurrence of a flow phenomenon, with the As concentration in the polycrystalline silicon on the vertical axis and the O concentration on the horizontal axis. As concentration is ^{1 × 10 16 ~4 × 10 20} ato ms / cm 3, O concentration is shaken until ^{4 × 10 17 ~1 × 10 19} atoms / cm 3.
[0040]
From FIG. 5, it can be seen that the flow phenomenon of Si is governed by the As concentration, and the As concentration of 2 × 10 ²⁰ atoms / cm ³ is a threshold value for the presence or absence of the flow of Si. Regarding the O concentration, it is considered that there is a concentration at which the flow phenomenon cannot be observed at 1 × 10 ¹⁹ atoms / cm ³ or more. However, when the O concentration is increased, the resistivity of polycrystalline silicon increases, and the high-speed operation of the semiconductor element is reduced. It is a factor that hinders. On the other hand, increasing the As concentration causes a decrease in resistivity.
[0041]
FIG. 6A shows polycrystalline silicon buried in a bottle type trench 71 having an insulating film 72 formed on the inner surface when the impurity concentration in the polycrystalline silicon is set to 2 × 10 ²⁰ atoms / cm ³ or more. The shape of the film 73 is shown. At the center of the buried polycrystalline silicon film 73, a void 74 is seen. After that, the shape in the case where the heat treatment is performed is shown in FIG. In FIG. 6B, no flow phenomenon of Si atoms is observed, and the buried shape after film formation is maintained as it is, and the surface of the capacitor insulating film 72 formed on the inner wall of the trench is favorably formed on the polycrystalline silicon. The film 73 can be formed.
[0042]
【The invention's effect】
As described above, according to the present invention, since the conductive material forming the capacitor electrode has a concentration gradient such that the lower part of the trench has a lower impurity concentration than the upper part of the trench, The embedding property of the conductive material into the conductive material can be improved, and generation of a void (seam) in the conductive material can be prevented.
[0043]
Further, in particular, when the impurity concentration in the polycrystalline silicon is set to 2 × 10 ²⁰ atoms / cm ³ or more, even if voids are generated in the embedded conductive material, the polycrystalline silicon near the capacitor insulating film is not affected. Since the flow of the silicon film can be prevented, a portion where no conductive material is formed on the surface of the capacitor insulating film does not occur, suppressing a decrease in capacitance and improving the reliability of the capacitor insulating film. Can be done.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a step of embedding polycrystalline silicon in a trench according to one embodiment of the present invention.
FIG. 2 is a characteristic diagram showing simulation results of a temperature distribution near a wafer when the wafer is not rotated and when the wafer is rotated.
FIG. 3 is a characteristic diagram showing a simulation result of a concentration distribution near a wafer when the wafer is not rotated and when the wafer is rotated.
FIG. 4 is a schematic diagram showing the effect of rotating the wafer at a high speed.
FIG. 5 is a characteristic diagram showing a relationship between As concentration and O concentration and Si flow.
FIG. 6 is a sectional view showing a step of embedding polycrystalline silicon in a bottle-shaped trench according to one embodiment of the present invention.
FIG. 7 is a cross-sectional view showing a state before and after heat treatment of a polycrystalline silicon film embedded in a vertical trench by a conventional method.
FIG. 8 is a cross-sectional view showing a state before and after a heat treatment of a polycrystalline silicon film buried in a bottle type trench by a conventional method.
[Explanation of symbols]
10, 20, 30 ... silicon substrates 11, 21, 31, 71 ... trenches 12, 22, 32, 72 ... capacitor insulating films 13, 23, 33, 73 ... polycrystalline silicon 14, 15, 24, 25, 74 ... voids

Claims (11)

A semiconductor substrate having a trench,
A capacitor insulating film formed on the inner surface of the trench,
A capacitor electrode made of a conductive material containing an impurity embedded in the trench groove in which a capacitor insulating film is formed on the inner surface,
A semiconductor device having a trench capacitor, wherein the conductive material forming the capacitor electrode has a concentration gradient such that a lower portion of the trench has a lower impurity concentration than a portion of the upper portion of the trench. The semiconductor device according to claim 1, wherein an impurity concentration in the conductive material is 2 × 10 ²⁰ atoms / cm ³ or more. 2. The semiconductor device according to claim 1, wherein an impurity concentration in the conductive material is 2 × 10 ²⁰ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³ . 2. The semiconductor device according to claim 1, wherein the conductive material is polycrystalline silicon, and the impurity is As or P. 2. The semiconductor device according to claim 1, wherein the semiconductor substrate has an impurity region in which As or P is diffused in a region in contact with an inner surface of the trench. 2. The semiconductor device according to claim 1, wherein a minimum line width of the trench is 0.2 μm or less, and a ratio of a frontage area of the trench to a surface area of the semiconductor substrate is 10% or more. 3. Forming a trench in the semiconductor substrate;
Forming a capacitor insulating film on the inner surface of the trench,
By performing a CVD method using a film forming material gas and a dopant gas while rotating the semiconductor substrate at a rotation speed of 2000 rpm or more, an impurity is contained in the trench in which the capacitor insulating film is formed on the inner surface. Forming a capacitor electrode made of a conductive material having a lower impurity concentration in the lower portion of the trench than in the upper portion of the trench . The method of manufacturing a semiconductor device according to claim 7, wherein an impurity concentration in the conductive material is 2 × 10 ²⁰ atoms / cm ³ or more. 8. The method according to claim 7, wherein an impurity concentration in the conductive material is 2 × 10 ²⁰ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³ . The method according to claim 7, wherein the conductive material is polycrystalline silicon, and the impurity is As or P. The method according to claim 1, further comprising, before the step of forming the capacitor insulating film, a step of diffusing As or P in a region of the semiconductor substrate in contact with the inner surface of the trench to form an impurity region. Item 8. A method for manufacturing a semiconductor device according to item 7.

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