JP3594081B2 - Information processing equipment - Google Patents

Description

図４に示すように、キャッシュ制御装置３００は、命令処理装置１００からロード要求が発せられたときに、命令キャッシュ２００のロードアドレス格納領域２０３から読み出されたロードアドレスを旧ロードアドレスとし、命令処理装置１００から要求された処理要求ロードアドレスを新ロードアドレスとして上述の式（１）を計算し予測アドレスを算出する。前述の「固定間隔アドレス予測方式」は、ソフトウエアにおける配列あるいは構造体等の配列要素を連続アクセスするときに有効な先読み方式である。
【００５４】
また、「アドレス組予測方式」とは、図３に示すように、命令キャッシュ２００のロードアドレス格納領域２０３から読み出されたロードアドレスを旧ロードアドレスとし、命令処理装置１００から要求された処理要求アドレスを新ロードアドレスとして、命令処理装置１００からロード要求が発せられる毎に旧ロードアドレスと新ロードアドレスとの組み合せをアクセス履歴テーブルに格納し、今回命令処理装置１００からアクセス要求があったオペランドデータのアドレスが、前記アクセス履歴テーブルに格納される旧ロードアドレスと一致した場合には、旧ロードアドレスに対応する新ロードアドレスを予測アドレスとする方式である。前記「アドレス組予測方式」は、配列をポインタで接続したデータ構造、あるいはリスト型のデータ構造である不定間隔のアドレスに決まった順序でアクセスする場合に有効な先読み方式である。
【００５５】
キャッシュ制御装置３００は、最初に「固定間隔アドレス予測方式」によりロードアドレス予測を行い、該アドレス予測成功の間は、「固定間隔アドレス予測方式」によりロードアドレスの先読みを行う。前記予測失敗時には、先読み方式を「アドレス組予測方式」に変更してロードアドレスの予測を行う。つまり、本実施形態の情報処理装置では、キャッシュ制御装置３００は、アドレス予測に失敗する毎に先読み方式を切り換えることができる。
【００５６】
また、本実施形態の情報処理装置では、命令キャッシュ２００内の命令毎に前述の「先読み抑止」、「先読み試験中」、「先読み確定」の３つの状態のいづれかを保持する。「先読み抑止」状態とは、前記命令に対するオペランドデータの先読みを行わない状態である。「先読み試験中」状態とはキャッシュ制御装置３００の先読みに失敗している状態である。「先読み確定」状態とはキャッシュ制御装置３００による先読みが成功している状態である。「先読み確定」状態の場合、キャッシュ制御装置３００は、前記先読み方式格納領域２０６の設定内容に従いロードアドレスの先読みアドレス予測を行い、先読みを実行する。
【００５７】
図５を用いて、命令処理装置１００により実行される命令の先読み状態の状態遷移を示す。オペランドキャッシュ４００のヒットが継続されている場合には、命令の先読み状態は、遷移Ｔ１を繰り返し、先読みを実行しない「先読み抑止」状態のままである。「先読み抑止」状態でオペランドキャッシュ４００のミスが発生した場合には、命令の先読み状態は、遷移Ｔ２により「先読み試験中」に移行する。「先読み試験中」において、先読みオペランドバッファ６００にミスした場合には、命令の先読み状態は、遷移Ｔ６を繰り返す。
【００５８】
「先読み試験中」において、ロードアドレスが、先読みオペランドバッファ６００の先読みアドレス格納領域６０１に格納されている予測アドレスに一致した場合、すなわち先読みオペランドバッファ６００にヒットし、かつ、ロード命令の命令アドレスと先読みオペランドバッファ６００の命令アドレス格納領域６０２内の命令アドレスとが一致した場合には、先読みが成功したとし、命令の先読み状態は遷移Ｔ３により「先読み確定」に移行する。「先読み確定」において、先読み成功が継続された場合の先読み状態は遷移Ｔ４を繰り返す。
【００５９】
「先読み確定」において、先読みに失敗した場合には、命令の先読み状態は遷移Ｔ５により「先読み試験中」に移行する。「先読み確定」において、実行中のロード命令の命令アドレスと、先読みオペランドバッファ６００の命令アドレス格納領域６０２内の命令アドレスとが一致しなかった場合には、命令の先読み状態は遷移Ｔ８により「先読み抑止」に移行する。
【００６０】
「先読み試験中」および「先読み確定」において、（１）ロード命令のロードアドレスがオペランドキャッシュ４００にヒットした場合、（２）異る命令アドレスのロードあるいはストア命令からのオペランドアドレスが先読み試験中あるいは先読み確定状態の命令が登録した先読みオペランドバッファ６００にヒットした場合、（３）同一のロード命令からの２回の連続するロード命令実行のオペランドアドレスが一致した場合、の３種類のいずれかの条件により、命令の先読み状態はそれぞれ遷移Ｔ７、Ｔ８によって「先読み抑止」に移行する。
【００６１】
次に、図６、図７を用いて本実施形態の情報処理装置の動作について説明する。図６，図７は本実施形態の情報処理装置におけるキャッシュ制御装置３００の動作を示すフローチャートである。
【００６２】
キャッシュ制御装置３００が命令処理装置１００から命令読み出し要求を受け付けると（ステップＳ１００）、命令キャッシュ２００の各記憶テーブル２１０の命令アドレス格納領域２０１に格納された命令アドレスの中に、前記命令読み出し要求で指定された命令アドレスと一致するものがあるかどうか、すなわち、命令キャッシュ２００にヒットしているか否かチェックする（ステップＳ１１０）。
【００６３】
命令キャッシュ２００にヒットしない場合、キャッシュ制御装置３００は、主記憶装置５００から前記命令を読み出し、前記命令を命令処理装置１００に供給するとともに、前記命令と命令アドレスとを、命令キャッシュ２００の命令格納領域２０２と命令アドレス格納領域２０１とに格納する（ステップＳ２００）。
【００６４】
命令キャッシュに前記命令を登録するための空きエントリがない場合、命令キャッシュ２００はＬＲＵ（Ｌｅａｓｔ Ｒｅｃｅｎｔｌｙ Ｕｓｅｄ）等のアルゴリズムによりエントリを置き換える。新規命令を命令記憶テーブル２１０に登録する時は、先読み方式として固定間隔アドレス予測方式を選択し、また、先読み状態として先読み試験中を設定する。
【００６５】
命令処理装置１００は、キャッシュ制御装置３００から供給された命令を解析し、キャッシュ制御装置３００は、命令処理装置１００によって解析された命令が、ロード命令であるか否かチェックする（ステップＳ２１０）。命令がロード命令以外の場合は（ステップＳ２１０のＮｏ側分岐）、ストア命令時はオペランドキャッシュ６００、あるいは主記憶装置５００にストア要求を送り、非メモリアクセス命令の場合は命令に従い動作を行う。
【００６６】
前記命令がロード命令である場合、キャッシュ制御装置３００は、前記命令のロード先のアドレスであるロードアドレスを、前記命令を格納する記憶テーブル２１０のロードアドレス格納領域２０３に格納し（ステップＳ２２０：ロードアドレス登録）、前記ロードアドレスがオペランドキャッシュ４００にヒットしているか否かをチェックする（ステップＳ２３０）。前記ロードアドレスが、オペランドキャッシュ４００にヒットしている場合には、前記命令を格納する記憶テーブル２１０の先読み状態格納領域２０５に「先読み抑止」を設定し（ステップＳ２４０）、ヒットしたオペランドデータを命令処理装置１００に返し、処理を終了する。
【００６７】
ステップＳ２３０において、前記ロードアドレスがオペランドキャッシュ４００にミスした場合には、キャッシュ制御装置３００が主記憶装置５００から前記ロードアドレスのデータを読み込んでオペランドキャッシュ４００に格納するとともに、命令処理装置１００にオペランド・データを供給し、前記命令を格納する記憶テーブル２１０の先読み状態格納領域２０５に「先読み試験中」を設定し、先読み方式格納領域２０６に「固定間隔アドレス予測方式」を設定する（ステップＳ２５０）。
【００６８】
ステップＳ２６０において、先読みオペランドバッファ６００の記憶テーブル６１０の先読みアドレス格納領域６０１と命令キャッシュ２００内の先読みアドレス格納領域２０４に前記ロードアドレスにオペランドキャッシュ４００の読み込み単位であるラインサイズを加算したアドレスを予測アドレスとして格納し、前記予測アドレスを格納する記憶テーブル６１０の命令アドレス格納領域６０２に前記命令の命令アドレスを格納し、データ有効フラグ格納領域６０３のデータ有効フラグをオフとする。ステップＳ２６０において先読み試験中に設定したことから、主記憶装置５００には先読み予測アドレスに対するロード要求、すなわち先読み要求を発行せずに処理を終了する。
【００６９】
ステップＳ２６０において、先読みオペランドバッファ６００の記憶テーブル６１０に未登録領域が存在しない場合、ＬＲＵ（Ｌｅａｓｔ ＲｅｃｅｎｔｌｙＵｓｅｄ）アルゴリズムあるいはリングバッファ方式等により、既登録の記憶テーブル６１０と置き換える。
【００７０】
ステップＳ１１０において、命令キャッシュ２００がヒットしている場合には、キャッシュ制御装置３００は、命令キャッシュ２００の命令格納領域２０２に格納されている命令を命令処理装置１００に供給する（ステップＳ１２０）。前記命令が非メモリアクセス命令である場合、キャッシュ制御装置３００は、処理を終了し、次の命令読み出し要求を待つ（ステップＳ１３０）。
【００７１】
キャッシュ制御装置３００は、命令処理装置１００によって解析された命令が、ロード命令であるか否かをチェックする（ステップＳ１４０）。前記命令がロード命令でない場合には、すでにステップＳ１３０でメモリアクセス命令であることが確定しているために前記命令はストアであり、キャッシュ制御装置３００は、前記ストア命令のオペランドデータがオペランドキャッシュ４００にヒットしているか否かをチェックする（ステップＳ５００）。ステップＳ５００において、ストア命令のオペランドがオペランドキャッシュ４００にヒットしている場合、キャッシュ制御装置３００がオペランドキャッシュ４００に対してストア要求を行う（ステップＳ５１０）。
【００７２】
ステップＳ５００において、ストア命令のオペランドがオペランドキャッシュ４００にミスした場合、キャッシュ制御装置３００は、主記憶装置５００に対してストア要求を行う（ステップＳ５２０）。また、キャッシュ制御装置３００は、前記ストア要求のアドレスが、先読みオペランドバッファ６００の各記憶テーブル６１０の中の先読みアドレス格納領域６０１に格納されている予測アドレスと一致しているテーブルが存在するか、すなわちヒットしているか否かをチェックする（ステップＳ５３０）。
【００７３】
前記ストア要求のアドレスが、先読みオペランドバッファ６００にヒットしている場合、キャッシュ制御装置３００は、ヒットした先読みアドレス格納領域６０１に対応した命令アドレス６０２に格納されている命令アドレスを読み出し、前記命令アドレスが命令キャッシュ２００にヒットしているか否かをチェックする（ステップＳ５４０）。
【００７４】
前記命令アドレスが命令キャッシュ２００にヒットしている場合には、ロードとストアの複数の命令に使用されるアドレスであり、オペランドキャッシュ４００の登録対象であり、ヒットした記憶テーブル２１０の先読み状態格納領域２０５に「先読み抑止」を設定する（ステップＳ５５０）。
【００７５】
ステップＳ１４０において、前記命令がロード命令であった場合には、キャッシュ制御装置３００は、ロードアドレスがオペランドキャッシュ４００にヒットしているか否かをチェックする（ステップＳ１５０）。前記命令のロードアドレスがオペランドキャッシュ４００にヒットしている場合には、キャッシュ制御装置３００はオペランドキャッシュ４００からデータを読み出し、前記データを命令処理装置１００へ供給する（ステップＳ１６０）。さらに、今回のアクセスは、局所的なアクセスであると見なし、前記命令が格納されている命令格納領域２０２に対応する先読み状態格納領域２０５に「先読み抑止」を設定し（ステップＳ１７０）、処理を終了する。
【００７６】
ここで、命令処理装置１００からのロード要求のロードアドレスと、先読みオペランドバッファ６００の記憶テーブル６１０の先読みアドレス格納領域６０１に格納されている先読みアドレスとが一致することを「先読みヒット」とする。また、「先読みヒット」、かつ、ヒットした記憶テーブル６１０内の命令アドレス格納領域６０２に格納されている命令アドレスがロード命令の命令アドレスと一致することを、「先読み自命令ヒット」とする。
【００７７】
ステップＳ１５０において、前記ロードアドレスがオペランドキャッシュ４００にミスした場合には、先読みオペランドバッファ６００にヒットか否かをチェックする（ステップＳ３００）。
【００７８】
キャッシュ制御装置３００は、先読みオペランドバッファ６００にヒットした記憶テーブル６１０のデータ有効フラグをチェックし（ステップＳ３１０）、前記データ有効フラグがデータ無効（オフ）を示している場合、キャッシュ制御装置３００は主記憶装置５００からデータを読み出して命令処理装置１００に供給し（ステップＳ３２０）、前記データ有効フラグがデータ有効（オン）を示している場合、キャッシュ制御装置３００はヒットした記憶テーブル６１０のデータ格納領域６０４からデータを読み出して命令処理装置１００に供給する（ステップＳ３３０）。
【００７９】
ステップＳ３２０およびステップＳ３３０では主記憶装置５００あるいは先読みオペランドバッファ６００から読みだしたデータはオペランドキャッシュ４００に登録しない。
【００８０】
ステップＳ３４０において、キャッシュ制御装置３００は、「先読み自命令ヒット」であるか否かをチェックする（ステップＳ３４０）。前記ロードアドレスが、「先読み自命令ヒット」の場合には、キャッシュ制御装置３００は、先読みが成功したとして、前記命令を格納する記憶テーブル２１０の先読み状態格納領域２０５に「先読み確定」を設定し（ステップＳ３５０）、先読み予測アドレスを求め、該先読み予測アドレスを、前記命令を格納する記憶テーブル２１０の予測アドレス格納領域２０４と、ヒットした記憶テーブル６１０の先読みアドレス格納領域６０１に格納し、前記予測アドレスの主記憶装置５００上のオペランドデータをデータ格納領域６０４に読み込み、先読みによるオペランドデータが読み込まれた記憶テーブル６１０のデータ有効フラグ格納領域６０４のデータ有効フラグをオンにする（ステップＳ３７０）。
【００８１】
ステップＳ３４０において、「先読み自命令ヒット」でなかった場合、キャッシュ制御装置３００は、前記ロードアドレスが複数の命令から参照されているアクセス頻度の高いアドレスであると見なし、前記命令を記憶する記憶テーブル２１０の先読み状態格納領域２０５に「先読み抑止」を設定する（ステップＳ３６０）。
【００８２】
ステップＳ３００において、前記ロードアドレスが先読みオペランドバッファ６００にミスした場合には、キャッシュ制御装置３００は、前記先読み方式格納領域２０６に格納されている先読み方式を変更し（ステップＳ４１０）、前記先読み方式格納領域２０６に格納された変更された先読み方式に従って予測アドレスを生成し、該予測アドレスを命令キャッシュ２００の予測アドレス格納領域２０４および、先読みオペランドバッファ６００の先読みアドレス格納領域６０１に格納する（ステップＳ４２０）。
【００８３】
ステップＳ４３０において、キャッシュ制御装置３００は主記憶装置５００からデータを読み出し、命令処理装置１００に供給し、読みだしたデータをオペランドキャッシュ４００に登録する。
【００８４】
（発明の他の実施の形態）
以下に、本発明のその他の実施形態について説明する。以下の（Ａ）−（Ｆ）はそれぞれ実施例を意味する記号である。
（Ａ）複数の先読み方式を切り替えて予測するのではなく、同時に複数の先読み方式により次回のロードアドレスを予測する方式の実施例を以下に示す。
【００８５】
前記先読みオペランドバッファ６００の記憶テーブル６１０に先読み方式格納領域を追加し、記憶テーブル６１０への登録時に、先読みアドレスを生成した先読み方式を設定する。キャッシュ制御装置３００が命令処理装置１００からのロード要求を受け取った時の動作を以下に説明する。
【００８６】
前記の実施の形態との相違点を以下の（相違点１）、（相違点２）に示す。
【００８７】
（相違点１）前記ロード要求のロードアドレスがオペランドキャッシュ４００にミスし、先読みオペランドバッファ６００にヒットした場合、ヒットした記憶テーブル６１０内の先読み方式格納領域２０６内の先読み方式を命令キャッシュ記憶テーブル２１０内の先読み方式格納領域に設定し、データ有効フラグ格納領域６０３の内容がオンの場合はデータ格納領域６０４から、データ有効フラグ格納領域６０４の内容がオフの場合は主記憶装置５００から、ロード要求されたデータを読み出し、命令処理装置１００へ供給する。前記ロード要求されたデータは先読みヒットであるため、オペランドキャッシュ４００には登録せず、前記先読み方式により先読みアドレス予測を行い、先読みを実行し読み出したデータを予測アドレスと共に先読みオペランドバッファ６００に登録する。
【００８８】
（相違点２）前記ロード要求のロードアドレスがオペランドキャッシュ４００にミスし、かつ先読みオペランドバッファ６００にミスした場合、複数の先読み方式で予測された次回のロードアドレスそれぞれに対して、オペランドバッファ６００に登録すると同時に、各記憶テーブル６１０の先読み方式格納領域にそれぞれの先読み方式を設定する。今回のロードに対する先読みはミスであったため、前記先読み予測アドレスに対する先読みは行わず、データ有効フラグ格納領域６０４をオフに設定する。
【００８９】
上記２つの相違点以外に関しては、最初の実施例の動作を行う。本実施例により、先読み予測が成功するまでの期間を短縮することができる。
（Ｂ）以下に、命令キャッシュ２００内の予測アドレス格納領域２０４により先読み予測の成功あるいは失敗を判断する実施の形態を示す。
【００９０】
命令キャッシュ２００の予測アドレス格納領域２０４に格納されたロードアドレスと、命令処理装置１００から要求されたロードアドレスとを比較することにより、
前記比較結果が一致した場合を先読み成功、不一致の場合を先読み失敗とする。ただし、前記比較結果が一致したが、先読みオペランドバッファ６００に該当する予測アドレスに対する記憶テーブル６１０が存在しない場合、すなわち前回の命令実行の後、今回の命令実行の前に、他命令の実行により記憶テーブル６１０が置き換えられた場合は、先読みデータ有効フラグ６０３がオフであったとして動作する。また、命令キャッシュ２００の予測アドレス格納領域２０４内のとロードアドレスと、今回のロード要求のロードアドレスにより先読みの成功あるいは失敗を判断することにより、前記発明の先読み自命令ヒットあるいは他命令ヒットという場合の区別がなく、全ての先読みヒットは前記自命令ヒットとして動作を行う。
【００９１】
上記の動作により、先読みアドレス予測の成功あるいは失敗を判断する以外は最初の実施例の動作を行う。本実施例により、先読みアドレス予測が成功した時のみ先読みオペランドバッファ６００を索引し、先読みアドレス予測が失敗した場合には、先読みオペランドバッファ６００の索引が不要となり、先読みオペランドバッファ６００の負荷を低減することができる。
（Ｃ）本発明の他の情報処理装置では、前記命令キャッシュから前記先読み状態を削除し、先読み状態によらず、オペランドキャッシュへのミス、かつ、先読みの成功時にのみ先読みを実行する装置の実施例を以下に示す。
【００９２】
本構成においては、先読み状態が存在しないため、キャッシュ制御装置３００の動作は命令処理装置１００からのロード要求に対するオペランドキャッシュ４００へのヒット・ミス、および先読みアドレス予測の成功・失敗により決定される。以下の（条件Ｋ１）〜（条件Ｋ４）は各動作条件を示す記号である。
【００９３】
（条件Ｋ１） オペランドキャッシュ４００ヒット時は、先読み動作は行われずオペランドキャッシュ４００に対してロード要求が行われ、読み出されたデータが命令処理装置１００に供給される。
【００９４】
（条件Ｋ２） オペランドキャッシュ４００ミス時かつ先読みアドレス予測失敗の場合は、先読み方式格納領域２０６の内容を変更し、先読み方式を変更し、変更された先読み方式により先読み予測アドレスを生成し、予測アドレス格納領域２０４に設定する。本条件においては先読みは実行されず、データ有効フラグ格納領域６０３をオフに設定する。本条件においては、前記ロード要求により読み出したデータをオペランドキャッシュ４００に登録する。さらに、アクセス履歴テーブル７００に、更新前のロードアドレス２０３と前記ロード要求のロードアドレスをそれぞれ実行中ロードアドレス、予測ロードアドレスとしてを登録する。
【００９５】
（条件Ｋ３） オペランドキャッシュ４００ミス時かつ先読みアドレス予測成功、かつデータ有効フラグ格納領域６０３がオフの場合は、主記憶装置５００からロード要求されたデータを読み出し命令処理装置１００に供給する。さらに、先読み方式格納領域２０６の先読み方式により先読みアドレスを予測し、オペランドキャッシュ４００に先読み要求を発行する。前記先読み要求がオペランドキャッシュ４００にヒットした場合は、先読みを行わずに先読み処理を終了する。前記先読み要求がオペランドキャッシュ４００にミスした場合は主記憶装置５００に対してロード要求を送信し、読み出しデータをデータ格納領域６０４にデータを格納し、データ有効フラグ６０３をオンとし、先読みした予測アドレスを予測アドレス格納領域２０４に設定する。本条件においては、前記ロード要求により読み出したデータは、オペランドキャッシュ４００に登録される。
【００９６】
（条件Ｋ４） オペランドキャッシュ４００ミス時かつ先読みアドレス予測成功、かつデータ有効フラグ格納領域６０３がオンの場合は、データ格納領域６０４からロード要求されたデータを読み出し命令処理装置１００に供給する。さらに、先読み方式格納領域２０６の先読み方式により先読みアドレスを予測し、オペランドキャッシュ４００に先読み要求を発行する。前記先読み要求がオペランドキャッシュ４００にヒットした場合は、先読みを行わずに先読み処理を終了する。前記先読み要求がオペランドキャッシュ４００にミスした場合は主記憶装置５００に対してロード要求を送信し、読み出しデータをデータ格納領域６０４にデータを格納し、データ有効フラグ６０３をオンとし、先読みした予測アドレスを予測アドレス格納領域２０４に設定する。本条件においては、前記ロード要求により読み出したデータは、オペランドキャッシュ４００に登録されない。
【００９７】
前記条件Ｋ１〜Ｋ４で指定された動作により先読みの実行の有無あるいはオペランドキャッシュ４００への登録の有無を判断する。
【００９８】
本実施例により、先読み状態による動作の相違のための複雑な制御を削除し、かつ、記憶テーブル２１０の情報量を削減することができる。
（Ｄ）次に、命令キャッシュ２００内の予測アドレス格納領域２０４により先読みアドレス予測の成功あるいは失敗を判断し、先読みオペランドキャッシュ６００を省略した構成による実施例を以下に示す。
【００９９】
本構成においては、先読みオペランドバッファ６００が存在しないため、先読みしたデータはオペランドキャッシュ４００に登録される。したがって、オペランドキャッシュ４００には命令処理装置１００からのロード要求により読み出したデータおよび先読みにより読み出したデータの両方が登録される。本実施例の情報処理装置の場合には、ロード要求はオペランドキャッシュ４００あるいは主記憶装置５００に転送され、ロード要求が発生する度に先読みアドレス予測の成功・失敗を判断し、先読みアドレス予測が成功した場合には次の先読み要求を主記憶装置５００あるいはオペランドキャッシュ４００に転送する。主記憶装置５００から先読みデータが読み出された場合には、オペランドキャッシュ４００に先読みデータを登録する。先読み状態遷移、先読みアドレス予測方式に関しては最初の実施例の動作を行う。
【０１００】
本実施例により、先読みオペランドバッファ６００を削除することができ、ハードウェア量を削減することができる。（Ｅ）前記（Ｄ）において、命令キャッシュ２００の記憶テーブル２１０にデータ有効フラグ６０３、データ格納領域６０４を追加した実施例を図８を使用して説明する。
【０１０１】
図８においては、前記命令キャッシュ２００に前記の実施例では先読みオペランドバッファ６００内に実装されていたデータ有効フラグ格納領域６０３とデータ格納領域６０４を実装する。前記（Ｄ）同様に先読みオペランドバッファ６００が存在せず、先読みアドレス予測の成功あるいは失敗の判断は命令キャッシュ内の予測アドレス格納領域２０４を用いて行われる。ただし、先読みされたデータはデータ格納領域６０４に格納され、オペランドキャッシュ４００に登録されないことが異なる。本方式によりオペランドキャッシュ４００に先読みに成功する非局所的なデータをオペランドキャッシュ４００に登録せず、オペランドキャッシュ４００を有効に使用することができる。
【０１０２】
本実施例においては、先読みデータを命令毎に持つことにより、先読みによる使用頻度の低い可能性の高いデータをオペランドキャッシュに登録しないことにより、小容量のオペランドキャッシュを有効に活用することができる。
（Ｆ） 前記（Ｄ）において、命令キャッシュ２００内の記憶テーブル２１０から予測アドレス格納領域２０４を削除することにより、命令キャッシュ記憶テーブル２１０の１組あたりの情報量を削減する実施例を示す。
【０１０３】
前回のロードアドレスと先読み方式とから前回のロード実行時の先読み予測アドレスを生成することにより、予測アドレス格納領域２０４を削除することが可能になる。本実施例においては、今回のロード要求のロードアドレスと、前回のロードアドレス２０３と、先読み方式２０６から予測された予測アドレスとを比較することにより、先読みアドレス予測の成功と失敗を判断する。前記ロードアドレスと予測アドレスが一致した場合を予測成功とし、不一致の場合を予測失敗とする。本実施例の方式により、記憶テーブル２１０の情報量を削減できる。
【０１０４】
（発明の他の課題）
前述の先読み状態格納領域２０５が存在する場合の技術においては、先読みが１度失敗することにより、先読み状態を先読み試験中に変更し、先読み方式を変更する。
【０１０５】
図９にＣ言語で記載されているネストしたループの内部でメモリアクセスが行われるプログラムにおいて、最も内側のループが終了したが外側のループが終了しない場合、メモリアクセスの基準アドレスが変更され、再度最も内側のループが実行され、ループの再入前後において実行されたメモリアクセスの間隔が不連続となるために、再入直後のロード命令の先読みが失敗する。前記最も内側のループへの再入後の２回目の繰り返し以降では、最も内のループのロード命令は、以前先読みが成功していた時の先読み方式を使用すれば成功する可能性が高い。
【０１０６】
図９に示されたネストしたループ構造のプログラムを前述の情報処理装置が処理した場合、最も内側のループへの再入直後の先読み失敗により先読み方式が変更されているために、先読み方式が元に戻るまで先読みが失敗し、先読みが再び成功するまでに無駄な先読みアドレス予測の試行が発生する。
【０１０７】
図９に示すＣ言語によって記述されているプログラムを用いて一例を示す。図９のＣ言語記述における繰り返しループの部分の仮想マシン命令への展開後の命令列を図１０に示す。図１０は２重の繰り返しループを実行する命令列であり、内側のループが終了し、次に内側のループを実行する際の行Ｌ８のロード命令
ｌｏａｄ ｒ（ａ） ＝ Ｍｅｍｏｒｙ［ａ＋ｘ＊２０００＋ｙ］のメモリアクセス履歴を図１１に示す。
【０１０８】
図１１中の「連番」がロード実行の順番を、「アドレス」がロード命令のオペランドデータの主記憶装置５００上のアドレスであるロードアドレスを、「間隔」が連続する２回の前記アドレスの差分を、「備考」が同一行のロードに対する注釈を示す。連番１から連番１０００までと、連番１００２から連番１００３までの前記間隔が＋１であるが、連番１００１における間隔は＋１００１であり、他の連番のアドレスの間隔とは異ることが問題となる。
【０１０９】
前記情報処理装置では、連番１００１のロード命令実行時には先読み予測が失敗するが、連番１００２では再び間隔が＋１になっており、連番１から１０００までの先読み方式で先読みを実行すれば先読みは成功する。しかし、１度の先読み失敗により先読み方式を変更すると、ネストしたループ構造の命令列に対し、最内部のループを抜け出す度に、先読み方式の不要な切り替えが発生する。
【０１１０】
（発明の他の課題を解決するための手段）
本問題を解決するため、前記の情報処理装置における先読み状態である「先読み抑止状態」と、「先読み試験中状態」と、「先読み確定状態」との他に、新たに「弱い先読み確定状態」を設け、「先読み確定状態」において先読みに失敗した場合には、「弱い先読み確定状態」に遷移し、「弱い先読み確定状態」に遷移する時には、先読み方式を変更せず、かつ、先読みによるオペランドデータの読み込みを実行し、「弱い確定状態」においてあらかじめ決められた回数の先読み失敗が発生した場合に、先読み方式を変更し、先読み試験状態に遷移することにより、前記ネストしたループにおいて内部ループを抜け出した後の一度の先読み失敗によっては先読み方式を変更せず、あらかじめ定められた規定の回数の先読み失敗により先読み方式を切り替える方式を用いて前記の発明の他の課題を解決する。
【０１１１】
（発明の他の課題を解決するための実施の形態）
前記課題を解決するための実施例を図１２を用いて説明する。
【０１１２】
図１２中の表の各列の意味は「Ｐ−ＭＡＴＣＨ」を除いて図２と同じである。「Ｐ−ＭＡＴＣＨ」は、命令処理装置１００からのロード要求のロードアドレスと、命令キャッシュ２００内のロード要求を発行したロード命令の登録されている記憶テーブル２１０内の予測アドレス格納領域２０４とが一致した場合を先読みヒットとして「Ｈｉｔ」で示し、不一致の場合を先読みミスとし「Ｍｉｓｓ」で表す。また、「−−−」は任意の状態を示し、先読みヒットあるいはミスとは無関係であることを示す。
（１）先読み状態が抑止中の動作
条件Ｄ１Ａ〜Ｄ１Ｄにおける、「旧状態」が「抑止」、すなわち先読み状態が抑止中の動作について説明する。キャッシュ制御装置３００が命令処理装置１００からのロード要求のロードアドレスを命令キャッシュ２００のロードアドレス格納領域２０３に登録し、オペランドキャッシュ４００を索引するときに、条件Ｄ１Ａにおける、オペランドキャッシュ４００にヒットした場合、前記状態は抑止状態のまま未変更とし、先読みを実行しない。
【０１１３】
条件Ｄ１Ｂ、Ｄ１Ｃにおける、オペランドキャッシュ４００にミスし、「先読みヒット」した場合には、キャッシュ制御装置３００は、前記ロードアドレスにより先読みオペランドバッファ６００を索引し、前記ロードアドレスと先読みアドレス格納領域６０１の比較結果が一致する記憶テーブル６１０が存在し、かつデータ有効フラグ格納領域６０３がオンであった場合には、データ格納領域６０４のデータを命令処理装置１００に供給し、前記比較結果が不一致または前記データ有効フラグ格納領域６０３がオフであった場合には、前記ロード要求を主記憶装置５００に転送し、読みだしたデータを命令処理装置１００に供給し、オペランドキャッシュ４００には登録せず、先読み状態格納領域２０５に「先読み確定」を設定し、先読み方式格納領域２０６に格納されている先読み方式に従い、条件Ｄ１Ｂの場合は「固定間隔アドレス予測方式」、条件Ｄ１Ｃの場合は「アドレス組予測方式」により、先読み予測アドレスを生成し、該予測アドレスを先読みアドレス格納領域２０４に登録するとともに、先読み要求をオペランドキャッシュ４００に送り、前記先読み要求がオペランドキャッシュ４００にヒットした場合には、データ有効フラグ６０３をオフにし、オペランドキャッシュ４００にミスした場合には、主記憶装置５００に先読み要求を送り、読みだされたデータをデータ格納領域６０４に登録し、データ有効フラグ格納領域６０３をオンにする。
【０１１４】
条件Ｄ１Ｄにおける、先読み状態が抑止状態で、かつ、オペランドキャッシュ４００にミスし、先読みミスした場合、キャッシュ制御装置３００は、前記ロード要求を主記憶装置１００に転送し、読みだしたデータを命令処理装置１００に供給し、オペランドキャッシュ４００に登録し、先読み状態を「先読み試験中」に変更するとともに、先読み方式を変更し、変更された先読み方式に従い生成した予測アドレスを予測アドレス格納領域２０４に登録する。
（２）先読み状態が試験中の動作
条件Ｄ２Ａ〜Ｄ２Ｆにおける、「旧状態」が「試験中」、すなわち先読み状態が試験中の動作について説明する。条件Ｄ２Ａ、Ｄ２Ｂにおける、オペランドキャッシュ４００にヒットし、かつ、先読みヒットした場合、キャッシュ制御装置３００は前記ロード要求をオペランドキャッシュ４００に転送し、読みだしたデータを命令処理装置１００に供給し、先読み状態格納領域２０５に「弱い先読み確定」を設定し、先読み方式格納領域２０６に従い先読み予測アドレスを生成し、該予測アドレスを予測アドレス格納領域２０４に登録するとともに、先読み要求をオペランドキャッシュ４００に送り、前記先読み要求がオペランドキャッシュ４００にヒットした場合には、データ有効フラグ６０３をオフにし、前記先読み要求がオペランドキャッシュ４００にミスした場合には、主記憶装置５００に先読み要求を送り、読みだ出したデータをデータ格納領域６０４に登録し、データ有効フラグ格納領域６０３をオンにする。
【０１１５】
条件Ｄ２Ｃにおける、「旧状態」が「試験中」状態かつ、オペランドキャッシュ４００にヒットし、かつ、先読みミスした場合、キャッシュ制御装置３００は前記ロード要求をオペランドキャッシュ４００に転送し、読みだしたデータを命令処理装置１００に供給し、先読み状態格納領域２０５に「先読み抑止」を設定し、先読み方式格納領域２０６に格納されている方式に従い先読み予測アドレスを生成し、該予測アドレスを予測アドレス格納領域２０４に登録する。
【０１１６】
条件Ｄ２Ｄ、Ｄ２Ｅにおける、オペランドキャッシュ４００にミスし、かつ、先読みヒットした場合、キャッシュ制御装置３００は先読みオペランドバッファ６００を前記ロード要求のロードアドレスによりオペランドバッファ６００を索引し、前記ロードアドレスと先読み予測アドレス格納領域６０１とを比較し、前記比較結果が一致であり、かつ、データ有効フラグ格納領域６０３がオンであった場合には、データ格納領域６０４のデータを命令処理装置１００に供給し、前記比較結果が不一致または前記データ有効フラグ格納領域６０３がオフであった場合には、前記ロード要求を主記憶装置５００に転送し、読みだしたデータを命令処理装置１００に供給するが、オペランドキャッシュ４００に登録せず、先読み状態格納領域２０５に「先読み確定」を設定し、先読み方式格納領域２０６に従い先読み予測アドレスを生成し、該予測アドレスを予測アドレス格納領域２０４に登録すると共に、先読み要求をオペランドキャッシュ４００に送り、オペランドキャッシュ４００にヒットした場合には、データ有効フラグ６０３をオフにし、オペランドキャッシュ４００ミスの場合には、主記憶装置５００に先読み要求を送り、読みだされたデータをデータ格納領域６０４に登録し、データ有効フラグ格納領域６０３をオンにする。
【０１１７】
条件Ｄ２Ｆにおける、「旧状態」が「試験中」であり、かつ、オペランドキャッシュ４００にミスし、かつ、先読みミスした場合、キャッシュ制御装置３００は前記ロード要求を主記憶装置１００に転送し、読みだしたデータを命令処理装置１００に供給し、オペランドキャッシュ４００に登録し、先読み状態を先読み試験中に変更するとともに、先読み方式を変更し、変更された先読み方式に従い予測された予測アドレスを予測アドレス格納領域２０４に登録する。また、条件Ｄ２Ｆでは、アドレス履歴テーブル７００に、ロードドレス格納領域２０３の値および今回のロード要求のロードアドレスをそれぞれ、実行中ロードアドレスおよび予測ロードアドレスに登録する。
（３）先読み状態が先読み確定であるときの動作
条件Ｄ３Ａ〜Ｄ３Ｆにおける、「旧状態」が「先読み確定」であるときの動作について説明する。
【０１１８】
条件Ｄ３Ａ、Ｄ３Ｂにおける、「旧状態」が「先読み確定」かつ、オペランドキャッシュ４００にヒットし、かつ、先読みヒットした場合、キャッシュ制御装置３００は、それぞれ前記条件Ｃ２Ａ、Ｃ２Ｂと同じ動作を行う。
【０１１９】
条件Ｄ３Ｃにおける、「旧状態」が「先読み確定」かつ、オペランドキャッシュ４００にヒットし、かつ、先読みミスした場合、キャッシュ制御装置３００は前記ロード要求をオペランドキャッシュ４００に転送し、読みだしたデータを命令処理装置１００に供給し、先読み状態格納領域２０５に弱い先読み確定を設定し、先読み方式格納領域２０６に従い先読み予測アドレスを生成し、該予測アドレスを予測アドレス格納領域２０４に登録するとともに、先読み要求をオペランドキャッシュ４００に送り、オペランドキャッシュ４００にヒットした場合には、データ有効フラグ６０３をオフにし、オペランドキャッシュ４００ミスの場合には、主記憶装置５００に前記先読み要求を送り、読みだされたデータをデータ格納領域６０４に登録し、データ有効フラグ格納領域６０３をオンにするが、アドレス履歴テーブル７００に登録しない。
【０１２０】
条件Ｄ３Ｄ、Ｄ３Ｅにおける、「旧状態」が「先読み確定」であり、かつ、オペランドキャッシュ４００にミスし、かつ、先読みヒットした場合、キャッシュ制御装置３００はそれぞれ前記条件Ｄ２Ｄ、Ｄ２Ｅと同じ動作を行う。
【０１２１】
条件Ｄ３Ｆにおける、「旧状態」が「先読み確定」であり、かつ、オペランドキャッシュ４００にミスし、かつ、先読みミスした場合、キャッシュ制御装置３００は、前記ロード要求を主記憶装置５００に転送し、読みだしたデータを命令処理装置１００に供給する。さらに、先読み状態格納領域２０５に「弱い先読み確定」を設定し、先読み方式格納領域２０６に従い先読み予測アドレスを算出し、該予測アドレスを予測アドレス格納領域２０４に登録すると共に、先読み要求をオペランドキャッシュ４００に送り、オペランドキャッシュ４００にヒットした場合には、データ有効フラグ６０３をオフにし、オペランドキャッシュ４００ミスの場合には、主記憶装置５００に前記先読み要求を送り、読みだされたデータをデータ格納領域６０４に登録し、データ有効フラグ格納領域６０３をオンにするが、アドレス履歴テーブル７００には登録しない。
（４）「先読み状態が弱い確定の動作」
条件Ｄ４Ａ〜Ｄ４Ｆにおける、「旧状態」が「弱い先読み確定」、すなわち先読み状態が試験中の動作について説明する。
【０１２２】
条件Ｄ４Ａ，Ｄ４Ｂにおける、「旧状態」が「弱い先読み確定」であり、かつ、オペランドキャッシュ４００にヒットし、かつ、先読みヒットした場合、キャッシュ制御装置３００は、それぞれ前記条件Ｄ２Ａ、Ｄ２Ｂと同じ動作を行う。
【０１２３】
条件Ｄ４Ｃにおける、「旧状態」が「弱い先読み確定」であり、かつ、オペランドキャッシュ４００にヒットし、かつ、先読みミスした場合、キャッシュ制御装置３００は前記条件Ｄ２Ｃのときと同じ動作を行う。ただし、複数の弱い先読み確定状態、例えば、弱い先読み確定状態１、弱い先読み確定状態２，．．．弱い先読み確定状態Ｎを設けて、あらかじめ決められた回数の連続した先読み失敗によって、先読み試験中状態に遷移することにすることにより、先読み試験中状態に遷移して先読み方式を変更することにより、先読み方式変更を遅くすることも可能である。
【０１２４】
条件Ｄ４Ｄ、Ｄ４Ｅにおける、「旧状態」が「弱い先読み確定」であり、かつ、オペランドキャッシュ４００にミスし、かつ、先読みヒットした場合、キャッシュ制御装置３００はそれぞれ前記条件Ｄ２Ｄ、Ｄ２Ｅのときと同じ動作を行う。
【０１２５】
条件Ｄ４Ｆにおける、「旧状態」が「弱い先読み確定」かつ、オペランドキャッシュ４００にミスし、かつ、先読みミスした場合、キャッシュ制御装置３００は前記条件Ｄ２Ｆのときと同じ動作を行う。
【０１２６】
【発明の効果】
以上述べたように、本発明の情報処理装置では、以下に示す効果を有する。
（１） 命令処理装置が実行するロード命令のロードアドレスが実行毎に常に同一アドレスである固定アドレスアクセス・ロード命令の場合には、データは一度オペランドキャッシュに登録するだけで後続の同一ロード命令実行時にはキャッシュにヒットする可能性が高いため、先読みによる効果はない。
【０１２７】
一方、ロードアドレスが実行毎に変化するロード命令の場合には、前回アクセスしたデータが再度使用される可能性が低いため、オペランドキャッシュにヒットする可能性は低く、事前にオペランドデータを読み込む先読みにより、ロードの読み込み時間を短縮する先読み効果が得られる。
【０１２８】
本キャッシュ制御装置では、オペランドキャッシュにヒットしたロード命令に対しては先読みを行わず、前記固定アドレスアクセス・ロード命令に対する効果を得られない先読みを行わないことにより、無駄な先読みを抑止する効果がある。
（２） 実行毎にロードアドレスが変化するロード命令である可変アドレス・ロード命令の場合、次回に前記ロード命令が実行されるロードアドレスがオペランドキャッシュに登録されていない可能性が高く、先読みが有効である。
【０１２９】
本キャッシュ制御装置では、オペランドキャッシュにミスした時に先読みアドレス予測を開始し、かつ先読みアドレス予測が成功したことが確認されるまで、オペランドデータの先読みを行わずに先読みアドレス予測のみを行うことにより、成功しない可能性の高い先読みを行わずに先読み成功率を向上させると共に、先読み実行頻度を下げる効果がある。
（３） 前記可変アドレス・ロード命令のアドレス変化には種々の傾向があり、単一のロードアドレス予測方式では高い先読み成功率を得られない。本方式では、複数の先読み方式である「固定間隔アドレス予測方式」あるいは「アドレス組予測方式」をそれぞれの予測が失敗した場合に切り替えることにより、前記可変アドレス・ロード命令のアドレス変化傾向に合った方式を動的に判断でき、先読み成功率向上効果がある。
（４） 連続する２回のロード要求のロードアドレス組であるアクセス履歴テーブルにより先読みアドレスを生成する「アドレス組予測方式」を用いた場合、前記アクセス履歴テーブルのアドレス組の数が容易に増加するという問題がある。本発明では固定間隔アドレス予測方式で先読みミスした場合にアドレス組予測方式を使用することで、非局所的な連続空間へのアクセスや、非局所的な一定間隔のアクセスを行う命令に対しては「固定間隔アドレス予測方式」によりアドレス予測を行い、前記固定間隔アドレス予測方式では先読みの成功しない不連続なアクセスを行う命令についてのみ「アドレス組予測方式」によってアクセス履歴テーブルを使用する。本方式により、先読みに必要なアクセス履歴テーブルの容量を小さく抑える効果がある。
（５） 複数の先読み方式を備え、先読み方式を切り替えて用いた先読み制御装置において、先読み方式の決定までの期間の先読みミスにより先読み成功率が低下する。本発明によるキャッシュ制御装置では、複数の先読みアドレス予測を同時に実行し、先読みの成功した方式により、後続の先読みを行うことにより、先読み方式の確定までの期間を短縮し、先読み成功率を向上させる効果がある。
（６） 規則的な順序によるアドレス空間のアクセスを行う場合は先読みが成功する可能性が高いが、先読みにより読み出したデータは１度使用されるだけで、再度使用されることの無い非局所的なデータである可能性が高い。従って、先読みアドレス予測が成功した場合に読み込みデータをオペランドキャッシュに登録すると、オペランドキャッシュに１度しか使用されないデータが登録されるために、小容量のオペランドキャッシュから、局所的に頻繁に利用されるデータが追い出され、オペランド・キャッシュのミスが増加する要因となりえる。
【０１３０】
キャッシュに１度しか使用しないデータが登録される、あるいは先読み失敗による一度限りあるいは一度も使用されないデータをキャッシュに登録することをキャッシュ汚染と呼ぶと、先読み機能を持つキャッシュ制御装置の設計においては、キャッシュ汚染を避けることが重要となる。
【０１３１】
本発明においては、先読みにより読み込んだデータをオペランドキャッシュに登録しないことにより、前記キャッシュ汚染を防ぎ、オペランドキャッシュを有効に使用することが可能となり、結果としてオペランドキャッシュのヒット率を向上させる効果を得られる。
（７） ロード命令のロードアドレスの変化する傾向は命令毎に異なり、単に命令処理装置から発行されたロード命令のロードアドレスを観察するだけでは正確な先読み予測が困難である。本発明では、命令キャッシュに各命令毎の先読み方式および先読み状態を格納し、先読みを行うか否か、あるいはどのような先読み方式を用いるかという情報を各命令毎に設定し、アクセス挙動が異なる命令が同一のオペランドデータのアドレスにアクセスした場合にも、それぞれの命令のアクセス挙動に応じたオペランドデータの先読みを実行可能にし、オペランドデータの先読み成功率向上効果がある。
（８） 先読み予測の成功あるいは失敗をロード命令の実行毎に判断することと、先読み失敗してから次に先読みによるアドレス予測が成功するまで、先読みによる主記憶あるいはオペランドキャッシュへのアクセスを行わないことにより、先読み失敗による無駄なメモリアクセスが発生せず、限られたメモリアクセス帯域を有効に使用することで、装置全体のメモリアクセス性能が向上するという効果が得られる。
（９） ソフトウェアの多重ループにおいては、最も内側のループが完了し、再度最も内側のループに実行が移る時にロードアドレスの連続性が崩れ、前記ループへの再入後２回目以降の繰り返しにおいては、再び以前と同様な連続的なアクセスが再開されることがある。本方式においては、先読みが成功している状態では、１度の先読み失敗による先読み方式を切り替えず、２度連続あるいは決められた回数の先読みが失敗して後に先読み方式を切り替えることにより、多重ループの最内側ループ完了後の最内周ループへの再入時に先読み方式が切り替わらず、無駄な先読み方式の切り替えを抑え、先読み成功率を向上させる。
（１０） ソフトウェアにおいては、コードサイズがデータサイズより小さいことが多いことと、本発明では命令毎に先読み予測を行うこととから、読みだすアドレス毎に先読み予測を行う方式よりも少ないハードウェア量にて、より高い先読み成功率を得られる効果がある。
（１１） 本発明では命令キャッシュ内の前回の予測アドレスと、ロード要求のロードアドレスを比較することにより先読み成功あるいは失敗の判断をし、先読みアドレス予測に失敗した場合は先読みオペランドバッファを索引する動作を回避し、不要な先読みオペランドバッファのアクセスを削減する。先読みオペランドバッファの使用頻度の低下の効果により、先読みオペランドバッファの索引と登録が同時に発生することによる先読みオペランドバッファアクセス競合による待ち合わせの発生頻度が低下し、メモリアクセス性能向上が得られる。
（１２） 先読みオペランドバッファ内に先読みアドレス予測により生成された予測アドレスと、先読みアドレス予測の元となった命令の命令アドレスとを保持し、前記命令アドレスと異なる命令アドレスを持つ命令が前記オペランドバッファ内の予測アドレスと一致するロードアドレスに対してロード要求を発行した場合、前記ロードアドレスが複数の命令により使用されていることをキャッシュ制御装置が検出し、前記ロードアドレスの読み出したデータをオペランドキャッシュに登録し、複数の命令により使用される頻繁に使用される局所的なデータをキャッシュに登録することで、局所的なデータと非局所的なデータを区別し、オペランドキャッシュのヒット率を低下させることなく先読みを行う効果を有する。
【図面の簡単な説明】
【図１】本発明の一実施形態の情報処理装置の構成を示すブロック図である。
【図２】本発明の一実施形態の情報処理装置の基本動作を示す表である。
【図３】本発明の一実施形態の情報処理装置における先読み方式である固定間隔アドレス予測方式を示すブロック図である。
【図４】本発明の一実施形態の情報処理装置における先読み方式であるアドレス組予測方式を示すブロック図である。
【図５】本発明の一実施形態の情報処理装置における先読み方式の状態遷移図である。
【図６】本発明の一実施形態の情報処理装置の動作を示すフローチャートである。
【図７】本発明の一実施形態の情報処理装置の動作を示すフローチャートである。
【図８】本発明の一実施形態の情報処理装置における命令キャッシュの変形例である。
【図９】Ｃ言語で記述されたプログラムの一例を示す図である。
【図１０】図９のＣ言語記述における繰り返しループの部分の仮想マシン命令への展開後の命令コードを示す図である。
【図１１】図１０の行Ｌ８のロード命令のメモリアクセス履歴を示す図である。
【図１２】「弱い先読み確定状態」を設けた場合の本発明の一実施形態のキャッシュ制御装置の動作を示す図である。
【図１３】Ｃ言語で記述されたプログラムの一例を示す図である。
【図１４】図１３のＣ言語記述における繰り返しループの部分の仮想マシン命令への展開後の命令コードを示す図である。
【図１５】図１４の行Ｌ８のロード命令のメモリアクセス履歴を示す図である。
【符号の説明】
１００ 命令処理装置
２００ 命令キャッシュ
２０１ 命令アドレス格納領域
２０２ 命令格納領域
２０３ ロードアドレス格納領域
２０４ 予測アドレス格納領域
２０５ 先読み状態格納領域
２０６ 先読み方式格納領域
２１０ 記憶テーブル
３００ キャッシュ制御装置
４００ オペランドキャッシュ
５００ 主記憶装置
６００ 先読みオペランドバッファ
６０１ 先読みアドレス格納領域
６０２ 命令アドレス格納領域
６０３ データ有効フラグ格納領域
６０４ データ格納領域
６１０ 記憶テーブル
Ｓ１００〜Ｓ５５０ ステップ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an information processing apparatus including a cache, and more particularly to an information processing apparatus including an instruction cache and an operand cache and performing data prefetching.
[0002]
[Prior art]
The information processing device incorporates a small-capacity but high-speed memory device that can read data into the CPU as an instruction processing device at a higher speed than the main storage device, and temporarily holds the data read from the main storage device. Often, a method of reading out frequently accessed data at high speed to shorten the average memory read time is adopted. Also, the cache performs reading, called line size, which is larger than the data size requested by the instruction processing device at a time, and registers, searches, replaces, and deletes in units of writing. In response to a load request to a plurality of consecutive addresses, a subsequent load request is already registered in the cache by data read by the first load request, that is, there is an effect of speeding up memory access by hitting.
[0003]
Furthermore, the cache may be separated into an instruction cache that holds some recently executed program instructions and an operand cache that holds some operand data stored in main storage. The access behavior to the cache can be roughly classified into (1) access to a local address, (2) access to a non-local continuous address space, and (3) access to a non-local address at a fixed interval. (4) Non-consecutive access in which the next address changes according to the contents of the previously accessed address, such as (4) access to a list-type data structure.
[0004]
In general, when the CPU reads an instruction to execute a program, access to the main storage device is local access in (1), whereas access to operand data is (2) and (3). , (4) are often non-local accesses. The cache hit rate is high for the type (1) access, but extremely low for the types (2), (3) and (4). Further, in the accesses of the types (2), (3) and (4), since the capacity of the operand data read into the cache is larger than the actual cache capacity, if all accessed operand data is registered in the cache, the access frequency May be flushed from the cache, and the cache hit rate may be further reduced. Therefore, the operand cache has a lower hit rate than the instruction cache, and the effect is small even if the cache capacity is increased.
[0005]
There is an information processing apparatus that prefetches operand data in order to reduce the load time of data that is not frequently accessed in the above non-local access and that is less likely to hit the operand cache.
[0006]
Before a load request is issued from the CPU, an address to be loaded next time is predicted, data of the address is read from the main storage device in advance, and the data is held in a high-speed storage device. Data can be read from the storage device, and the time required to load the operand data can be reduced.
[0007]
In JP-A-07-21838, a set of a load address of a preceding load instruction and a load address of a subsequent load instruction is registered in an access history table in a memory access history, and an instruction of a load address matching the address of the preceding load instruction is executed. Discloses a data prefetch control device for prefetching operand data at an address of a subsequent access instruction in an access history table.
[0008]
In the data read-ahead control device according to the prior art, when accessing a continuous memory space, one entry of the access history table is used for almost all load requests. A large-capacity access history table for storing the history table is required.
[0009]
In general, even when a plurality of instructions access the same operand data, if the instructions are different, that is, if the addresses on the main memory where the respective instructions are stored, that is, the instruction addresses are different, In many cases, the access behaviors of the plurality of instructions are different. Therefore, in the data prefetch control device in the conventional device, when successive loads to the target address are issued from the same instruction, the subsequent load address is likely to succeed in the prefetch prediction, but the two consecutive If the load is issued from a different instruction, the load address prediction is likely to fail, and the prefetch success rate decreases. Therefore, in the data read-ahead control device according to the related art, unnecessary read-ahead data may be loaded into the cache due to the read-ahead having a low success rate, and the hit rate of the operand cache may be reduced.
[0010]
[Problems to be solved by the invention]
As described above, the conventional information processing apparatus has the following four problems.
(1) In order to compensate for a decrease in the hit rate of the operand cache due to non-local access, a load address to be accessed next time is used by using an access history table that stores a history of a set of load addresses of a preceding load instruction and a subsequent access instruction. Was used to predict the operand data, but one entry of the access history table is used for almost all loads, so that the capacity of the access history table is enormous to obtain a necessary prefetch success rate. It becomes.
(2) When the preceding load instruction for the target address is issued from the same instruction having the same instruction address, the operation is often simple, and a certain prefetch success rate can be secured. If the load instruction is issued from an instruction having a different instruction address, the behavior of the change of the load address becomes complicated, so that the prefetch success rate decreases.
(3) Unused data due to the failure of the prefetch load address prediction is registered in the small-capacity operand cache, so that frequently used data is flushed out, and the cache hit rate is reduced.
(4) A load request for prefetching unused data due to incorrect prefetch load address prediction causes a subsequent load request for actually used data to wait, thereby increasing the access time of the load request, and As a result, memory access performance is reduced due to waste of a limited memory access band.
[0011]
An object of the present invention is to provide an information processing apparatus which does not require a huge storage capacity, maintains a high prefetch success rate, and can suppress waste of cache capacity and memory access bandwidth due to incorrect prefetch load address failure. With the goal.
[0012]
[Means for Solving the Problems]
In order to solve the above problems, an information processing device of the present invention includes a main storage device that stores a plurality of instructions and a plurality of operand data,
Instruction processing means for executing each of the instructions;
An operand cache holding a plurality of the operand data,
Registers some of the instructions recently executed by the instruction processing means among the instructions, registers the registered instruction with the address of the registered instruction on the main storage device, and stores the registered instruction in the main storage. When the instruction is a load instruction for loading operand data on a device into the instruction processing means, the address of the operand data on the main storage device when the registered instruction was executed last time, and the registered instruction Address of the operand data predicted to be accessed the next time execution is performed on the main memory, a prefetch address prediction method when the predicted address is predicted, and a prefetch state of the registered instruction And an instruction cache capable of storing each of the registered instructions.
If the instruction executed by the instruction processing means is a load instruction and the address of the operand data to be loaded changes each time the instruction is executed, the instruction is executed each time the instruction is executed by the instruction processing means. Predicts the address of the operand data to be accessed the next time it is executed on the main storage device, and the look-ahead where the address of the actually accessed operand data matches the predicted address stored in the instruction cache A prefetch method is set in the instruction cache, and the prediction address is generated in the prefetch method stored in the instruction cache each time the instruction is executed by the instruction processing means, and an operand of the prediction address is generated. And a cache control unit that executes data prefetching.
[0013]
Further, in another information processing apparatus according to the present invention, the predicted address, the address of the load instruction for accessing the predicted address on the main storage device, the operand data of the predicted address, and the operand data to be stored are valid. A look-ahead operand buffer for storing a data valid flag indicating whether there is
If the address of the operand data loaded by the instruction executed by the instruction processing means in the main storage device is the predicted address of an instruction other than the instruction, the cache control means sets the operand data in the instruction Is not executed, and the operand data is stored in the operand cache.
[0014]
In another information processing apparatus according to the present invention, each time a load instruction is executed by the instruction processing means, the address of the operand data requested to be accessed by the instruction processing means on the main storage device and the instruction cache are stored. A fixed interval, which is an address obtained by adding the difference between the stored operand data at the time of execution of the previous load instruction and the address on the main storage device to the address requested to be accessed by the instruction processing means and the predicted address Each time a load instruction is executed by the instruction processing means, the address of the operand data to which an access request was previously issued from the instruction processing means is used as an old load address. The old load address as the new load address A combination of the the dress new load address Access history table And if the address of the operand data requested to be accessed by the instruction processing means this time matches the old load address stored in the access history table, a new load address corresponding to the old load address is stored. Is used as the look-ahead method.
[0015]
Further, in another information processing apparatus according to the present invention, when determining the prefetching method, the cache control means may use any one of the fixed interval address prediction method and the address group prediction method as the prefetching method. And switches the prefetching method stored in the instruction cache until the address of the current operand data matches the predicted address stored in the instruction cache.
[0016]
Further, in another information processing apparatus according to the present invention, when determining the prefetching method, the cache control means uses both the fixed interval address prediction method and the address set prediction method as the prefetching method, respectively. A predicted address is calculated, and a prefetch method in which the address of the current operand data matches the predicted address is stored in the instruction cache.
[0017]
Further, in another information processing apparatus according to the present invention, the predicted address storage area is deleted from the instruction cache, and a prediction predicted previously based on an address on the main storage device of the operand data when the load instruction is executed last time. An address is generated, the address is compared with the address of operand data to be actually accessed, the success or failure of prefetch is determined, and a prefetch method is determined.
[0019]
Further, in another information processing apparatus according to the present invention, the prefetch state is deleted from the instruction cache, and regardless of the prefetch state, a miss in the operand cache, and the data obtained by the prefetch for the next load address only when the prefetch is successful. Perform a read.
[0020]
Further, in another information processing apparatus according to the present invention, in the instruction cache, when the prefetch address prediction is once successful and the prefetch is successful, the prefetch is not performed once or a plurality of prefetch address prediction failures less than a predetermined number of times. The prefetching is continued without suppression, and the prefetching method is switched when the prefetching address prediction fails more than a specified number of times.
[0021]
In the information processing apparatus according to the present invention, the success rate of the prefetch prediction is improved by incorporating the prefetch mechanism into the instruction cache. A prefetch success rate improvement method will be described using the instruction sequence of the C language description shown in FIG.
[0022]
FIG. 14 shows an instruction code after the repetition loop part (1) in the C language description of FIG. 13 is expanded into a virtual machine instruction. In FIG. 14, FIG. 15 shows load instructions and load addresses issued by the instruction processing device, address intervals for each load request to the cache control device, and load address intervals for each instruction.
[0023]
The operand address intervals in the load execution order in FIG. 15 are +100, -19, +100, and -19, and the load address changes are discontinuous, and the fixed interval access prediction does not succeed. On the other hand, looking at the load address from the same instruction, the load memory [a + r (cnt)] instruction and the load memory [b + r (cnt)] instruction are fixed-interval address accesses that increase by +1. Succeeds. Therefore, by performing address prediction for each instruction, the success rate of load address prediction is improved.
[0024]
In the above example, seven instructions access 2,000 addresses, and the number of instructions is only 7/2000 = 0.35% of the access address. Instead, by performing prefetch prediction for each instruction, the size of the predicted address holding buffer can be significantly reduced, and the information processing apparatus of the present invention can greatly reduce the amount of hardware.
[0025]
Further, in the information processing apparatus according to the present invention, the prefetching of the operand data is performed only when the instruction executed by the instruction processing means is a load instruction and an instruction in which the address of the operand data to be loaded changes each time the instruction is executed is executed. The prefetch is not executed by other load instructions, and a high prefetch success rate can be obtained even in a small-capacity storage area for prefetch.
[0026]
Further, in the information processing apparatus of the present invention, the prefetch method and the prefetch state for each instruction are stored in the instruction cache, and whether to perform prefetch or what prefetch method is used is set for each instruction. By doing so, in the information processing apparatus of the present invention, it is possible to execute the prefetching of the operand data according to the access behavior of each instruction, and it is possible to keep the prefetching success rate high.
[0027]
Further, in the information processing apparatus according to the present invention, during a prefetch test in which the prefetch address predicted by the previous load instruction does not match the load address at the time of execution of the next instruction, loading into the memory by prefetch is performed. By suppressing the request, useless memory access does not occur, and it is possible to prevent waste of the memory bandwidth due to prefetching that is unlikely to succeed.
[0028]
In addition to the above, in the information processing apparatus of the present invention, when prefetching is successful and data exists in the prefetch buffer, an access to data in the prefetch buffer by another instruction is detected, and the prefetch data is referenced from another instruction. If the prefetched data is not referred to by other instructions, that is, if it is non-local data that is discarded, the data is registered in the operand cache. A large capacity operand cache can be used efficiently.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an information processing apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings. In all the drawings, components denoted by the same reference numerals indicate the same components.
[0030]
FIG. 1 is a block diagram illustrating a configuration of the information processing apparatus according to the present embodiment. The information processing device according to the present embodiment includes an instruction processing device 100, an instruction cache 200, a cache control device 300, an operand cache 400, a main storage device 500, and a prefetch operand buffer 600. The instruction cache 200 includes an instruction address storage area 201, an instruction storage area 202, a load address storage area 203, a predicted address storage area 204, a prefetch state storage area 205, and a prefetch scheme storage area 206. It has a plurality of storage tables 210. The prefetch operand buffer 600 includes a plurality of storage tables 610 each having a set of a prefetch address storage area 601, an instruction address storage area 602, a data valid flag storage area 603, and a data storage area 604.
[0031]
The main storage device 500 stores a plurality of instructions executed by the instruction processing device 100 and a plurality of operand data accessed from the instructions. The instructions include a load instruction for reading operand data into the instruction processing device 100, a memory access instruction including a store instruction for writing operand data to the main storage device 500, and a non-memory access instruction that does not read or write to the main storage device 500. They are roughly divided into instructions.
[0032]
The instruction processing device 100 reads, analyzes, and executes the instruction via the cache control device 300. When the analyzed instruction is a memory access instruction, the instruction processing device 100 issues a memory access request to the cache control device 300. In the instruction cache 200, an instruction recently executed by the instruction processing apparatus 100 and an instruction address of the instruction are stored in an instruction storage area 202 and an instruction address storage area 201 of each storage table 210, respectively. When receiving an instruction read request from the instruction processing device 100, the cache control device 300 refers to the instruction address stored in the instruction address storage area 201 in each storage table 210 of the instruction cache 200, and executes the instruction of the instruction read request. It is checked whether there is one that matches the address, and if there is a matching storage table 210, the instruction is read from the instruction storage area 202 in the matched storage table 210.
[0033]
If an instruction address that matches the instruction address of the instruction read request is not registered in the instruction cache 200, the cache control device 300 sends a read request to the main storage device 500, and the read data returned from the main storage device 500. That is, the instruction and the instruction address of the instruction read request are registered in the instruction cache 200, and the read data is returned to the instruction processing device 100.
[0034]
The instruction processing device 100 processes the read data returned in response to the instruction read request, that is, the instruction, and when the instruction is a load instruction, generates a load request including the instruction address and the load address of the instruction. It is sent to the instruction cache 200 via the cache control device 300.
[0035]
The instruction cache 200 indexes the instruction cache 200 based on the instruction address of the load request received from the instruction processing apparatus 100, and stores a set of load address storage areas in which an instruction address matching the instruction address is stored in the instruction address storage area 201. In 203, the load address of the load request is registered. When registering the load address, a predicted address storage area 204 that holds the predicted load address, a prefetch state storage area 205 that indicates one of three states of prefetch suppression, prefetch test, and prefetch determination, a fixed interval address prediction method, Alternatively, the prefetching method storage area 206 indicating one of the address group prediction methods is set at the same time.
[0036]
The setting method of each storage area in the storage table 210, the presence or absence of registration in the operand cache 400, the presence or absence of registration of a prefetch prediction address in the prefetch operand buffer 600, the presence or absence of execution of a read operation for the prefetch prediction address, the access history table 700 The basic operation of the information processing apparatus according to the present embodiment, such as the presence or absence of registration in the information processing apparatus, will be described below with reference to FIGS.
[0037]
Condition names C1a to C4 in FIG. 2 are symbols attached to conditions for determining each operation. “O-Cache” indicates whether the index result of the operand cache 400 by the load request is a hit (Hit) or a miss (Miss), and “P-Buffer” is a prefetch operand by the load request. The index result of the buffer 600 indicates whether the result is a hit (Hit) or a miss (Miss). The “old state” indicates a prefetch state of the storage table 210 holding the currently executed load instruction in the instruction cache 200. The pre-reading state before the execution of the instruction stored in the storage area 205 is shown, and the “old method” indicates the pre-reading method before the instruction stored in the pre-reading method storage area 206 of the storage table 210. .
[0038]
The “new state” indicates the state of the pre-reading state storage area 205 of the storage table 210 after the instruction is executed, and the “new method” indicates whether the pre-reading method storage area 206 is changed. The “predicted address” indicates whether or not to update the value of the prefetched predicted address storage area 204 of the storage table 210 by executing an instruction. The “OC registration” indicates that the data read by the load request is stored in the operand cache. 400 indicates whether to register. However, this “OC registration” is described as completed if the operand cache 400 has been hit.
[0039]
“P registration” indicates whether or not to register the load address predicted by the load instruction in the prefetch prediction address storage area 601 of the prefetch operand buffer 600, and “P execution” indicates that the prefetch request for the prefetch prediction address is "History registration" indicates whether to issue an address set to the operand cache 400 or the main storage device 500, and "history registration" indicates whether to register an address set in the access history table 700.
[0040]
In the information processing apparatus of the present embodiment, when the cache control device 300 registers the load address of the load request from the instruction processing device 100 in the load address storage area 203 of the instruction cache 200, the cache control device 300 satisfies the load address under the conditions C1a to C1g. Is hit in the operand cache 400, that is, if “O-Cache” is “Hit”, “new state” is set to “suppress”, that is, “prefetch suppression” is set in the prefetch state storage area 205. I do. The fact that the load hits the operand cache indicates the locality of the data, and the local data is excluded from the target of prefetching. Therefore, when the O-Cache hits, the prefetching is suppressed.
[0041]
In the conditions C2a to C2c, “O-Cache” is “Miss” and “P-Buffer” is “Miss”, that is, the cache control device 300 indexes the prefetch operand buffer 600 by the current load address, A case where there is no storage table 610 in which the load address matches the predicted address in the prefetch address storage area 601 is referred to as “prefetch miss”. In the case of “read-ahead mistake”, “new state” is set to “under test”, that is, “pre-reading test” is set in the pre-read state storage area 205. Further, the "new method" is "changed", that is, the look-ahead method is changed, the changed look-ahead method is registered in the look-ahead method storage area 206, the look-ahead address is calculated in accordance with the changed look-ahead method, and the look-ahead address is predicted. In addition to registering in the address storage area 204, a prefetch prediction address is registered in the prefetch operand buffer 600. The conditions C2a to C2c are "prefetch failure", and the data read at the prefetch predicted address is not executed, and data invalid (off) is set in the prefetch data valid flag storage area 603. Further, the cache control device 300 issues a read request for the current load address to the main storage device 500, registers the read data in the operand cache 400, and supplies the read data to the instruction processing device 100.
[0042]
The cache control device 300 indexes the look-ahead operand buffer 600 using the current load address, and determines that there is a storage table 610 in which the load address matches the predicted address in the look-ahead address storage area 601 as a “look-ahead hit”. Assume that the instruction address storage area 602 of the storage table 610 in which the "prefetch instruction hit" is the "prefetch hit" matches the instruction address of the load instruction.
[0043]
In the case of a "prefetch own instruction hit" (conditions C3a to C3f), the information processing apparatus according to the present embodiment has two types of operations: (1) an operation based on the current load instruction and (2) an operation based on the prefetch address prediction. The operation is performed.
[0044]
(1) Operation based on the current load instruction: The look-ahead address storage area 601 of the storage table 610 of the look-ahead operand buffer 600 is indexed by the current load address, and an address that matches the current load address is present and stored. When the value of the data valid flag storage area 603 in the table 610 is valid (ON), the cache control device 300 reads the data of the data storage area 604 in the storage table 610 that matches, and reads the data of the instruction processing device 100 To return.
[0045]
When there is no storage table 610 that matches the index, or when the match indicates that the data valid flag is invalid (off), the cache control device 300 reads the data into the main storage device 500. A request is issued, and the returned data is supplied to the central processing unit 100.
[0046]
Regardless of whether the data valid flag is on or off, the contents of the matched storage table 610 become invalid by turning off a storage table valid flag (not shown) in the storage table 610, and are reused for subsequent prefetching. You. The read data is not registered in the operand cache 400 because the prefetch has succeeded. A storage table valid flag (not shown) is always set to ON when a predicted address is registered in the operand cache 400. The storage table valid flag of the storage table 610 whose contents are not registered is off, and is not an index target of the prefetch operand cache 600.
[0047]
(2) Operation based on prefetch address prediction: "prefetch determination" is set in prefetch state storage area 205, and a prefetch address predicted according to the prefetch scheme stored in prefetch scheme storage area 206 is set in prefetch prediction address storage area 204; The predicted look-ahead address is registered in the look-ahead predicted address storage area 601, and the operand cache 400 is indexed by the predicted look-ahead address. If the index result hits the operand cache 400, the data valid flag storage area 603 is set to off, and a prefetch request is not issued to the main storage device 500. If the index result is a mistake, the prefetch request is issued to the main storage device 500, the read data is registered in the data storage area 604, and the data valid flag storage area 603 is turned on.
[0048]
When both the operand cache 400 and the prefetch buffer 600 miss (condition C2b), the previous load address is registered as the ongoing load address and the current load address is registered as the predicted load address in the access history table 700 of FIG. Since the number of address sets that can be registered in the access history table 700 is finite, when there is no space available for registering the address sets in the access history table 700, the previously registered old address sets are deleted and registered. When the access history table 700 is implemented by a cache structure of a direct map, replacement with an address set for the same set address is performed, and when implemented by a set associative method, a set to be replaced by an LRU (least recently used) algorithm is used. Is determined, and when implemented in a ring buffer, replacement with the oldest registered address set is performed.
[0049]
In the case of a “prefetch hit”, and when the instruction address in the instruction address storage area 602 of the hit storage table 610 does not match the instruction address of the load instruction (condition C4), the load address is frequently referred to by a plurality of instructions. As shown in FIG. 2, the cache control device 300 sets the “new state” to “inhibited”, that is, sets “prefetch inhibition” in the prefetch state storage area 205, as shown in FIG. A load request is issued to the device 500, the read data is registered in the operand cache 400, and the read data is returned to the instruction processing device 100.
[0050]
As described above, in the information processing apparatus according to the present embodiment, the operand data accessed by the load instruction whose operand address does not change, or the operand data accessed by a plurality of instructions are the operands that are locally frequently accessed. The operand data is regarded as data, and the operand data is registered in the operand cache 400. However, when the load address is changed every time the instruction is executed, the cache control device 300 predicts the load address to be executed next by the load instruction, and if the prediction is successful, the cache address is used next. Predict the load address to be executed and execute prefetching.
[0051]
The predicted address of the prefetched operand data is stored in the predicted address 204 of the storage table 210 in which the instruction is stored, and the predicted address, the load address, the instruction address of the load instruction, and the operand The data is stored in the prefetch address storage area 601, the instruction address storage area 602, and the data storage area 604 of the prefetch operand buffer 600, respectively.
[0052]
The cache control device 300 predicts the load address by using two methods, the “fixed interval address prediction method” and the above-mentioned “address group prediction method”, and prefetches the operand data. The “fixed interval address prediction method” is, as shown in the following equation (1), the difference between the old load address when the previous load instruction was executed and the new load address when the current load instruction was executed. In this method, an address obtained by adding a difference to a new load address is used as a predicted address.
[0053]

As shown in FIG. 4, when a load request is issued from the instruction processing device 100, the cache control device 300 sets the load address read from the load address storage area 203 of the instruction cache 200 as an old load address, and Using the processing request load address requested from the processing device 100 as a new load address, the above formula (1) is calculated, and the predicted address is calculated. The aforementioned “fixed interval address prediction method” is a look-ahead method that is effective when successively accessing array elements such as an array or a structure in software.
[0054]
As shown in FIG. 3, the “address group prediction method” refers to a load address read from the load address storage area 203 of the instruction cache 200 as an old load address, and a processing request received from the instruction processing apparatus 100. Each time a load request is issued from the instruction processing device 100, the combination of the old load address and the new load address is stored in the access history table, and the operand data requested by the instruction processing device 100 this time is stored. Is the same as the old load address stored in the access history table, the new load address corresponding to the old load address is used as the predicted address. The "address group prediction method" is a look-ahead method effective when a data structure in which arrays are connected by pointers or addresses at irregular intervals, which is a list-type data structure, are accessed in a fixed order.
[0055]
The cache control device 300 first performs load address prediction using the “fixed interval address prediction method”, and prefetches the load address using the “fixed interval address prediction method” while the address prediction is successful. When the prediction fails, the prefetching method is changed to the "address group prediction method" to predict the load address. That is, in the information processing device of the present embodiment, the cache control device 300 can switch the prefetching method every time the address prediction fails.
[0056]
Further, the information processing apparatus of the present embodiment holds one of the three states of the above-described “prefetch suppression”, “during prefetch test”, and “prefetch confirmation” for each instruction in the instruction cache 200. The "prefetch suppression" state is a state in which the prefetch of the operand data for the instruction is not performed. The “pre-reading test in progress” state is a state where the pre-reading of the cache control device 300 has failed. The “read ahead confirmation” state is a state in which the read ahead by the cache control device 300 is successful. In the case of the “prefetching fixed” state, the cache control device 300 performs a prefetch address prediction of the load address according to the setting contents of the prefetch method storage area 206 and executes the prefetch.
[0057]
FIG. 5 shows a state transition of a prefetch state of an instruction executed by the instruction processing device 100. When the hit of the operand cache 400 is continued, the prefetch state of the instruction remains in the “prefetch suppression state” in which the transition T1 is repeated and the prefetch is not executed. If a miss occurs in the operand cache 400 in the "prefetch suppression" state, the prefetch state of the instruction shifts to "during prefetch test" by transition T2. If a miss occurs in the prefetch operand buffer 600 during “prefetch test”, the prefetch state of the instruction repeats the transition T6.
[0058]
In “during pre-reading test”, when the load address matches the predicted address stored in the pre-read address storage area 601 of the pre-read operand buffer 600, that is, a hit occurs in the pre-read operand buffer 600, and the instruction address of the load instruction is When the instruction address in the instruction address storage area 602 of the prefetch operand buffer 600 matches, it is determined that the prefetch has succeeded, and the prefetch state of the instruction shifts to “determination of prefetch” by the transition T3. In the "prefetching confirmation", the prefetching state in the case where the prefetching success is continued repeats the transition T4.
[0059]
If the prefetching has failed in "prefetching fixed", the prefetching state of the instruction shifts to "during prefetching test" by transition T5. If the instruction address of the load instruction being executed does not match the instruction address in the instruction address storage area 602 of the prefetch operand buffer 600 in “prefetch determination”, the prefetch state of the instruction is changed to “prefetch” by the transition T8. Move to "Suppression".
[0060]
In the "pre-reading test" and the "pre-reading determination", (1) when the load address of the load instruction hits the operand cache 400, and (2) the operand address from the load or store instruction of a different instruction address is during the pre-reading test or Any one of three conditions: when an instruction in a prefetched fixed state hits the registered prefetch operand buffer 600, or (3) when operand addresses of two consecutive load instruction executions from the same load instruction match. As a result, the prefetch state of the instruction shifts to "prefetch suppression" by transitions T7 and T8, respectively.
[0061]
Next, the operation of the information processing apparatus according to the present embodiment will be described with reference to FIGS. 6 and 7 are flowcharts showing the operation of the cache control device 300 in the information processing device according to the present embodiment.
[0062]
When the cache control device 300 receives an instruction read request from the instruction processing device 100 (step S100), the instruction address stored in the instruction address storage area 201 of each storage table 210 of the instruction cache 200 contains the instruction read request. It is checked whether or not there is a match with the designated instruction address, that is, whether or not there is a hit in the instruction cache 200 (step S110).
[0063]
If no hit occurs in the instruction cache 200, the cache control device 300 reads the instruction from the main storage device 500, supplies the instruction to the instruction processing device 100, and stores the instruction and the instruction address in the instruction cache 200. It is stored in the area 202 and the instruction address storage area 201 (step S200).
[0064]
If there is no empty entry for registering the instruction in the instruction cache, the instruction cache 200 replaces the entry with an algorithm such as LRU (Least Recently Used). When registering a new instruction in the instruction storage table 210, the fixed-interval address prediction method is selected as the pre-reading method, and the pre-reading state is set as the pre-reading state.
[0065]
The instruction processing device 100 analyzes the instruction supplied from the cache control device 300, and the cache control device 300 checks whether or not the instruction analyzed by the instruction processing device 100 is a load instruction (step S210). If the instruction is not a load instruction (No branch at step S210), a store request is sent to the operand cache 600 or the main storage device 500 at the time of a store instruction, and the operation is performed according to the instruction if it is a non-memory access instruction.
[0066]
If the instruction is a load instruction, the cache control device 300 stores the load address, which is the load destination address of the instruction, in the load address storage area 203 of the storage table 210 that stores the instruction (step S220: load). It is checked whether the load address has hit the operand cache 400 (step S230). If the load address hits the operand cache 400, "prefetch suppression" is set in the prefetch state storage area 205 of the storage table 210 storing the instruction (step S240), and the hit operand data is stored in the instruction table. The processing is returned to the processing device 100, and the processing ends.
[0067]
In step S230, if the load address misses the operand cache 400, the cache control device 300 reads the data of the load address from the main storage device 500 and stores it in the operand cache 400. "Pre-reading test" is set in the pre-reading state storage area 205 of the storage table 210 that supplies data and stores the instruction, and "fixed interval address prediction method" is set in the pre-reading method storage area 206 (step S250). .
[0068]
In step S260, an address obtained by adding the line address, which is a read unit of the operand cache 400, to the load address in the prefetch address storage area 601 of the storage table 610 of the prefetch operand buffer 600 and the prefetch address storage area 204 in the instruction cache 200 is predicted. The instruction address of the instruction is stored in the instruction address storage area 602 of the storage table 610 storing the predicted address, and the data valid flag of the data valid flag storage area 603 is turned off. Since the setting is performed during the prefetch test in step S260, the process ends without issuing a load request for the prefetch prediction address to the main storage device 500, that is, issuing a prefetch request.
[0069]
In step S260, if there is no unregistered area in the storage table 610 of the prefetch operand buffer 600, the storage table 610 is replaced with the registered storage table 610 by the LRU (Least Recently Used) algorithm or the ring buffer method.
[0070]
In step S110, when the instruction cache 200 is hit, the cache control device 300 supplies the instruction stored in the instruction storage area 202 of the instruction cache 200 to the instruction processing device 100 (step S120). If the instruction is a non-memory access instruction, the cache control device 300 ends the processing and waits for the next instruction read request (step S130).
[0071]
The cache control device 300 checks whether or not the instruction analyzed by the instruction processing device 100 is a load instruction (Step S140). If the instruction is not a load instruction, the instruction is a store because it has already been determined in step S130 that the instruction is a memory access instruction, and the cache controller 300 stores the operand data of the store instruction in the operand cache 400. It is checked whether or not there is a hit (step S500). If the operand of the store instruction hits the operand cache 400 in step S500, the cache controller 300 issues a store request to the operand cache 400 (step S510).
[0072]
When the operand of the store instruction misses the operand cache 400 in step S500, the cache control device 300 issues a store request to the main storage device 500 (step S520). Also, the cache control device 300 checks whether there is a table in which the address of the store request matches the predicted address stored in the prefetch address storage area 601 in each storage table 610 of the prefetch operand buffer 600, That is, it is checked whether or not there is a hit (step S530).
[0073]
If the address of the store request hits the look-ahead operand buffer 600, the cache control device 300 reads the instruction address stored in the instruction address 602 corresponding to the hit look-ahead address storage area 601 and reads the instruction address. Is checked in the instruction cache 200 (step S540).
[0074]
When the instruction address hits the instruction cache 200, it is an address used for a plurality of instructions of load and store, is a registration target of the operand cache 400, and is a prefetch state storage area of the hit storage table 210. “Prefetch suppression” is set in 205 (step S550).
[0075]
If the instruction is a load instruction in step S140, the cache control device 300 checks whether the load address hits the operand cache 400 (step S150). When the load address of the instruction hits the operand cache 400, the cache control device 300 reads data from the operand cache 400 and supplies the data to the instruction processing device 100 (Step S160). Further, this access is regarded as a local access, and "prefetch suppression" is set in the prefetch state storage area 205 corresponding to the instruction storage area 202 in which the instruction is stored (step S170). finish.
[0076]
Here, a match between the load address of the load request from the instruction processing device 100 and the prefetch address stored in the prefetch address storage area 601 of the storage table 610 of the prefetch operand buffer 600 is defined as a “prefetch hit”. In addition, a condition that a “prefetch hit” and an instruction address stored in the instruction address storage area 602 of the hit storage table 610 matches the instruction address of the load instruction is defined as a “prefetch first instruction hit”.
[0077]
If the load address misses in the operand cache 400 in step S150, it is checked whether or not there is a hit in the prefetch operand buffer 600 (step S300).
[0078]
The cache control device 300 checks the data valid flag of the storage table 610 that hits the prefetch operand buffer 600 (step S310), and if the data valid flag indicates data invalid (off), the cache control device 300 The data is read from the storage device 500 and supplied to the instruction processing device 100 (step S320). If the data valid flag indicates data valid (ON), the cache control device 300 stores the hit data storage area of the storage table 610. The data is read from 604 and supplied to the instruction processing device 100 (step S330).
[0079]
In steps S320 and S330, data read from the main storage device 500 or the prefetch operand buffer 600 is not registered in the operand cache 400.
[0080]
In step S340, the cache control device 300 checks whether it is a "prefetch own instruction hit" (step S340). When the load address is “prefetch own instruction hit”, the cache control device 300 determines that the prefetch is successful and sets “prefetch determination” in the prefetch state storage area 205 of the storage table 210 storing the instruction. (Step S350) A prefetch prediction address is obtained, and the prefetch prediction address is stored in the prediction address storage area 204 of the storage table 210 storing the instruction and the prefetch address storage area 601 of the hit storage table 610. The operand data in the main storage device 500 at the address is read into the data storage area 604, and the data valid flag in the data valid flag storage area 604 of the storage table 610 in which the prefetched operand data has been read is turned on (step S370).
[0081]
In step S340, if it is not a "prefetch self-instruction hit", the cache control device 300 considers the load address to be an address frequently accessed by a plurality of instructions, and stores the instruction in the storage table. “Pre-reading suppression” is set in the pre-reading state storage area 205 of step 210 (step S360).
[0082]
If the load address misses the prefetch operand buffer 600 in step S300, the cache control device 300 changes the prefetch method stored in the prefetch method storage area 206 (step S410), and stores the prefetch method. A predicted address is generated according to the changed prefetching method stored in the area 206, and the predicted address is stored in the predicted address storage area 204 of the instruction cache 200 and the prefetch address storage area 601 of the prefetch operand buffer 600 (step S420). .
[0083]
In step S430, the cache control device 300 reads data from the main storage device 500, supplies the data to the instruction processing device 100, and registers the read data in the operand cache 400.
[0084]
(Other Embodiments of the Invention)
Hereinafter, other embodiments of the present invention will be described. The following (A) to (F) are symbols indicating examples.
(A) An embodiment of a method of predicting the next load address by using a plurality of prefetching methods at the same time instead of performing prediction by switching a plurality of prefetching methods will be described below.
[0085]
A look-ahead method storage area is added to the storage table 610 of the look-ahead operand buffer 600, and a look-ahead method for generating a look-ahead address is set at the time of registration in the storage table 610. The operation when the cache control device 300 receives a load request from the instruction processing device 100 will be described below.
[0086]
Differences from the above embodiment are shown in (Difference 1) and (Difference 2).
[0087]
(Difference 1) When the load address of the load request misses the operand cache 400 and hits the prefetch operand buffer 600, the prefetch method in the prefetch method storage area 206 in the hit storage table 610 is changed to the instruction cache storage table 210. In the pre-reading method storage area, and when the content of the data valid flag storage area 603 is on, from the data storage area 604, and when the content of the data valid flag storage area 604 is off, the load request is transmitted from the main storage device 500. The read data is read and supplied to the instruction processing device 100. Since the data requested to be loaded is a prefetch hit, the data is not registered in the operand cache 400, but a prefetch address is predicted by the prefetch method, and the prefetch is executed and the read data is registered in the prefetch operand buffer 600 together with the predicted address. .
[0088]
(Difference 2) When the load address of the load request misses in the operand cache 400 and misses in the prefetch operand buffer 600, the next load address predicted by a plurality of prefetch methods is stored in the operand buffer 600. At the same time as the registration, the prefetching method is set in the prefetching method storage area of each storage table 610. Since the read-ahead for this load was a mistake, the read-ahead is not performed for the predicted read-ahead address, and the data valid flag storage area 604 is set to off.
[0089]
Except for the above two differences, the operation of the first embodiment is performed. According to the present embodiment, it is possible to shorten the period until the prefetch prediction succeeds.
(B) The following describes an embodiment in which the prediction address storage area 204 in the instruction cache 200 determines the success or failure of the prefetch prediction.
[0090]
By comparing the load address stored in the predicted address storage area 204 of the instruction cache 200 with the load address requested by the instruction processing device 100,
If the comparison results match, the prefetching is successful, and if they do not match, the prefetching fails. However, if the comparison result matches, but the storage table 610 for the predicted address corresponding to the prefetch operand buffer 600 does not exist, that is, after execution of the previous instruction and before execution of the current instruction, storage is performed by executing another instruction. When the table 610 is replaced, the operation is performed assuming that the prefetch data valid flag 603 is off. The success or failure of prefetching is determined based on the load address in the predicted address storage area 204 of the instruction cache 200 and the load address of the current load request. , And all the prefetch hits operate as the own instruction hit.
[0091]
By the above operation, the operation of the first embodiment is performed except that the success or failure of the prefetch address prediction is determined. According to this embodiment, the look-ahead operand buffer 600 is indexed only when the look-ahead address prediction succeeds, and when the look-ahead address prediction fails, the index of the look-ahead operand buffer 600 becomes unnecessary, and the load on the look-ahead operand buffer 600 is reduced. be able to.
(C) In another information processing apparatus of the present invention, an apparatus for deleting the prefetch state from the instruction cache and executing prefetch only when an error occurs in the operand cache and the prefetch succeeds regardless of the prefetch state. An example is shown below.
[0092]
In this configuration, since the prefetch state does not exist, the operation of the cache control device 300 is determined by a hit / miss to the operand cache 400 in response to the load request from the instruction processing device 100 and the success / failure of the prefetch address prediction. The following (Condition K1) to (Condition K4) are symbols indicating each operating condition.
[0093]
(Condition K1) When the operand cache 400 hits, a prefetch operation is not performed and a load request is made to the operand cache 400, and the read data is supplied to the instruction processing device 100.
[0094]
(Condition K2) When the operand cache 400 misses and the prefetch address prediction fails, the contents of the prefetch method storage area 206 are changed, the prefetch method is changed, a prefetch prediction address is generated according to the changed prefetch method, and the prediction address is calculated. It is set in the storage area 204. Under this condition, prefetching is not performed, and the data valid flag storage area 603 is set to off. Under this condition, the data read by the load request is registered in the operand cache 400. Further, the pre-update load address 203 and the load address of the load request are registered in the access history table 700 as a running load address and a predicted load address, respectively.
[0095]
(Condition K3) When the operand cache 400 misses, the prefetch address prediction is successful, and the data valid flag storage area 603 is off, the data requested to be loaded from the main storage device 500 is supplied to the read instruction processing device 100. Further, a prefetch address is predicted by the prefetch method in the prefetch method storage area 206, and a prefetch request is issued to the operand cache 400. If the prefetch request hits the operand cache 400, the prefetch process ends without prefetching. If the prefetch request misses the operand cache 400, a load request is transmitted to the main storage device 500, the read data is stored in the data storage area 604, the data valid flag 603 is turned on, and the prefetched predicted address is Is set in the predicted address storage area 204. Under this condition, the data read by the load request is registered in the operand cache 400.
[0096]
(Condition K4) When the operand cache 400 misses, the prefetch address prediction is successful, and the data valid flag storage area 603 is ON, the data requested to be loaded from the data storage area 604 is read and supplied to the instruction processing apparatus 100. Further, a prefetch address is predicted by the prefetch method in the prefetch method storage area 206, and a prefetch request is issued to the operand cache 400. If the prefetch request hits the operand cache 400, the prefetch process ends without prefetching. If the prefetch request misses the operand cache 400, a load request is transmitted to the main storage device 500, the read data is stored in the data storage area 604, the data valid flag 603 is turned on, and the prefetched predicted address is Is set in the predicted address storage area 204. Under this condition, the data read by the load request is not registered in the operand cache 400.
[0097]
Based on the operations specified by the conditions K1 to K4, it is determined whether or not prefetching is performed or whether or not registration is performed in the operand cache 400.
[0098]
According to the present embodiment, it is possible to eliminate complicated control for a difference in operation depending on the prefetch state, and to reduce the amount of information in the storage table 210.
(D) Next, an embodiment having a configuration in which the success or failure of the prefetch address prediction is determined by the predicted address storage area 204 in the instruction cache 200 and the prefetch operand cache 600 is omitted will be described below.
[0099]
In this configuration, since the prefetch operand buffer 600 does not exist, the prefetched data is registered in the operand cache 400. Therefore, in the operand cache 400, both data read by a load request from the instruction processing device 100 and data read by prefetch are registered. In the case of the information processing apparatus according to the present embodiment, the load request is transferred to the operand cache 400 or the main storage device 500. Each time a load request occurs, the success / failure of the prefetch address prediction is determined. In this case, the next prefetch request is transferred to the main storage device 500 or the operand cache 400. When the prefetch data is read from the main storage device 500, the prefetch data is registered in the operand cache 400. For the prefetch state transition and the prefetch address prediction method, the operation of the first embodiment is performed.
[0100]
According to this embodiment, the prefetch operand buffer 600 can be deleted, and the amount of hardware can be reduced. (E) An embodiment in which the data valid flag 603 and the data storage area 604 are added to the storage table 210 of the instruction cache 200 in the above (D) will be described with reference to FIG.
[0101]
8, a data valid flag storage area 603 and a data storage area 604 mounted in the prefetch operand buffer 600 in the above embodiment are mounted in the instruction cache 200. Similarly to the above (D), the prefetch operand buffer 600 does not exist, and the success or failure of the prefetch address prediction is determined using the predicted address storage area 204 in the instruction cache. However, the difference is that the pre-read data is stored in the data storage area 604 and is not registered in the operand cache 400. According to this method, the non-local data successfully prefetched in the operand cache 400 is not registered in the operand cache 400, and the operand cache 400 can be used effectively.
[0102]
In this embodiment, since the prefetch data is provided for each instruction, data having a low possibility of being used by prefetching is not registered in the operand cache, so that a small-capacity operand cache can be effectively used.
(F) In (D), an embodiment is shown in which the predicted address storage area 204 is deleted from the storage table 210 in the instruction cache 200 to reduce the information amount per set of the instruction cache storage table 210.
[0103]
By generating the prefetch prediction address at the time of the previous load execution from the previous load address and the prefetch method, the predicted address storage area 204 can be deleted. In this embodiment, the success or failure of the prefetch address prediction is determined by comparing the load address of the current load request, the previous load address 203, and the predicted address predicted from the prefetch method 206. If the load address and the predicted address match, the prediction is successful, and if they do not match, the prediction is failed. According to the method of the present embodiment, the amount of information in the storage table 210 can be reduced.
[0104]
(Other problems of the invention)
In the technology in the case where the prefetch state storage area 205 exists, the prefetch fails once, so that the prefetch state is changed during the prefetch test, and the prefetch method is changed.
[0105]
In a program in which memory access is performed inside a nested loop described in C language in FIG. 9, if the innermost loop ends but the outer loop does not end, the memory access reference address is changed, and Since the innermost loop is executed and the intervals between the memory accesses executed before and after the reentry of the loop become discontinuous, the prefetching of the load instruction immediately after the reentry fails. After the second repetition after reentering the innermost loop, the load instruction of the innermost loop is likely to succeed if the prefetching method used when the prefetching was successful previously.
[0106]
When the above-described information processing apparatus processes the program having the nested loop structure illustrated in FIG. 9, the prefetching method has been changed due to the prefetching failure immediately after re-entry into the innermost loop. The prefetching fails until it returns to, and useless prefetch address prediction attempts occur until the prefetching succeeds again.
[0107]
An example will be described using a program described in C language shown in FIG. FIG. 10 shows an instruction sequence after the repetition loop in the C language description of FIG. 9 is expanded into virtual machine instructions. FIG. 10 is a sequence of instructions for executing a double repetition loop, in which the inner loop ends and a load instruction for row L8 when the next inner loop is executed.
FIG. 11 shows the memory access history of load r (a) = Memory [a + x * 2000 + y].
[0108]
“Serial number” in FIG. 11 indicates the order of load execution, “address” indicates a load address which is an address of the operand data of the load instruction on the main storage device 500, and “address” indicates the two consecutive addresses. In the difference, “Remarks” indicates an annotation for loading the same line. The interval from the serial number 1 to the serial number 1000 and the interval from the serial number 1002 to the serial number 1003 are +1. However, the interval at the serial number 1001 is +1001, which is different from the interval between the addresses of the other serial numbers. Is a problem.
[0109]
In the information processing apparatus, the look-ahead prediction fails when the load instruction of the serial number 1001 is executed. However, in the serial number 1002, the interval is again +1. Succeeds. However, if the look-ahead method is changed due to one failure of the look-ahead, unnecessary switching of the look-ahead method occurs every time the innermost loop is exited for an instruction sequence having a nested loop structure.
[0110]
(Means for Solving Other Problems of the Invention)
In order to solve this problem, in addition to the "read-ahead suppression state", the "read-ahead test in-progress state", and the "look-ahead confirmed state" in the information processing apparatus, a new "weak look-ahead confirmed state" If the read-ahead fails in the "pre-read fixed state", the state transits to the "weak pre-read fixed state", and when the state transits to the "weak pre-read confirmed state", the pre-read method is not changed, and the pre-read operand is not changed. Execute the data reading, if a predetermined number of prefetch failures occur in the "weak confirmed state", change the prefetch method, and by transiting to the prefetch test state, the inner loop in the nested loop Do not change the prefetching method depending on one prefetching failure after exiting, and use the prefetching method based on a predetermined number of prefetching failures. To solve the other problems of the invention by using a method of switching a.
[0111]
(Embodiments for Solving Other Problems of the Invention)
An embodiment for solving the problem will be described with reference to FIG.
[0112]
The meaning of each column of the table in FIG. 12 is the same as FIG. 2 except for “P-MATCH”. “P-MATCH” matches the load address of the load request from the instruction processing device 100 with the predicted address storage area 204 in the storage table 210 in the instruction cache 200 where the load instruction that issued the load request is registered. A hit is shown as "Hit" as a look-ahead hit, and a mismatch is shown as "Miss" as a look-ahead miss. Further, "---" indicates an arbitrary state, and indicates that the state is unrelated to a prefetch hit or miss.
(1) Operation when the prefetch state is suppressed
The operation of the conditions D1A to D1D when the “old state” is “inhibited”, that is, the pre-reading state is in the inhibited state will be described. When the cache control device 300 registers the load address of the load request from the instruction processing device 100 in the load address storage area 203 of the instruction cache 200 and searches the operand cache 400 for a hit in the operand cache 400 in the condition D1A. In this case, the state is not changed and the pre-reading is not executed.
[0113]
When a miss occurs in the operand cache 400 under the conditions D1B and D1C and a “prefetch hit” occurs, the cache control device 300 indexes the prefetch operand buffer 600 by the load address, and reads the load address and the prefetch address storage area 601. If there is a storage table 610 having the same comparison result and the data valid flag storage area 603 is on, the data in the data storage area 604 is supplied to the instruction processing device 100, and the comparison result is different or If the data valid flag storage area 603 is off, the load request is transferred to the main storage device 500, and the read data is supplied to the instruction processing device 100. Set "pre-reading confirmation" in the status storage area 205, and According to the look-ahead method stored in the formula storage area 206, a look-ahead prediction address is generated by the “fixed interval address prediction method” in the case of the condition D1B, and by the “address group prediction method” in the case of the condition D1C. In addition to registering in the prefetch address storage area 204, a prefetch request is sent to the operand cache 400, and if the prefetch request hits the operand cache 400, the data valid flag 603 is turned off. Sends a prefetch request to the main storage device 500, registers the read data in the data storage area 604, and turns on the data valid flag storage area 603.
[0114]
When the prefetch state in the condition D1D is in the inhibited state, and the miss occurs in the operand cache 400 and the prefetch miss occurs, the cache control device 300 transfers the load request to the main storage device 100 and executes the read data in the instruction processing. The data is supplied to the device 100, registered in the operand cache 400, the prefetch state is changed to "prefetch test in progress", the prefetch method is changed, and the predicted address generated according to the changed prefetch method is registered in the predicted address storage area 204. I do.
(2) Operation when the pre-reading state is under test
An operation in which the “old state” is “under test” under the conditions D2A to D2F, that is, the pre-read state is under test is described. When the operand cache 400 is hit and the prefetch is hit under the conditions D2A and D2B, the cache control device 300 transfers the load request to the operand cache 400, supplies the read data to the instruction processing device 100, and "Weak look-ahead determination" is set in the state storage area 205, a look-ahead predicted address is generated in accordance with the look-ahead scheme storage area 206, the predicted address is registered in the predicted address storage area 204, and a look-ahead request is sent to the operand cache 400, When the read-ahead request hits the operand cache 400, the data valid flag 603 is turned off. When the read-ahead request misses the operand cache 400, the read-ahead request is sent to the main storage device 500 to read out. Data storage area Register 604, to turn on the data valid flag storage area 603.
[0115]
In the condition D2C, when the “old state” is in the “testing” state, the operand cache 400 is hit, and the read-ahead is missed, the cache control device 300 transfers the load request to the operand cache 400 and reads the read data. Is supplied to the instruction processing apparatus 100, "prefetch suppression" is set in the prefetch state storage area 205, a prefetch prediction address is generated in accordance with the method stored in the prefetch method storage area 206, and the prediction address is stored in the prediction address storage area. Register in 204.
[0116]
When a miss occurs in the operand cache 400 and a prefetch hit occurs under the conditions D2D and D2E, the cache control device 300 indexes the prefetch operand buffer 600 by the load address of the load request, and the load address and the prefetch prediction. If the result of the comparison is a match and the data valid flag storage area 603 is on, the data in the data storage area 604 is supplied to the instruction processing device 100, and If the comparison result does not match or the data valid flag storage area 603 is off, the load request is transferred to the main storage device 500, and the read data is supplied to the instruction processing device 100. Not registered in the prefetch state storage area 205 By setting “prefetching fixed”, a prefetch prediction address is generated in accordance with the prefetch method storage area 206, the prediction address is registered in the prediction address storage area 204, a prefetch request is sent to the operand cache 400, and the operand cache 400 is hit. In this case, the data valid flag 603 is turned off. In the case of an operand cache 400 miss, a prefetch request is sent to the main storage device 500, the read data is registered in the data storage area 604, and the data valid flag storage area Turn 603 on.
[0117]
When the "old state" in the condition D2F is "under test" and the operand cache 400 misses and the prefetching misses, the cache control device 300 transfers the load request to the main storage device 100 and reads the read request. The read data is supplied to the instruction processing device 100, registered in the operand cache 400, the prefetch state is changed during the prefetch test, the prefetch method is changed, and the predicted address predicted according to the changed prefetch method is changed to the predicted address. Register in the storage area 204. Further, under the condition D2F, the value of the load dress storage area 203 and the load address of the current load request are registered in the address history table 700 as the executing load address and the predicted load address, respectively.
(3) Operation when the prefetch state is determined to be prefetch
An operation when the “old state” is “prefetching fixed” under the conditions D3A to D3F will be described.
[0118]
When the “old state” in the conditions D3A and D3B is “prefetched” and hits the operand cache 400 and hits the prefetch, the cache control device 300 performs the same operation as the conditions C2A and C2B, respectively.
[0119]
In the case where the “old state” in the condition D3C is “pre-determined” and the operand cache 400 is hit and the read-ahead is missed, the cache control device 300 transfers the load request to the operand cache 400 and transfers the read data. This is supplied to the instruction processing apparatus 100, a weak prefetch determination is set in the prefetch state storage area 205, a prefetch prediction address is generated in accordance with the prefetch scheme storage area 206, the prediction address is registered in the prediction address storage area 204, and a prefetch request is issued. Is sent to the operand cache 400. If the operand cache 400 is hit, the data valid flag 603 is turned off. If the operand cache 400 is missed, the prefetch request is sent to the main storage device 500, and the read data is read. Is registered in the data storage area 604 Although turning on the data valid flag storage area 603, it is not registered in the address history table 700.
[0120]
When the “old state” in the conditions D3D and D3E is “prefetch determination”, the miss occurs in the operand cache 400, and the prefetch hits, the cache control device 300 performs the same operation as the conditions D2D and D2E, respectively. .
[0121]
When the “old state” in the condition D3F is “prefetch determination”, the miss occurs in the operand cache 400, and the prefetch miss occurs, the cache control device 300 transfers the load request to the main storage device 500, The read data is supplied to the instruction processing device 100. Further, "weak lookahead determination" is set in the prefetch state storage area 205, a prefetch prediction address is calculated in accordance with the prefetch scheme storage area 206, the prediction address is registered in the prediction address storage area 204, and a prefetch request is transmitted to the operand cache 400. If the operand cache 400 is hit, the data valid flag 603 is turned off. If the operand cache 400 is missed, the prefetch request is sent to the main storage device 500, and the read data is stored in the data storage area. 604, and turns on the data valid flag storage area 603, but does not register it in the address history table 700.
(4) "Confirmation operation with weak pre-reading state"
The operation of the conditions D4A to D4F in which the "old state" is "weak look-ahead determination", that is, the pre-read state is a test under test will be described.
[0122]
When the "old state" in the conditions D4A and D4B is "weak look-ahead determination", and the operand cache 400 is hit and the look-ahead is hit, the cache control device 300 operates the same as the conditions D2A and D2B, respectively. I do.
[0123]
When the "old state" in the condition D4C is "weak look-ahead determination" and a hit occurs in the operand cache 400 and a miss occurs in the look-ahead, the cache control device 300 performs the same operation as in the condition D2C. However, there are a plurality of weak look-ahead determined states, for example, a weak look-ahead determined state 1, a weak look-ahead determined state 2,. . . By providing a weak prefetch confirmation state N and transitioning to the prefetch test state by a predetermined number of consecutive prefetch failures, by changing to the prefetch test state and changing the prefetch method, It is also possible to delay the change of the prefetching method.
[0124]
When the "old state" in the conditions D4D and D4E is "weak look-ahead determination", and the miss occurs in the operand cache 400 and the look-ahead hits, the cache control device 300 performs the same operation as in the conditions D2D and D2E, respectively. Perform the operation.
[0125]
In the case where the "old state" in the condition D4F is "weak lookahead determination", the miss occurs in the operand cache 400, and the look-ahead is missed, the cache control device 300 performs the same operation as in the condition D2F.
[0126]
【The invention's effect】
As described above, the information processing apparatus of the present invention has the following effects.
(1) In the case of a fixed address access load instruction in which the load address of the load instruction executed by the instruction processing device is always the same address each time it is executed, data is registered only once in the operand cache and the subsequent same load instruction is executed. Sometimes there is a high possibility of hitting the cache, so there is no effect of prefetching.
[0127]
On the other hand, in the case of a load instruction in which the load address changes with each execution, the possibility that the previously accessed data is less likely to be used again is low, and the possibility of hitting the operand cache is low. Thus, a look-ahead effect of shortening the load time of the load can be obtained.
[0128]
In the present cache control device, the prefetch is not performed for the load instruction that hits the operand cache, and the prefetch that cannot obtain the effect of the fixed address access load instruction is not performed. is there.
(2) In the case of a variable address load instruction that is a load instruction whose load address changes each time it is executed, it is highly possible that the load address at which the load instruction is executed next time is not registered in the operand cache, and prefetching is valid. It is.
[0129]
In the present cache control device, the prefetch address prediction is started when a miss occurs in the operand cache, and only the prefetch address prediction is performed without performing the prefetch of the operand data until it is confirmed that the prefetch address prediction is successful. The prefetching success rate is improved without performing prefetching that is not likely to succeed, and the prefetching execution frequency is reduced.
(3) The address change of the variable address load instruction has various tendencies, and a single load address prediction method cannot achieve a high prefetch success rate. In this method, a plurality of look-ahead methods, that is, “fixed interval address prediction method” or “address group prediction method” are switched when each prediction fails, so that the address change tendency of the variable address load instruction is matched. The method can be dynamically determined, and there is an effect of improving the prefetch success rate.
(4) In the case of using the “address group prediction method” that generates a prefetch address using an access history table which is a load address group of two consecutive load requests, the number of address groups in the access history table easily increases. There is a problem. In the present invention, by using the address group prediction method when a prefetch error occurs in the fixed-interval address prediction method, an instruction to access a non-local continuous space or a non-local constant-space access instruction is obtained. The address prediction is performed by the "fixed interval address prediction method", and the access history table is used by the "address group prediction method" only for instructions that perform discontinuous accesses that do not succeed in prefetching in the fixed interval address prediction method. According to this method, there is an effect that the capacity of the access history table required for prefetching is reduced.
(5) In a pre-reading control device that includes a plurality of pre-reading methods and uses the pre-reading method by switching, the pre-reading success rate decreases due to a pre-reading error until the pre-reading method is determined. In the cache control device according to the present invention, a plurality of prefetch address predictions are executed simultaneously, and subsequent prefetching is performed according to the successful prefetching method, thereby shortening the period until the prefetching method is determined and improving the prefetching success rate. effective.
(6) When accessing the address space in a regular order, the prefetching is likely to succeed, but the data read by the prefetching is used only once, and is not used again. Data is likely to be Therefore, if the read data is registered in the operand cache when the prefetch address prediction is successful, data that is used only once is registered in the operand cache, so that the small-capacity operand cache is frequently used locally. Data can be evicted, which can cause an increase in operand cache misses.
[0130]
Registering data that is used only once in the cache, or registering data that is used only once or that is never used due to read-ahead failure in the cache is called cache pollution. In designing a cache control device having a read-ahead function, It is important to avoid cache pollution.
[0131]
In the present invention, by preventing data read by prefetching from being registered in the operand cache, the cache pollution can be prevented, and the operand cache can be used effectively. As a result, the effect of improving the hit rate of the operand cache can be obtained. Can be
(7) The tendency of the load address of the load instruction to change differs for each instruction, and it is difficult to accurately predict the prefetching by simply observing the load address of the load instruction issued from the instruction processing device. In the present invention, the prefetch method and prefetch state for each instruction are stored in the instruction cache, and information on whether to perform prefetch or what prefetch method is used is set for each instruction, and the access behavior differs. Even when instructions access the address of the same operand data, it is possible to execute the prefetching of the operand data according to the access behavior of each instruction, and there is an effect of improving the success rate of the prefetching of the operand data.
(8) The success or failure of the prefetch prediction is determined for each execution of the load instruction, and the access to the main memory or the operand cache by the prefetch is not performed until the address prediction by the prefetch succeeds after the failure of the prefetch. As a result, useless memory access due to read-ahead failure does not occur, and the effect of improving the memory access performance of the entire apparatus by effectively using the limited memory access band is obtained.
(9) In a software multiplex loop, the continuity of the load address is lost when the innermost loop is completed and the execution shifts to the innermost loop again, and in the second and subsequent repetitions after reentering the loop, , The same continuous access as before may be resumed. In this method, in the state where the prefetching is successful, the prefetching method is not switched due to one prefetching failure, and the prefetching method is switched twice or consecutively after a predetermined number of prefetching failures. When the re-entry into the innermost loop after completion of the innermost loop, the prefetching method is not switched, so that useless switching of the prefetching method is suppressed, and the prefetching success rate is improved.
(10) In software, since the code size is often smaller than the data size, and in the present invention, the prefetch prediction is performed for each instruction, the amount of hardware is smaller than in the method of performing the prefetch prediction for each address to be read. Thus, there is an effect that a higher prefetch success rate can be obtained.
(11) In the present invention, the prefetch success or failure is determined by comparing the last predicted address in the instruction cache with the load address of the load request, and when the prefetch address prediction fails, the prefetch operand buffer is indexed. And reduce unnecessary access to the prefetch operand buffer. Due to the effect of the decrease in the use frequency of the prefetch operand buffer, the frequency of occurrence of queuing due to the contention of the prefetch operand buffer access due to the simultaneous occurrence of the index and registration of the prefetch operand buffer is reduced, and the memory access performance is improved.
(12) The prediction address generated by the prefetch address prediction in the prefetch operand buffer and the instruction address of the instruction that is the source of the prefetch address prediction are held, and an instruction having an instruction address different from the instruction address is stored in the operand buffer. When a load request is issued for a load address that matches the predicted address in the cache address, the cache controller detects that the load address is used by a plurality of instructions, and stores the read data of the load address in the operand cache. , And frequently used local data used by a plurality of instructions is registered in the cache, so that local data and non-local data are distinguished, and the hit rate of the operand cache is reduced. This has the effect of performing pre-reading without the need.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus according to an embodiment of the present invention.
FIG. 2 is a table showing a basic operation of the information processing apparatus according to the embodiment of the present invention.
FIG. 3 is a block diagram illustrating a fixed-interval address prediction method that is a prefetch method in the information processing apparatus according to the embodiment of the present invention.
FIG. 4 is a block diagram illustrating an address set prediction method which is a prefetch method in the information processing apparatus according to the embodiment of the present invention;
FIG. 5 is a state transition diagram of a prefetching method in the information processing apparatus according to the embodiment of the present invention.
FIG. 6 is a flowchart illustrating an operation of the information processing apparatus according to the embodiment of the present invention.
FIG. 7 is a flowchart illustrating an operation of the information processing apparatus according to the embodiment of the present invention.
FIG. 8 is a modification example of the instruction cache in the information processing apparatus according to the embodiment of the present invention;
FIG. 9 is a diagram showing an example of a program described in C language.
10 is a diagram showing an instruction code after the repetition loop in the C language description of FIG. 9 is expanded into a virtual machine instruction.
11 is a diagram showing a memory access history of a load instruction of a row L8 in FIG. 10;
FIG. 12 is a diagram illustrating an operation of the cache control device according to the embodiment of the present invention when a “weak prefetch confirmation state” is provided.
FIG. 13 is a diagram showing an example of a program described in C language.
14 is a diagram showing an instruction code after the repetition loop part in the C language description of FIG. 13 is expanded into a virtual machine instruction.
FIG. 15 is a diagram showing a memory access history of a load instruction in a row L8 in FIG. 14;
[Explanation of symbols]
100 instruction processing unit
200 instruction cache
201 Instruction address storage area
202 Instruction storage area
203 Load address storage area
204 Predicted address storage area
205 Prefetch state storage area
206 Prefetch method storage area
210 storage table
300 Cache control device
400 operand cache
500 main storage
600 Look-ahead operand buffer
601 prefetch address storage area
602 instruction address storage area
603 Data valid flag storage area
604 data storage area
610 storage table
S100 to S550 Step

Claims (8)

A main storage device for storing a plurality of instructions and a plurality of operand data;
Instruction processing means for executing each of the instructions;
An operand cache holding a plurality of the operand data,
Registers some of the instructions recently executed by the instruction processing means among the instructions, registers the registered instruction together with the address of the registered instruction on the main storage device, and stores the registered instruction in the main storage. When the instruction is a load instruction for loading operand data on a device into the instruction processing means, the address of the operand data on the main storage device when the registered instruction was previously executed, and the registered instruction Is the predicted address on the main memory of the operand data that is predicted to be accessed the next time it is executed, the prefetch method when the predicted address is predicted, and the prefetch state of the registered instruction. An instruction cache capable of storing each of the registered instructions,
When the instruction executed by the instruction processing means is a load instruction, and the address of the operand data to be loaded changes each time the instruction is executed, the instruction is executed every time the instruction is executed by the instruction processing means. Predicts the address of the operand data to be accessed the next time it is executed on the main storage device, and the address of the actually accessed operand data matches the predicted address stored in the instruction cache. And setting the prefetching method in the instruction cache, generating the prediction address in the prefetching method stored in the instruction cache each time the instruction is executed by the instruction processing means, and calculating operand data of the prediction address. An information processing apparatus comprising: Stores, along with the predicted address, an address on the main storage device of a load instruction that accesses the predicted address, operand data of the predicted address, and a data valid flag indicating whether the stored operand data is valid. Further comprising a look-ahead operand buffer
If the address of the operand data loaded by the instruction executed by the instruction processing means on the main storage device is the predicted address of an instruction other than the instruction, the cache control means sets the operand data in the instruction to 2. The information processing apparatus according to claim 1, wherein said operand data is stored in said operand cache without performing prefetching of said address. Every time a load instruction is executed by the instruction processing means, the address of the operand data requested to be accessed by the instruction processing means on the main memory and the execution of the previous load instruction stored in the instruction cache A fixed-interval address prediction method in which an address obtained by adding a difference between an address of the operand data of the main storage device and an address requested by the instruction processing means to the address is the predicted address;
Each time a load instruction is executed by the instruction processing means, the address of the operand data requested to be accessed previously by the instruction processing means is used as the old load address, and the address of the operand data requested by the instruction processing means to be accessed this time. Is used as a new load address, and a combination of the old load address and the new load address is stored in the access history table, and the address of the operand data requested to be accessed by the instruction processing means this time is stored in the access history table. 3. The information processing apparatus according to claim 1, wherein, when the read address matches the old load address, an address set prediction method using a new load address corresponding to the old load address as the prediction address is used as the look-ahead method. 4. The cache control unit, when determining the prefetching method, selects one of the fixed interval address prediction method and the address group prediction method as the prefetching method, and determines the address of the current operand data and 4. The information processing apparatus according to claim 3, wherein the prefetching method stored in the instruction cache is switched until the predicted address stored in the instruction cache matches. The cache control means, when deciding the look-ahead method, generates the predicted addresses using both the fixed-interval address prediction method and the address group prediction method as the look-ahead method, and calculates the address of the current operand data. 4. The information processing apparatus according to claim 3, wherein a prefetching method in which the predicted address matches the predicted address is stored in the instruction cache. Deleting the predicted address storage area from the instruction cache, generating a previously predicted address from the address on the main storage device of the operand data when the load instruction was previously executed, and accessing the actually accessed operand data; The information processing apparatus according to any one of claims 1 to 5, wherein a prefetching method is determined by comparing whether the prefetching is successful or unsuccessful by comparing the prefetching method with a predetermined address. The instruction to delete the pre-read state from the cache, regardless of the look-ahead state, misses the operand cache, and the information processing apparatus according to any one of claims 1 to perform prefetching only upon successful prefetch 6. 5. The information processing apparatus according to claim 4, wherein the prefetch method is switched in the instruction cache by one or more prefetch failures.

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