JP3580312B2 - Image processing circuit for driving liquid crystal, liquid crystal display device using the same, and image processing method - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly, to an image processing circuit and an image processing method for improving a response speed of a liquid crystal.

  Liquid crystal has a drawback that the transmittance changes due to the cumulative response effect, so that it cannot cope with a moving image that changes rapidly. In order to solve such a problem, there is a method of improving the response speed of the liquid crystal by making the liquid crystal driving voltage at the time of gradation change higher than the normal driving voltage.

  FIG. 72 is a diagram showing an example of a liquid crystal driving device for driving liquid crystal by the above method, the details of which are described in, for example, JP-A-6-189232. In FIG. 72, reference numeral 100 denotes an A / D conversion circuit; 101, an image memory for holding data for one frame of a video signal; 102, a gradation change signal by comparing current image data with image data of one frame before A comparison circuit for outputting, 103 is a liquid crystal panel driving circuit, and 104 is a liquid crystal panel.

  Next, the operation will be described. The A / D conversion circuit 100 samples a video signal with a clock having a predetermined frequency, converts the video signal into digital image data, and outputs the digital image data to the image memory 101 and the comparison circuit 102. The image memory 101 delays the input image data by a period corresponding to one frame of the video signal, and outputs the delayed image data to the comparison circuit 102. The comparison circuit 102 compares the current image data output from the A / D conversion circuit 100 with the image data one frame before output from the image memory 102, and generates a gradation change signal representing the gradation change of both images. Is output to the drive circuit 103 together with the current image data. Based on the gradation change signal, the drive circuit 103 drives a display pixel of the liquid crystal panel 104 by applying a drive voltage higher than a normal liquid crystal drive voltage to a pixel whose gradation value is increased, and is low for a pixel whose gradation value is decreased. Drive by applying voltage.

  In the image display device shown in FIG. 72, when the number of display pixels on the liquid crystal panel 104 increases, the amount of image data for one frame written to the image memory 101 increases, so that there is a problem that the required memory capacity increases. In the image display device described in JP-A-4-204593, one address of the image memory is assigned to four pixels as shown in FIG. 73 in order to reduce the capacity of the image memory 101. In other words, when pixel data is thinned out every other pixel in the vertical and horizontal directions and stored in the image memory, and when the image memory is read out, the same image data as the stored pixel is read out a plurality of times for the thinned out pixels, thereby reducing the capacity of the image memory. ing. For example, for the pixels at (a, B), (b, A), and (b, B), the data at address 0 is read.

  As described above, when the gradation value changes one frame before, the response speed of the liquid crystal can be improved by setting the liquid crystal driving voltage higher than the normal liquid crystal driving voltage. However, since the liquid crystal driving voltage is increased or decreased only based on the change in the magnitude relationship of the gradation values, when the gradation value increases one frame before, the driving voltage higher than usual becomes uniform regardless of the increase amount. Applied. For this reason, when the change in the gradation value is slight, an overvoltage is applied to the liquid crystal, thereby deteriorating the image quality.

  As shown in FIG. 73, when the capacity of the image memory 101 is reduced by thinning out the image data in the image memory 101, the following problem occurs. FIG. 74 is an explanatory diagram for describing a problem caused by the thinning processing. In FIG. 74, (a) is the image data in the (n + 1) th frame, (b) is the image data obtained by performing the decimating process on the (n + 1) th frame image shown in (a), and (c) is the pixel data obtained by performing the decimating process. (D) represents the image data of the nth frame preceding by one frame. As shown in FIGS. 74 (a) and (d), the image of the nth frame is the same as the image of the (n + 1) th frame.

  When the thinning process is performed, the pixel data of (A, a) is read as the pixel data of (B, a) and (B, b) as shown in FIG. 74 (c), and (B, c) , (B, d) are read out as (A, c) pixel data. That is, the pixel data having the gradation value of 150 is actually read as the pixel data having the gradation value of 50. For this reason, the pixels at (B, a), (B, b), (B, c), and (B, d) in the (n + 1) th frame are higher than usual, even though the image has not changed one frame before. Is also driven by a high drive voltage.

  As described above, when the thinning processing is performed, voltage control is not correctly performed in a portion where pixel data is thinned, and image quality is deteriorated due to application of an unnecessary voltage.

  The present invention has been made in view of the above problems, and in a liquid crystal display device, a liquid crystal driving image for correcting image data output to the liquid crystal display device so that a voltage applied to liquid crystal is appropriately controlled. It is an object to provide a processing circuit and an image processing method.

  Further, the present invention provides a liquid crystal driving image processing circuit and an image processing method capable of accurately controlling the voltage applied to the liquid crystal even when the capacity of a frame memory for reading an image one frame before is reduced. The purpose is to:

An image processing circuit for driving a liquid crystal according to the present invention converts image data representing a gradation value of each pixel of an image corresponding to a voltage applied to the liquid crystal based on a temporal change of the gradation value of each pixel. An image processing circuit for driving a liquid crystal for correcting and outputting,
First color conversion means for converting image data consisting of R, G, and B signals representing the image of the current frame into a luminance signal and a color signal;
An encoding unit that outputs encoded image data corresponding to the image of the current frame by encoding the luminance signal and the color signal,
Decoding means for outputting the first decoded image data corresponding to the image data of the current frame by decoding the encoded image data output by the encoding means;
Delay means for delaying the encoded image data output by the encoding means for a period corresponding to one frame;
Decoding means for decoding the encoded image data output by the delay means to output second decoded image data corresponding to the image data one frame before the current frame;
Second color space conversion means for converting the first decoded image data into image data composed of R, G, B signals;
Third color space conversion means for converting the second decoded image data into image data consisting of R, G, B signals;
Based on the first decoded image data and the second decoded image data converted into image data composed of R, G, and B signals by the second color space conversion unit and the third color space conversion unit. Correction data generating means for outputting correction data for correcting the gradation value of the image of the current frame;
Correction means for correcting image data representing the image of the current frame based on the correction data.

An image processing method according to the present invention is an image processing method that corrects image data representing a gradation value of each pixel of an image corresponding to a voltage applied to a liquid crystal based on a temporal change in a gradation value of each pixel. Processing method,
Image data composed of R, G, and B signals representing the image of the current frame is converted into a luminance signal and a color signal;
Generate the encoded image data corresponding to the image data of the current frame by encoding the luminance signal and the color signal, respectively.
Decoding first encoded image data corresponding to the image data of the current frame obtained by decoding the encoded image data, and delaying the encoded image data by a period corresponding to one frame; Converting the second decoded image data corresponding to the image data one frame before the current frame obtained by the above into image data consisting of R, G, B signals, respectively,
The image data of the current frame is corrected based on the first decoded image data and the second decoded image data converted into image data composed of R, G, and B signals.

According to the liquid crystal driving image processing circuit and the image processing method according to the present invention,
The current frame is corrected by converting the image data composed of the R, G, and B signals into a luminance signal and a chrominance signal, and then decoding the encoded image data with a delay corresponding to one frame. Since the image data of one frame before that is required is obtained, the memory capacity of the delay means can be reduced.
Also, the first decoded image data obtained by decoding the encoded image data and the second decoded image data obtained by decoding the encoded image data with a delay corresponding to one frame are obtained. Since the image data of the current frame is corrected based on the error, the error due to the coding is canceled, the response of the display means is improved when a moving image is input, and the error due to the coding is applied when a still image is input. A still image can be accurately displayed on the display means without unnecessary correction.
Further, at the time of encoding, by setting the compression rate of the chrominance signal higher than the compression rate of the luminance signal, the memory capacity of the delay unit can be further reduced.

Embodiment 1 FIG.
FIG. 2 is a block diagram showing a configuration of the liquid crystal drive circuit according to the first embodiment of the present invention. The receiving unit 2 receives an image signal via the input terminal 1 and sequentially outputs current image data Di1 representing an image for one frame (hereinafter, referred to as a current image). The image data processing unit 3 includes an encoding unit 4, a delay unit 5, decoding units 6 and 7, a correction data generator 8, and a correction unit 9, and generates new image data Dj1 corresponding to the current image data Di1. I do. The display unit 10 is configured by a general liquid crystal display panel, and performs a display operation by applying a voltage corresponding to a gradation value of an image to the liquid crystal.

  The encoding unit 4 outputs encoded data Da1 obtained by encoding the current image data Di1. The current image data Di1 can be encoded using block encoding such as FBTC or GBTC. In addition, any encoding method for a still image such as two-dimensional discrete cosine transform encoding such as JPEG, predictive encoding such as JPEG-LS, and wavelet transform such as JPEG2000 can be used. It should be noted that such a still image encoding method can be applied to lossy encoding in which image data before encoding and decoded image data do not completely match.

  The delay unit 5 outputs encoded data Da0 obtained by encoding the image data one frame before the current image data Di1 by delaying the encoded data Da1 by a period corresponding to one frame. The delay unit 5 includes a memory that stores the encoded data Da1 for one frame period. Therefore, as the encoding rate (data compression rate) of the current image data Di1 is increased, the memory capacity of the delay unit 5 required to delay the encoded data Da1 can be reduced.

  The decoding means 6 outputs decoded image data Db1 corresponding to the current image represented by the current image data Di1 by decoding the encoded data Da1. At the same time, the decoding unit 7 outputs the decoded image data Db0 corresponding to the image one frame before the current image by decoding the encoded data Da0 delayed by the delay unit 5.

  When the gradation value of the current image changes one frame before, based on the decoded image data Db1 and the decoded image data Db0, the correction data generator 8 changes the liquid crystal of the current image within one frame period. The correction data Dc for correcting the current image data Di1 so as to have the transmittance corresponding to the gradation value is output.

  The correction means 9 generates new image data Dj1 corresponding to the image data Di1 by adding (or multiplying) the correction data Dc to the current image data Di1.

  The display means 10 performs a display operation by applying a predetermined voltage to the liquid crystal based on the image data Dj1.

FIG. 1 is a flowchart showing the operation of the liquid crystal drive circuit shown in FIG.
In the image data encoding step (St1), the encoding unit 4 encodes the current image data Di1 and outputs the encoded data Da1. In the coded data delay step (St2), the coded data Da1 is delayed by the delay means 5 for a period corresponding to one frame, and coded data Da0 obtained by coding image data one frame before the current image data Di1 is output. Is done. In the image data decoding step (St3), the encoded data Da1 and Da0 are decoded by the decoding means 6 and 7, and the decoded image data Db1 and Db0 are output. In the correction data generation step (St4), the correction data generator 8 outputs correction data Dc based on the decoded image data Db1 and Db0. In the image data correction step (St5), the correction means 9 outputs correction data Dc corresponding to the current image data Di1 based on the correction data Dc. As described above, the operation of each of the steps S1 to St5 is performed for the current image data Di1 for each frame.

  FIG. 3 is a diagram showing an example of the internal configuration of the correction data generator 8. The look-up table (LUT) 11 is configured by a look-up table 11 storing data Dc1 representing each value of the correction data Dc determined based on the decoded image data Db0 and Db1. The output Dc1 of the lookup table 11 is used as correction data Dc.

  FIG. 4 is a diagram schematically illustrating the configuration of the lookup table 11. Here, each of the decoded image data Db0 and Db1 is 8-bit (256 gradation) image data, and takes a value of 0 to 255. As shown in FIG. 4, the look-up table 11 has 256 × 256 data arranged two-dimensionally, and correction data Dc1 = dt (Db1, Db1) corresponding to both values of the decoded image data Db0 and Db1. Db0).

  Hereinafter, the correction data Dc will be described in detail. Assuming that the gray level of the current image is 8 bits (0 to 255 gray levels), when the current image data Di1 = 127, a voltage V50 is applied to the liquid crystal so that the transmittance becomes 50%. Similarly, when the current image data Di1 = 191, a voltage V75 is applied so that the transmittance becomes 75%. FIG. 5 is a diagram showing a response speed when the voltages V50 and V75 are applied to a liquid crystal having a transmittance of 0%. As shown in FIG. 5, a response time longer than one frame period is required for the liquid crystal to reach a predetermined transmittance. Therefore, when the gradation value of the current image changes, the response speed of the liquid crystal can be improved by applying a voltage such that the transmittance after one frame period becomes a desired transmittance.

  As shown in FIG. 5, when a voltage V75 is applied, the transmittance of the liquid crystal after one frame period has elapsed is 50%. Therefore, when the target transmittance is 50%, the liquid crystal can have a desired transmittance within one frame period by setting the voltage of the liquid crystal to V75. In other words, when the current image data Di1 changes from 0 to 127, the current image data is output to the display means 10 as Dj1 = 191, so that a voltage that has a desired transmittance within one frame period is applied to the liquid crystal. Applied.

  FIG. 6 is a diagram illustrating an example of the response speed of the liquid crystal. The x-axis represents the value of the current image data Di1 (gradation value in the current image), and the y-axis represents the value of the image data Dj0 one frame before (one frame before). The z-axis indicates the response time required for the liquid crystal to change from the transmittance corresponding to the tone value of the previous frame to the transmittance corresponding to the tone value of the current image data Di1. ing. Here, when the gradation value of the current image is 8 bits, there are 256 × 256 combinations of gradation values in the current image and the image one frame before, so that there are also 256 × 256 response speeds. In FIG. 6, the response speed corresponding to the combination of the gradation values is simplified and shown in 8 × 8 ways.

  FIG. 7 shows the value of the correction data Dc added to the current image data Di1 so that the liquid crystal has a transmittance corresponding to the value of the current image data Di1 when one frame period has elapsed. When the gradation value of the current image is 8 bits, there are 256 × 256 correction data Dc corresponding to the combination of the gradation values in the current image and the image one frame before. In FIG. 7, the correction data corresponding to the combination of the gradation values is simplified and shown in 8 × 8 ways.

  As shown in FIG. 6, the response speed of the liquid crystal differs for each gradation value in the current image and the image one frame before, and the value of the correction data Dc cannot be obtained by a simple calculation formula. Stores 256 × 256 kinds of correction data corresponding to both the gradation values of the current image and the image of the previous frame.

  FIG. 8 is a diagram illustrating another example of the response speed of the liquid crystal. FIG. 9 shows the value of the correction data Dc added to the current image data Di1 so that the liquid crystal having the response characteristics shown in FIG. 8 has a transmittance corresponding to the value of the current image data Di1 when one frame period has elapsed. . As shown in FIGS. 6 and 8, the response characteristics of the liquid crystal vary depending on the material of the liquid crystal, the shape of the electrode, the temperature, etc. Therefore, by using the look-up table 11 provided with the correction data Dc corresponding to such use conditions, The response speed can be controlled in accordance with the characteristics of.

  The correction data Dc = dt (Db1, Db0) is set so that the correction amount for a combination of gradation values with low response speed of the liquid crystal becomes large. In particular, the liquid crystal has a low response speed when changing from an intermediate gradation (gray) to a high gradation (white). Therefore, the response speed is effectively improved by setting the values of the decoded image data Db0 representing the intermediate gradation and the correction data dt (Db1, Db0) corresponding to the decoded image data Db1 representing the high gradation to be large. Can be done.

  The correction data generator 8 outputs the data Dc1 output from the lookup table 11 as correction data Dc. The correction unit 9 outputs new image data Dj1 corresponding to the current image by adding the correction data Dc to the current image data Di1. The display means 10 performs a display operation by applying a voltage corresponding to the gradation value of the image data Dj1 to the liquid crystal.

  FIG. 10 is an explanatory diagram for describing an operation of the liquid crystal drive circuit according to the present embodiment. In FIG. 10, (a) shows the value of the current image data Di1, (b) shows the value of the image data Dj1 corrected based on the correction data Dc, and (c) shows the value of the liquid crystal when a voltage based on the image data Dj1 is applied. The response characteristics are shown. In FIG. 10C, the characteristic indicated by the broken line is the response characteristic of the liquid crystal when a voltage based on the current image data Di1 is applied. When the gradation value increases or decreases as shown in FIG. 10B, the correction values V1 and V2 based on the correction data Dc are added to or subtracted from the current image data Di1, thereby obtaining a new image corresponding to the current image. Is generated. In the display means 10, by applying a voltage based on the image data Dj1 to the liquid crystal, the liquid crystal can be driven to have a predetermined transmittance within substantially one frame period as shown in FIG. 10C.

  In the liquid crystal drive circuit according to the present embodiment, when the correction data Dc is generated, the encoding means 4 encodes the current image data Di1 and compresses and delays the data capacity, so that the current image data Di1 is delayed by one frame period. In this case, the capacity of the memory required for the operation can be reduced. Further, since encoding / decoding is performed without thinning out the pixel information of the current image data Di1, correction data Dc having an appropriate value can be generated, and the response speed of the liquid crystal can be accurately controlled.

  Further, since the correction data Dc is generated based on the decoded image data Db0 and Db1 encoded and decoded by the encoding unit 4 and the decoding units 6 and 7, the image data Dj1 is generated as described below. It is not affected by encoding / decoding errors.

  FIG. 11 is an explanatory diagram for describing the effect of an encoding / decoding error on image data Dj1. FIG. 11D is a diagram schematically illustrating the value of the current image data Di1 representing the current image, and FIG. 11A is a diagram schematically illustrating the value of the image data Di0 representing the image one frame before the current image. As shown in FIGS. 11D and 11A, the current image data Di1 does not change one frame before. FIGS. 11B and 11E are diagrams schematically showing encoded data corresponding to the current image data Di1 and the image data Di0 one frame before shown in FIGS. 11D and 11A. Here, FIGS. 11B and 11E show encoded data obtained by FTBC encoding. The representative value (La, Lb) is 8 bits, and 1 bit is assigned to each pixel. FIGS. 11C and 11F show decoded image data Db0 and Db1 obtained by decoding the encoded data shown in FIGS. 11E and 11B. FIG. 11 (g) shows the value of the correction data Dc generated based on the decoded image data Db0 and Db1 shown in FIGS. 11 (c) and 11 (f), and FIG. 9 shows the value of the image data Dj1 output to the display means 10.

  As shown in FIGS. 11 (d) and 11 (f), even when an error occurs during encoding / decoding of the current image data Di1, the decoded image data Db0 shown in FIGS. 11 (c) and 11 (f). , Db1, the value of the correction data Dc becomes 0 as shown in FIG. 11 (g). As a result, as shown in FIG. 11H, the image data Dj1 is output to the display means 10 without being affected by an error caused by encoding / decoding.

  In the above description, the case where the data input to the look-up table 11 is 8 bits has been described. However, the present invention is not limited to this, and the number of bits capable of substantially generating correction data by interpolation processing or the like is described. If so, any number of bits may be used.

  Further, the value of the correction data Dc may be a multiplied value by which the current image data Di1 is multiplied. In this case, the correction data Dc is represented as a coefficient centered at 1.0 times and having a magnification that changes in accordance with the correction amount. In this case, the correction means 9 is configured to include a multiplier. The correction data Dc is set so that the image data Dj1 does not exceed the range of the displayable gradation of the display unit 10.

Embodiment 2 FIG.
FIG. 13 is a diagram showing a first configuration of the correction data generator 8 according to the second embodiment. The data conversion unit 12 performs a bit number conversion for reducing the number of quantization bits of the decoded image data Db1 from, for example, 8 bits to 3 bits, thereby obtaining new decoded image data De1 corresponding to the decoded image data Db1. Is output. The lookup table 13 outputs correction data Dc1 based on the decoded image data De1 and the decoded image data Db0 whose bit numbers have been converted.

  FIG. 12 is a flowchart showing the operation of the liquid crystal drive circuit having the correction data generator 8 shown in FIG. In the encoded data conversion step (St6), the data converter 12 reduces the number of quantization bits of the decoded image data Db1. In the next correction data generation step (St4), the correction data Dc1 is output based on the decoded image data De1 and the decoded image data Db0 whose bit numbers have been converted by the look-up table 13. The operations in the other steps are the same as those described in the first embodiment.

  FIG. 14 is a diagram schematically showing a configuration of the lookup table 13 shown in FIG. Here, the decoded image data De1 whose bit number has been converted is data of 3 bits (8 gradations) and takes a value of 0 to 7. As shown in FIG. 14, the look-up table 13 has 256 × 8 data arranged in a two-dimensional manner, and is based on 3-bit decoded image data De1 and 8-bit decoded image data Db0. Data Dc1 = dt (De1, Db0) corresponding to both values of De1, Db0 is output.

  The method of converting the number of quantization bits by the data conversion means 12 may be either linear quantization or non-linear quantization that changes the quantization density of a predetermined gradation value.

  FIG. 15 is a diagram schematically illustrating a configuration of the lookup table 13 when the number of bits of the decoded image data De1 is converted by nonlinear quantization. In this case, the data conversion unit 12 compares the gradation value of the decoded image data Db1 with a plurality of threshold values set in advance corresponding to the number of conversion bits, and outputs the closest threshold value as the decoded image data De1. In FIG. 15, the interval between the correction data Dc1 arranged in the horizontal direction corresponds to the interval between a plurality of threshold values.

  As described above, when converting the number of bits by non-linear quantization, by setting the quantization density to be high in a region where the amount of correction is large, it is possible to reduce the error of the correction data Dc1 due to the reduction in the number of bits.

  FIG. 16 is a diagram showing a second configuration of the correction data generator 8 according to the present embodiment. The data conversion unit 14 performs a bit number conversion process of reducing the number of quantization bits of the decoded image data Db0 from, for example, 8 bits to 3 bits, thereby obtaining new decoded image data corresponding to the decoded image data Db0. De0 is output. The lookup table 15 outputs the corrected image data Dc1 based on the decoded image data Dbe whose bit number has been converted and the decoded image data De1.

  FIG. 17 is a diagram schematically showing a configuration of the lookup table 15 shown in FIG. Here, the decoded image data De0 whose bit number has been converted is data of 3 bits (8 gradations) and takes a value of 0 to 7. As shown in FIG. 17, the look-up table 15 has 8 × 256 data arranged two-dimensionally, and is based on 3-bit decoded image data De0 and 8-bit decoded image data Db1. The correction data Dc1 = dt (Db1, De0) corresponding to both values of Db1, De0 are output.

  The method of converting the number of quantization bits by the data conversion means 14 may be either linear quantization or non-linear quantization that changes the quantization density of a predetermined gradation value.

  FIG. 18 is a diagram schematically illustrating a configuration of the lookup table 15 when the number of bits of the decoded image data De1 is converted by non-linear quantization.

  FIG. 19 is a diagram showing a third configuration of the correction data generator 8 according to the present embodiment. The data converters 12 and 14 correspond to the decoded image data Db1 and Db0 by performing a bit number conversion process of reducing the number of quantization bits of the decoded image data Db1 and Db0 from, for example, 8 bits to 3 bits. The new decoded image data De1 and De0 are output. The look-up table 16 outputs correction data Dc1 based on the decoded image data De0 and De1 whose number of bits has been converted.

  FIG. 20 is a diagram schematically showing the configuration of the lookup table 16 shown in FIG. Here, the decoded image data De1 and De0 whose bit numbers have been converted are 3-bit (eight gradation) data and take values of 0 to 7. As shown in FIG. 20, the correction data generating means 16 has 8 × 8 data arranged two-dimensionally, and based on the 3-bit decoded image data De1 and De0, both values of De1 and De0 are provided. Is output as the correction data Dc1 = dt (De1, De0).

  The method of converting the number of quantization bits by the data conversion units 12 and 14 may be either linear quantization or non-linear quantization that changes the quantization density of a predetermined gradation value.

  FIG. 21 is a diagram schematically showing the configuration of the look-up table 16 when the decoded image data De1 and De0 are converted to the number of bits by nonlinear quantization.

  As described above, by reducing the number of quantization bits of the decoded image data Db1 and / or the decoded image data Db0, the data amount of the look-up tables 13, 15, and 16 is reduced, and correction data generation is performed. The configuration of the container 8 can be simplified.

  In the above description, the data converters 12 and 14 convert the number of quantization bits from 8 bits to 3 bits. However, the present invention is not limited to this. Any number of bits may be used as long as the number of bits can generate the correction data.

Embodiment 3 FIG.
FIG. 23 is a diagram showing a first configuration of the correction data generator 8 according to the third embodiment. The data conversion means 17 linearly quantizes the decoded image data Db1, converts the quantization bit number from, for example, 8 bits to 3 bits, and outputs the decoded image data De1 whose bit number has been converted. At the same time, the data conversion means 17 calculates an interpolation coefficient k1 described later. The look-up table 18 outputs two correction data Df1 and Df2 based on the 3-bit decoded image data De1 and the 8-bit decoded image data Db0 whose bit numbers have been converted. The correction data interpolation means 19 generates correction data Dc1 based on the two correction data Df1 and Df2 and the interpolation coefficient k1.

  FIG. 22 is a flowchart showing the operation of the liquid crystal drive circuit according to the present embodiment having the correction data generator 8 shown in FIG. In the coded image data conversion step (St6), the data conversion unit 17 performs bit number conversion for reducing the number of quantization bits of the decoded image data Db1, and outputs an interpolation coefficient k1. In the correction data generation step (St4), two correction data Df1 and Df2 are output based on the decoded image data De1 and the decoded image data Db0 whose bit numbers have been converted by the look-up table 18. In the correction data interpolation step (St7), the correction data interpolation means 19 generates correction data Dc1 based on the two correction data Df1 and Df2 and the interpolation coefficient k1. The operations in the other steps are the same as those described in the first embodiment.

  FIG. 24 is a diagram schematically showing a configuration of the lookup table 18. As shown in FIG. Here, the decoded image data De1 whose bit number has been converted is data of 3 bits (8 gradations) and takes a value of 0 to 7. As shown in FIG. 24, the look-up table 18 has 256 × 9 data arranged two-dimensionally, and has both values of the 3-bit decoded image data De1 and the 8-bit decoded image data Db0. Is output as the correction value Df1, and the correction data dt (De1 + 1, Db0) adjacent to the correction value Df1 is output as the correction value Df2.

The correction data interpolation means 19 uses the correction data Df1 and Df2 and the interpolation coefficient k1 to calculate the correction data Dc1 according to the following equation (1).
Dc1 = (1−k1) × Df1 + k1 × Df2 (1)

  FIG. 25 is an explanatory diagram for describing a method of calculating the correction data Dc1 represented by the above equation (1). In FIG. 25, s1 and s2 are threshold values used when the data conversion unit 17 converts the number of bits of the decoded image data Db1. s1 is a threshold value corresponding to the decoded image data De1 whose bit number has been converted, and s2 is a threshold value corresponding to the decoded image data De1 + 1 larger by one gradation than the decoded image data De1 whose bit number has been converted. is there.

At this time, the interpolation coefficient k1 is calculated by the following equation (2).
k1 = (Db1-s1) / (s2-s1) (2)
Where s1 <Db1 ≦ s2

  The correction data Dc1 calculated by the interpolation calculation is output from the correction data generator 8 to the correction means 9 as the correction data Dc, as shown in FIG. The correction unit 9 corrects the current image data Di1 based on the correction data Dc, and sends the corrected image data Dj1 to the display unit 10.

  As described above, two correction data corresponding to the decoded image data (De1, Db0) and (De + 1, Db0) using the interpolation coefficient k1 calculated when converting the number of bits of the decoded image data Db1. By calculating the interpolation values of Df1 and Df2 and obtaining the correction data Dc1, it is possible to reduce the influence of the quantization error of the decoded image data De1 on the correction data Dc.

  FIG. 26 is a diagram showing a second configuration of the correction data generator 8 according to the third embodiment. The data conversion means 20 linearly quantizes the decoded image data Db0, converts the number of quantization bits from, for example, 8 bits to 3 bits, and outputs the decoded image data De0 whose bit number has been converted. At the same time, the data conversion means 20 calculates an interpolation coefficient k0 described later. The look-up table 21 outputs two correction data Df3 and Df4 based on the 3-bit decoded image data De0 and the 8-bit decoded image data Db1 whose bit numbers have been converted. The correction data interpolation means 22 generates correction data Dc1 based on the two correction data Df3 and Df4 and the interpolation coefficient k0.

  FIG. 27 is a diagram schematically showing the configuration of the lookup table 21. Here, the decoded image data De0 whose bit number has been converted is 3-bit (8 gradations) data and takes a value of 0 to 7. As shown in FIG. 27, the look-up table 21 has 256 × 9 pieces of data arranged in a two-dimensional manner, and has both values of 8-bit decoded image data Db1 and 3-bit decoded image data De0. Is output as the correction value Df3, and the correction data dt (Db1, De0 + 1) adjacent to the correction value Df3 is output as the correction value Df4.

The correction data interpolation means 22 uses the correction data Df3 and Df4 and the interpolation coefficient k0 to calculate the correction data Dc1 according to the following equation (3).
Dc1 = (1−k0) × Df3 + k0 × Df4 (3)

  FIG. 28 is an explanatory diagram for describing a method of calculating the correction data Dc1 represented by the above equation (3). In FIG. 28, s3 and s4 are threshold values used when the data conversion unit 20 converts the number of quantization bits of the decoded image data Db0. s3 is a threshold value corresponding to the decoded image data De0 whose bit number has been converted, and s4 is a threshold value corresponding to the decoded image data De0 + 1 larger by one gradation than the decoded image data De0 whose bit number has been converted. is there.

At this time, the interpolation coefficient k0 is calculated by the following equation (4).
k0 = (Db0−s3) / (s4−s3) (4)
However, s3 <Db0 ≦ s4

  The correction data Dc1 calculated by the interpolation operation shown in the above equation (3) is output from the correction data generator 8 to the correction means 9 as the correction data Dc. The correction unit 9 corrects the current image data Di1 based on the correction data Dc, and sends the corrected image data Dj1 to the display unit 10.

  As described above, the two correction data corresponding to the decoded image data (Db1, De0) and (Db1, De0 + 1) using the interpolation coefficient k0 calculated when converting the number of bits of the decoded image data Db0. By calculating the interpolation values of Df3 and Df4 and obtaining the correction data Dc1, it is possible to reduce the influence of the quantization error of the decoded image data De0 on the correction data Dc.

  FIG. 29 is a diagram showing a third configuration of the correction data generator 8 according to the third embodiment. The data converters 17 and 20 linearly quantize the decoded image data Db1 and Db0, respectively, and output the decoded image data De1 and De0 obtained by converting the number of quantization bits from, for example, 8 bits to 3 bits. At the same time, the data conversion means 17 and 20 calculate interpolation coefficients k0 and k1, respectively. The lookup table 23 outputs correction values Df1 to Df4 based on the 3-bit decoded image data De1 and De0. The correction data interpolation means 24 generates correction data Dc1 based on the correction values Df1 to Df4 and the interpolation coefficients k0 and k1.

  FIG. 30 is a diagram schematically showing the configuration of the lookup table 23. Here, the decoded image data De1 and De0 whose bit numbers have been converted are 3-bit (8 gradation) data and take values from 0 to 7. As shown in FIG. 30, the look-up table 23 has 9 × 9 data arranged two-dimensionally, and has correction data dt (De1) corresponding to both values of the 3-bit decoded image data De1 and De0. , De0) as the correction value Df1, and three correction data dt (De1 + 1, De0), dt (De1, De0 + 1), dt (De1 + 1, De0 + 1) adjacent to the correction value Df1 are output as correction values Df2, Df3, respectively. Output as Df4.

The correction data interpolation means 24 uses the correction values Df1 to Df4 and the interpolation coefficients k1 and k0 to calculate the correction data Dc1 according to the following equation (5).
Dc1 = (1−k0) × {(1−k1) × Df1 + k1 × Df2}
+ K0 × {(1-k1) × Df3 + k1 × Df4} (5)

  FIG. 31 is an explanatory diagram for describing a method of calculating the correction data Dc1 represented by the above equation (5). In FIG. 31, s1 and s2 are threshold values used when the data conversion means 17 converts the number of quantization bits of the decoded image data Db1, and s3 and s4 are values of the decoded image data Db0 of the decoded image data Db0 by the data conversion means 20. This is a threshold used when converting the number of quantization bits. s1 is a threshold value corresponding to the decoded image data De1 whose bit number has been converted, and s2 is a threshold value corresponding to the decoded image data De1 + 1 larger by one gradation than the decoded image data De1 whose bit number has been converted. is there. In addition, s3 is a threshold value corresponding to the decoded image data De0 whose bit number has been converted, and s4 corresponds to the decoded image data De0 + 1 larger by one gradation than the decoded image data De0 whose bit number has been converted. This is a threshold.

At this time, the interpolation coefficients k1 and k0 are calculated by the following equations (6) and (7), respectively.
k1 = (Db1-s1) / (s2-s1) (6)
Where s1 <Db1 ≦ s2
k0 = (Db0−s3) / (s4−s3) (7)
However, s3 <Db0 ≦ s4

  The correction data Dc1 calculated by the interpolation operation shown in the above equation (5) is output from the correction data generator 8 to the correction means 9 as the correction data Dc, as shown in FIG. The correction unit 9 corrects the current image data Di1 based on the correction data Dc, and outputs the corrected image data Dj1 to the display unit 10.

  As described above, the decoded image data (De1, De0), (De1 + 1, De0), (De1, D2) are calculated using the interpolation coefficients k0 and k1 calculated when the bit numbers of the decoded image data Db0 and Db1 are converted. De0 + 1) and the interpolation values of the four correction data Df1, Df2, Df3, and Df4 corresponding to (De1 + 1, De0 + 1) are calculated, and the correction data Dc1 is obtained, whereby the quantization error of the decoded image data De0 and De1 is reduced. The effect on the correction data Dc can be reduced.

  Note that the correction data interpolation means 19, 22, and 24 may be configured to calculate the correction data Dc1 by using an interpolation operation using a higher-order function other than the linear interpolation.

Embodiment 4 FIG.
FIG. 33 is a diagram showing a configuration of a liquid crystal drive circuit according to the fourth embodiment. The image data processing unit 25 according to the present embodiment includes a data conversion unit, a delay unit 5, a correction data generator 8, and a correction unit 9. The data conversion unit 26 reduces the data capacity by converting the number of quantization bits of the current image data Di1 from, for example, 8 bits to 3 bits. The conversion of the number of quantization bits may use either linear quantization or non-linear quantization. The image data Da1 whose bit number has been converted by the data conversion unit 26 is output to the delay unit 5 and the correction data generator 8. The delay unit 5 outputs the image data Da0 corresponding to the image one frame before the current image by delaying the bit-converted image data Da1 for a period corresponding to one frame.

  The correction data generator 8 outputs correction data Dc based on the image data Da1 and the image data Da0 one frame before. The correction unit 5 corrects the current image data Di1 based on the correction data Dc, and outputs the corrected image data Dj1 to the display unit 10.

  Here, the number of quantization bits of the image data Da0 whose number of bits is converted by the data conversion means 26 may be other than 3 bits, and can be arbitrarily set. The smaller the quantization bit number of the image data Da0 is set, the smaller the memory capacity required for the delay unit 5 to delay the image data Da1 by one frame period. The conversion of the number of quantization bits may be performed using either linear quantization or non-linear quantization.

  The correction data generator 8 holds correction data corresponding to the number of bits of the image data Da1 and Da0.

  FIG. 32 is a flowchart showing the operation of the liquid crystal drive circuit according to the present embodiment. In the image data conversion step (St8), the data conversion means 26 performs bit number conversion for reducing the quantization bit number of the current image data Di1, and outputs new image data Da1 corresponding to the current image data Di1. . In the next image data delay step (St2), the image data Da1 is delayed by the delay means 5 for a period corresponding to one frame. In the correction data generation step (St4), the correction data generator 8 outputs the correction data Dc based on the image data Da1 and Da0. In the image data correction step (St5), the correction means 9 generates the image data Dj1 based on the correction data Dc.

  As described above, in the fourth embodiment, since the data capacity is compressed by converting the number of quantization bits of the current image data Di1, the decoding means is omitted and the configuration of the correction data generator 8 is simplified. And the circuit scale can be reduced.

Embodiment 5 FIG.
FIG. 35 is a diagram showing a configuration of a liquid crystal drive circuit according to the fifth embodiment. In the image data processing unit 27 according to the present embodiment, the correction data generator 28 detects an error between the current image data Di1 and the decoded image data Db1, and corrects the correction data Dc based on the detected error. Restrict. Other operations are the same as those in the first embodiment.

  FIG. 36 is a diagram showing a first configuration of the correction data generator 28 according to the present embodiment. The lookup table 11 outputs correction data Dc1 based on the decoded image data Db0 and Db1. The error determination unit 29 compares the current image data Di1 with the decoded image data Db1 to obtain an error generated in the decoded image data Db1 by the encoding / decoding processing in the encoding unit 4 and the decoding unit 6. Is detected. When the difference between the current image data Di1 and the decoded image data Db1 exceeds a predetermined value, the error determining unit 29 outputs a correction amount limiting signal j1 for limiting the correction amount of the correction data Dc1 to the limiting unit 30. I do.

  The limiter 30 limits the correction amount of the correction data Dc1 based on the correction amount limit signal j1 from the error determiner 29, and outputs new correction data Dc2. The correction data Dc2 output by the limiting unit 30 is output as correction data Dc, as shown in FIG. The correction unit 9 corrects the current image data Di1 based on the correction data Dc.

  FIG. 34 is a flowchart showing the operation of the liquid crystal drive circuit according to the present embodiment shown in FIG. Through the steps from St1 to St4, the correction data Dc1 is generated by the same operation as in the first embodiment. In the subsequent error determination step (St9), the error determination unit 29 detects an error between the current image data Di1 and the decoded image data Db1 for each pixel. In the correction data limiting step (St10), when the error detected by the error determining means 29 exceeds a predetermined value, the value of the correction data Dc1 is limited by the limiting means 30, and new correction data Dc2 is output. . In the image data correction step (St5), the image data Dj1 is corrected by the correction unit 9 based on the correction data Dc2.

  As described above, when the error between the current image data Di1 and the decoded image data Db1 is large, the response speed of the liquid crystal is accurately controlled by controlling the value of the correction data Dc to be small, Deterioration of the display image due to unnecessary correction can be prevented.

  FIG. 37 is a diagram showing another configuration of the correction data generator 28 shown in FIG. As shown in FIG. 37, the data conversion means 12 for converting the number of bits of the decoded image data Db1 may be provided, and the correction data Dc1 may be output based on the decoded image data De1 whose bit number has been converted. .

  As shown in FIG. 38, the correction data generator 28 is provided with the data conversion means 14 for converting the number of bits of the decoded image data Db0, and outputs the correction data Dc1 based on the bit number-converted decoded image data De0. May be configured.

  Further, as shown in FIG. 39, the correction data generator 28 is provided with data conversion means 12 and 14 for converting the number of bits of the decoded image data Db1 and Db0, and the bit number-converted decoded image data De1 and De0 are provided. May be configured to output the correction data Dc1 based on.

  Here, the operation of each configuration of the data conversion means 12, 14 and the look-up tables 13, 15, 16 is the same as that described in the second embodiment. According to the configuration shown in FIGS. 37 to 39, the data capacity of the look-up tables 13, 15, 16 can be reduced, and the circuit scale can be reduced.

  FIG. 40 is a diagram showing a second configuration of the correction data generator 28 according to the present embodiment. The error determination unit 31 detects a difference between the current image data Di1 and the decoded image data Db1 for each pixel, and outputs the detected difference as a correction signal j2. The data correction unit 32 corrects each of the decoded image data Db0 and Db1 for each pixel based on the correction signal j2 output from the error determination unit 31, and looks up the corrected decoded image data Dg1 and Dg0. Output to table 11.

Here, the relationship between the decoded image data Db0 and Db1 and the decoded image data Dg0 and Dg1 corrected by the correction signal j2 is expressed by the following equations (8) to (10).
Dg1 = Db1 + j2 (8)
Dg0 = Db0 + j2 (9)
j2 = Di1-Db1 (10)

  As shown in the above formulas (8) and (9), by adding the correction signal j2 (= Di1-Db1) to each of the decoded image data Db1 and Db0, the decoding is performed along with the encoding / decoding processing. The error component j2 generated in the image data Db1 and Db0 can be canceled.

  The lookup table 11 outputs correction data Dc1 based on the corrected decoded image data Dg1 and Dg0. As shown in FIG. 35, the correction data generator 28 outputs the correction data Dc1 output from the lookup table 11 to the correction unit 9 as correction data Dc.

  As described above, by adding the difference j2 between the current image data Di1 and the decoded image data Db1 to each of the decoded image data Db1 and Db0, the decoded image data Db1 and Db0 are encoded and decoded. Can be corrected. This makes it possible to accurately control the response speed of the liquid crystal and prevent the display image from deteriorating due to unnecessary correction.

The corrected decoded image data Dg1 is equal to the decoded image data Di, as shown in the following equation (11).
Dg1 = Db1 + Di1-Db1 = Di1 (11)
Therefore, as shown in FIG. 41, the current image data Di1 may be input to the look-up table 11 instead of the corrected decoded image data Dg1.

  FIG. 42 is a diagram showing another configuration of the correction data generator 28 shown in FIG. As shown in FIG. 42, by providing the data conversion unit 12 for reducing the number of bits of the decoded image data Dg1 output by the data correction unit 32, the correction data is obtained based on the decoded image data De1 whose bit number has been converted. Dc1 may be configured to be output.

  As shown in FIG. 43, the correction data generator 28 is provided with the data conversion unit 14 for reducing the number of bits of the decoded image data Dg0 output by the data correction unit 32. The correction data Dc1 may be output based on the data De0.

  Further, as shown in FIG. 44, the correction data generator 28 is provided with data conversion units 12 and 14 for reducing the number of bits of the decoded image data Dg1 and Dg0 output by the data correction unit 32, so that the number of bits can be reduced. The correction data Dc1 may be output based on the converted decoded image data Dg1 and Dg0.

  As described above, according to the configurations shown in FIGS. 42 to 44, it is possible to reduce the data capacity of the look-up tables 13, 15, and 16 and to reduce the circuit scale.

  FIG. 45 is a diagram showing a third configuration of the correction data generator 28 according to the present embodiment. If the error between the current image data Di1 and the decoded image data Db1 exceeds a predetermined value, the error determination unit 29 outputs a correction amount limiting signal j1 for limiting the correction amount of the correction data Dc1 to the limiting unit 30. I do. On the other hand, the error determination unit 31 detects a difference between the current image data Di1 and the decoded image data Db1 for each pixel, and outputs the detected difference to the data correction unit 32 as a correction signal j2.

  The data correction unit 32 corrects each of the decoded image data Db0 and Db1 for each pixel based on the correction signal j2 output from the error determination unit 31, and looks up the corrected decoded image data Dg1 and Dg0. Output to table 11. The lookup table 11 outputs the correction data Dc1 based on the corrected decoded image data Dg1 and Dg0, and sends the correction data Dc1 to the limiting unit 30. The limiting unit 30 limits the correction amount of the correction data Dc1 based on the correction amount restriction signal j1, and outputs new correction data Dc2.

  As described above, by correcting the decoded image data Dg1 and Dg0 and the correction data Dc1 based on the error between the current image data Di1 and the decoded image data Db1, the encoding / decoding process is performed. Even when the error between the decoded image data Db1 and Db0 is large, it is possible to accurately control the response speed of the liquid crystal and prevent the display image from deteriorating due to unnecessary correction.

  FIG. 46 is a diagram showing another configuration of the correction data generator 28 shown in FIG. As shown in FIG. 46, by providing the bit number conversion means 12 for reducing the number of bits of the decoded image data Dg1 output by the data correction means 32, the correction based on the bit number-converted decoded image data De1 is performed. It may be configured to output the data Dc1.

  As shown in FIG. 47, the correction data generator 28 includes a data conversion unit 14 for reducing the number of quantization bits of the decoded image data Dg0 output from the data correction unit 32, thereby providing a bit-number-converted decoded data. The configuration may be such that the correction data Dc1 is output based on the structured image data De0.

  Further, as shown in FIG. 48, the correction data generator 28 includes data conversion units 12 and 14 for reducing the number of bits of each of the decoded image data Dg1 and Dg0 output by the data correction unit 32. The correction data Dc1 may be output based on the decoded image data De1 and De0 whose bit numbers have been converted.

  As described above, according to each configuration of the correction data generator 28 shown in FIGS. 46 to 48, it is possible to reduce the data capacity of the look-up tables 13, 15, and 16 and to reduce the circuit scale.

Embodiment 6 FIG.
FIG. 49 is a diagram showing a configuration of a liquid crystal drive circuit according to the sixth embodiment. The image data processing unit 34 according to the present embodiment includes an encoding unit 4, a delay unit 5, a decoding unit, a correction data generator 35, and a correction unit 9. The encoding means 4 encodes the current image data Di1 and outputs encoded data Da1. The delay unit 5 delays the encoded data Da1 for a period corresponding to one frame, and outputs the delayed encoded data Da0. Here, the encoded data Da0 delayed by the delay unit 5 corresponds to the image data one frame before the encoded data Da1. The decoding unit 7 decodes the encoded data Da0 and outputs decoded image data Db0. The correction data generator 35 generates correction data Dc based on the current image data Di1 and the decoded image data Db0, and outputs the correction data Dc to the correction unit 9.

  As shown in FIG. 49, by configuring the correction data generator 35 to generate the correction data Dc based on the current image data Di1 and the decoded image data Db0, the encoded data corresponding to the current image data Di1 is generated. The decoding unit 6 for decoding Da1 can be omitted, and the circuit scale can be reduced.

Embodiment 7 FIG.
FIG. 51 is a diagram showing a configuration of a liquid crystal drive circuit according to the seventh embodiment. The image data processing unit 36 according to the present embodiment includes an encoding unit 4, a delay unit 5, a decoding unit 7, a correction data generator 37, and a correction unit 9. The encoding unit 4 encodes the current image data Di1 and outputs the encoded data Da1 to the delay unit 5 and the correction data generator 37. The delay unit 5 delays the encoded data Da1 for a period corresponding to one frame, and outputs the delayed encoded data Da0 to the decoding unit 7 and the correction data generator 37. Here, the encoded data Da0 delayed by the delay unit 5 corresponds to the image data one frame before the encoded data Da1. The decoding means 7 decodes the encoded data Da0 and outputs the decoded image data Db0 to the correction data generator 37.

  The correction data generator 37 generates correction data Dc based on the current image data Di1, the decoded image data Db0, the encoded data Da1, and the encoded data Da0 output by the delay unit 5. Hereinafter, the operation of the correction data generator 37 will be described in detail.

  FIG. 52 is a diagram illustrating a first configuration of the correction data generator 37. The lookup table 11 outputs correction data Dc1 based on the current image data Di1 and the decoded image data Db0. The comparing means 38 compares the coded data Da0 and Da1, and when the two coded data are the same, there is no need to perform the correction. Output.

  When the coded data Da0 and Da1 are the same based on the correction amount limiting signal j3, the limiting unit 39 sets the value of the correction data Dc1 to 0 and outputs it as new correction data Dc2. The correction data Dc2 output by the restriction unit 39 is output to the correction unit 9 as the correction data Dc, as shown in FIG. The correction unit 9 corrects the current image data Di1 based on the correction data Dc, and outputs the corrected image data Dj1 to the display unit 10.

  FIG. 50 is a flowchart showing the operation of the liquid crystal drive circuit according to the present embodiment shown in FIG. The correction data Dc1 is generated by the same steps from St1 to St4 as in the first embodiment. In the following comparison step (St11), the coded image data Da1 and Da0 are compared by the comparing means 38, and if both are the same data, the correction amount limiting signal j3 is output. In the correction data restriction step (St12), the correction data Dc2 is output by the restriction means 39 based on the correction amount restriction signal j3. In the image data correction step (St5), the current image data Di1 is corrected based on the correction data Dc2 output by the limiting unit 39.

  As described above, when generating the correction data Dc based on the current image data Di1 and the decoded image data Db0, the liquid crystal driving circuit according to the present embodiment performs correction when the encoded data Da0 and Da1 are the same. By setting the value of the data Dc1 to 0, the response speed of the liquid crystal can be accurately controlled, and deterioration of the display image due to unnecessary correction can be prevented.

  FIG. 53 is a diagram showing another configuration of the correction data generator 37 shown in FIG. As shown in FIG. 53, by providing the data conversion means 12 for reducing the number of bits of the decoded image data Db1, it is configured to output the correction data Dc1 based on the decoded image data De1 whose bit number has been converted. Is also good.

  As shown in FIG. 54, the correction data generator 37 is provided with the data conversion means 14 for reducing the number of bits of the decoded image data Db0, so that the correction data Dc1 is based on the bit number-converted decoded image data De0. May be output.

  Further, as shown in FIG. 55, the correction data generator 37 is provided with the data conversion means 12 and 14 for reducing the number of bits of the decoded image data Db1 and Db0, so that the decoded image data De1 whose bit number has been converted is provided. , De0 may be configured to output the correction data Dc1.

  FIG. 56 is a diagram illustrating a second configuration of the correction data generator 37. The data conversion means 17 reduces the number of quantization bits of the decoded image data Db1, calculates the interpolation coefficient k1, and sends the calculated interpolation coefficient k1 to the correction data interpolation means 19. The correction data generating means 18 outputs two correction data Df1 and Df2 based on the decoded image data De1 and the decoded image data Db0 whose bit numbers have been converted, and sends them to the correction data interpolation means 19. The correction data interpolation means 19 calculates the correction data Dc1 based on the correction data Df1 and Df2 and the interpolation coefficient k1, and outputs it to the restriction means 39. The limiting unit 39 limits the correction amount of the correction data Dc1 based on the correction amount limiting signal j3 output by the comparing unit 38, and outputs new correction data Dc2.

  The operations of the data conversion unit 17, look-up table 18, and correction data interpolation unit 19 shown in FIG. 56 are the same as those described in the third embodiment.

  FIG. 57 is a diagram showing a third configuration of the correction data generator 37. The data conversion means 20 performs a bit number conversion process for reducing the number of quantization bits of the decoded image data Db0, calculates an interpolation coefficient k0, and sends the calculated correction data k0 to the correction data interpolation means 22. The look-up table 21 outputs two correction data Df3 and Df4 based on the decoded image data De0 and the decoded image data Db1 whose bit numbers have been converted, and sends them to the correction data interpolation means 22. The correction data interpolation means 22 calculates the correction data Dc1 based on the correction values Df3, Df4 and the interpolation coefficient k0, and outputs the same to the restriction means 39. The limiting unit 39 limits the correction amount of the correction data Dc1 based on the correction amount limiting signal j3 output by the comparing unit 38, and outputs new correction data Dc2.

  The operations of the data conversion means 20, look-up table 21, and correction data interpolation means 22 shown in FIG. 57 are the same as those described in the third embodiment.

  FIG. 58 is a diagram illustrating a fourth configuration of the correction data generator 37. The data conversion means 17 and 20 reduce the number of quantization bits of each of the decoded image data Db1 and Db0, calculate interpolation coefficients k1 and k0, and convert the calculated correction data k1 and k0 to the correction data interpolation means 24. Send to The correction data generating means 23 outputs four correction data Df1, Df2, Df3 and Df4 based on the decoded image data De1 and De0 whose bit numbers have been converted, and sends them to the correction data interpolation means 24. The correction data interpolation unit 24 performs an interpolation operation based on the correction data Df1 to Df4 and the interpolation coefficients k1 and k0, calculates correction data Dc1, and outputs the correction data Dc1 to the limiting unit 39. The limiting unit 39 limits the correction amount of the correction data Dc1 based on the correction amount limiting signal j3 output by the comparing unit 38, and outputs new correction data Dc2.

  The operations of the data conversion units 17 and 20, the look-up table 23, and the correction data interpolation unit 24 shown in FIG. 58 are the same as those described in the third embodiment.

Embodiment 8 FIG.
FIG. 60 is a diagram showing a configuration of a liquid crystal drive circuit according to the eighth embodiment. The image data processing unit 40 in the present embodiment includes a frequency band limiting unit 41. The frequency band limiting unit 41 outputs image data Dh1 obtained by limiting a predetermined frequency component of the current image data Di1. The frequency band limiting unit 41 is configured by, for example, a low-pass filter that limits high frequency components. The encoding unit 4 encodes the image data Dh1 band-limited by the frequency band limiting unit 41, and outputs coded data Da1. The delay unit 5 delays the encoded data Da1 for a period corresponding to one frame, and outputs encoded data Da0. At the same time, the decoding means 6 decodes the encoded data Da1, and outputs decoded image data Db1. The decoding means 7 decodes the encoded data Da0 and outputs decoded image data Db0. The correction data generator 8 generates correction data Dc based on the image data Db1 and Db0. Here, the operation at the subsequent stage of the encoding means 4 is the same as in the first embodiment.

  FIG. 59 is a flowchart showing the operation of the liquid crystal drive circuit according to the present embodiment shown in FIG. In the frequency band limiting step (St13), which is the first step, the image data Dh1 in which a predetermined frequency component of the current image data Di1 is limited by the frequency band limiting means 41 is output. In the next image encoding step (St1), the image data Dh1 whose band has been limited is encoded. The subsequent operations in St2 to St3 are the same as those in the first embodiment.

  As described above, by performing coding after limiting unnecessary frequency components, it is possible to suppress a coding error of the current image data Di1. This makes it possible to accurately control the response speed of the liquid crystal.

  Note that the same effect can be obtained even if the frequency band limiting unit 41 is configured by a band-pass filter that limits predetermined high-frequency components and low-frequency components.

Embodiment 9 FIG.
FIG. 62 is a diagram showing a configuration of a liquid crystal drive circuit according to the ninth embodiment. The noise removing unit 43 removes a noise component of the current image data Di1, and outputs image data Dk1 from which the noise component has been removed. Here, the noise component is a high-frequency component having a small level change. The encoding unit 4 encodes the image data Dk1 output by the noise removing unit 43, and outputs encoded data Da1. The operation at the subsequent stage of the encoding means 4 is the same as in the first embodiment.

  FIG. 61 is a flowchart showing the operation of the liquid crystal drive circuit according to the present embodiment shown in FIG. In the noise removing step (St14), which is the first step, the image data Dk1 from which the noise component of the current image data Di1 has been removed by the noise removing means 43 is output. In the image data encoding step (St1) which is the second step, encoding of the image data Dk1 is performed. The subsequent operations in St2 to St5 are the same as those in the first embodiment.

  As described above, by performing the encoding after removing the noise component, it is possible to suppress the encoding error of the current image data Di1. This makes it possible to accurately control the response speed of the liquid crystal.

Embodiment 10 FIG.
FIG. 64 is a diagram showing a configuration of the liquid crystal drive circuit according to the tenth embodiment. The image data processing unit 44 in the present embodiment includes color space conversion units 45, 46, and 47. The color space conversion means 45 converts the current image data Di1 into a YC signal composed of a luminance signal and a color signal, and outputs the current image data Dm1 of the YC signal. The encoding means 4 encodes the current image data Dm1 and outputs encoded data Da1 corresponding to the current image data Dm1. The delay unit 5 outputs the encoded data Da0 corresponding to the image one frame before the current image by delaying the encoded data Da1 for a period corresponding to one frame. The decoding means 6 and 7 decode the coded data Da1 and Da0, respectively, to obtain the decoded image data Dn1 corresponding to the current image and the coded data Dn0 corresponding to the image one frame before the current image, respectively. Output.

  The color space conversion means 46 and 47 convert the decoded image data Db1 and Db0 of the YC signal composed of the luminance signal and the color signal into R, G and B digital signals, and output the R, G and B image data Dn1. , Dn0. The correction data generator 8 outputs correction data Dc based on the image data Dn1 and Dn0.

  FIG. 63 is a flowchart showing the operation of the liquid crystal drive circuit according to the present embodiment shown in FIG. In a first color space conversion step (St15), which is the first step, image data Dm1 obtained by converting the current image data Di1 into a YC signal including a luminance signal and a color signal by the color space conversion means 45 is output. . In the next image data encoding step (St1), the encoding means 4 outputs encoded data Da1 obtained by encoding the image data Dm1. In the encoded data delay step (St2), the encoded data Da0 one frame before the encoded data Da1 is output by the delay unit 5. In the next image data encoding step (St3), the decoding means 6 and 7 output the encoded data Da1 and the decoded image data Db1 and Db0 obtained by decoding the encoded data Da0 one frame before. In the second color space conversion step (St16), the color space conversion means 46 and 47 convert the decoded image data Db1 and Db0 from YC signals including luminance signals and color signals to R, G and B digital signals. The converted image data Dn1 and Dn0 are output. In the next correction data generation step (St14), correction data Dc is generated based on the image data Dn1 and Dn0.

  As described above, the coding rate (data compression rate) is obtained by converting the R, G, and B signals into image data Dm1 of a YC signal including a luminance signal and a chrominance signal and then performing encoding. Can be enhanced. As a result, it is possible to reduce the memory capacity of the delay unit 5 required for delaying the encoded data Da1.

  It is also possible to configure so that the compression ratio is changed between the luminance signal and the color signal. At this time, by reducing the compression ratio of the luminance signal so that the information is not lost, and increasing the compression ratio of the chrominance signal, the capacity of the encoded data Da1 is reduced and the information necessary for generating the correction data is reduced. Can be maintained.

  FIG. 65 is a diagram showing another configuration of the liquid crystal drive circuit according to the present embodiment. FIG. 65 shows a configuration in a case where the image signal is received by the receiving means 2 as a YC signal including a luminance signal and a chrominance signal. The color space conversion means 49 outputs image data Dn2 obtained by converting the current image data Di1 of the YC signal into R, G, B digital signals. The color space units 46 and 47 output decoded image data Dn1 and Dn0 obtained by converting the decoded image data Db1 and Db0 into R, G, and B digital signals.

Embodiment 11 FIG.
FIG. 66 is a diagram showing a first configuration of the liquid crystal drive circuit according to the eleventh embodiment. As shown in FIG. 66, in the image data processing unit 50 according to the present embodiment, the encoding unit 4 outputs encoded data Da1 obtained by encoding the image data Dj1 output by the correction unit 9. The delay unit 5 outputs the encoded data Da0 that is obtained by delaying the encoded data Da1 by a period corresponding to one frame. The decoding means 6 and 7 output decoded image data Db1 and Db0 obtained by decoding the encoded data Da1 and Da0, respectively. Here, the decoded image data Db1 corresponds to the image data Dj1 output by the correction unit 9, and the decoded image data Db0 corresponds to the image data output one frame before the image data Dj1. The correction data generator 8 outputs correction data Dc based on the decoded image data Db0 and Db1. The correction unit 9 generates new image data Dj1 corresponding to the current image data Di1 by correcting the gradation value of the image data Di1 based on the correction data Dc in the same operation as in the first embodiment, and displaying the image data. Output to the means 10 and the encoding means 4.

  FIG. 67 is a diagram showing the response characteristics of the liquid crystal in the display means 10. 67A shows the current image data Di1 before correction, FIG. 67B shows the value of the corrected image data Dj1, and FIG. 67C shows the response characteristics of the liquid crystal when a voltage based on the image data Dj1 is applied. Is shown. As shown in FIG. 67 (b), when the gradation value of the current image increases as compared to one frame before, the correction value V1 based on the correction data Dc is added to / subtracted from the current image data Di1, thereby obtaining the current image. Is generated, image data Dj1 representing a new image corresponding to. In the display means 10, by applying a voltage based on the image data Dj1 to the liquid crystal, the liquid crystal can be driven to have a predetermined transmittance within substantially one frame period as shown in FIG. 67 (c). As shown in FIG. 67 (b), when the tone value of the current image increases compared to one frame before, the tone value of the corrected image data Dj1 increases by V1 with respect to the current image data Di1. Then, in the next frame, the current image data Di1 is reduced by V3. When the tone value decreases one frame before, the tone value of the corrected image data Dj1 decreases by V2 with respect to the current image data Di1, and in the next frame, the tone value of the corrected image data Dj1 decreases with respect to the current image data Di1. Increase by V4. Thereby, as shown in FIG. 67 (c), the change speed of the display gradation can be improved, and the change in the gradation can be emphasized.

  FIG. 68 is a diagram showing a second configuration of the liquid crystal drive circuit according to the present embodiment. As shown in FIG. 68, a data conversion unit 26 is provided in place of the encoding unit 4, and the number of quantization bits of the image data Dj1 output from the correction unit 9 is converted from, for example, 8 bits to 3 bits to convert the data. The capacity may be compressed.

  FIG. 69 is a diagram showing a third configuration of the liquid crystal drive circuit according to the present embodiment. As shown in FIG. 69, the correction data generator 28 detects an error between the image data Dj1 output by the correction means 9 and the decoded image data Db1, and corrects the correction data Dc based on the detected error. It may be configured to limit the amount.

  FIG. 70 is a diagram showing a fourth configuration of the liquid crystal drive circuit according to the eleventh embodiment. As shown in FIG. 70, the correction data Dc may be generated based on the image data Dj1 output from the correction means 9 and the decoded image data Db0.

  FIG. 71 is a diagram showing a fifth configuration of the liquid crystal drive circuit according to the present embodiment. As shown in FIG. 71, the coded data Da1 and the coded data Da0 delayed by the delay unit 5 may be compared, and if both are the same, the correction amount of the correction data Dc may be limited. .

5 is a flowchart illustrating an operation of the liquid crystal drive circuit according to the first embodiment. FIG. 2 is a diagram illustrating a configuration of a liquid crystal drive circuit according to the first embodiment. FIG. 3 is a diagram showing a configuration of a correction data generator according to the first embodiment. FIG. 3 is a schematic diagram illustrating a configuration of a correction data generation unit according to the first embodiment. FIG. 3 is a diagram illustrating an example of a response speed of a liquid crystal. FIG. 3 is a diagram illustrating an example of a response speed of a liquid crystal. FIG. 4 is a diagram illustrating an example of correction data. FIG. 3 is a diagram illustrating an example of a response speed of a liquid crystal. FIG. 4 is a diagram illustrating an example of correction data. FIG. 4 is an explanatory diagram for describing an operation of the liquid crystal drive circuit according to the first embodiment. FIG. 4 is an explanatory diagram for describing an effect of an encoding / decoding error on current image data. 9 is a flowchart illustrating an operation of the liquid crystal drive circuit according to the second embodiment. FIG. 9 is a diagram illustrating a first configuration of a correction data generator according to a second embodiment. FIG. 13 is a diagram schematically illustrating a configuration of a lookup table illustrated in FIG. 12. FIG. 13 is a diagram schematically illustrating a configuration of a lookup table illustrated in FIG. 12. FIG. 13 is a diagram showing a second configuration of the correction data generator according to the second embodiment. FIG. 16 is a diagram schematically illustrating a configuration of a lookup table illustrated in FIG. 15. FIG. 16 is a diagram schematically illustrating a configuration of a lookup table illustrated in FIG. 15. FIG. 14 is a diagram showing a third configuration of the correction data generator according to the second embodiment. FIG. 19 is a diagram schematically illustrating a configuration of a lookup table illustrated in FIG. 18. FIG. 19 is a diagram schematically illustrating a configuration of a lookup table illustrated in FIG. 18. 9 is a flowchart illustrating an operation of the liquid crystal drive circuit according to the third embodiment. FIG. 13 is a diagram showing a first configuration of a correction data generator according to a third embodiment. 23 is a diagram schematically illustrating a configuration of a lookup table illustrated in FIG. 22. FIG. FIG. 9 is an explanatory diagram for describing a method for calculating correction data. FIG. 13 is a diagram showing a second configuration of the correction data generator according to the third embodiment. FIG. 26 is a diagram schematically illustrating a configuration of a lookup table illustrated in FIG. 25. FIG. 9 is an explanatory diagram for describing a method for calculating correction data. FIG. 14 is a diagram showing a third configuration of the correction data generator according to the third embodiment. FIG. 29 is a diagram schematically illustrating a configuration of a lookup table illustrated in FIG. 28. FIG. 9 is an explanatory diagram for describing a method for calculating correction data. 13 is a flowchart showing an operation of the liquid crystal drive circuit according to the fourth embodiment. FIG. 13 is a diagram illustrating a configuration of a liquid crystal drive circuit according to a fourth embodiment. 13 is a flowchart showing the operation of the liquid crystal drive circuit according to the fifth embodiment. FIG. 13 is a diagram illustrating a configuration of a liquid crystal drive circuit according to a fifth embodiment. FIG. 15 is a diagram showing a first configuration of a correction data generator according to a fifth embodiment. FIG. 36 is a diagram illustrating another configuration of the correction data generator illustrated in FIG. 35. FIG. 36 is a diagram illustrating another configuration of the correction data generator illustrated in FIG. 35. FIG. 36 is a diagram illustrating another configuration of the correction data generator illustrated in FIG. 35. FIG. 15 is a diagram illustrating a second configuration of the correction data generator according to the fifth embodiment. FIG. 40 is a diagram showing another configuration of the correction data generator shown in FIG. 39. FIG. 40 is a diagram showing another configuration of the correction data generator shown in FIG. 39. FIG. 40 is a diagram showing another configuration of the correction data generator shown in FIG. 39. FIG. 40 is a diagram showing another configuration of the correction data generator shown in FIG. 39. FIG. 15 is a diagram showing a third configuration of the correction data generator according to the fifth embodiment. FIG. 45 is a diagram showing another configuration of the correction data generator shown in FIG. 44. FIG. 45 is a diagram showing another configuration of the correction data generator shown in FIG. 44. FIG. 45 is a diagram showing another configuration of the correction data generator shown in FIG. 44. FIG. 13 is a diagram illustrating a configuration of a liquid crystal drive circuit according to a sixth embodiment. 17 is a flowchart showing the operation of the liquid crystal drive circuit according to the seventh embodiment. FIG. 14 is a diagram illustrating a configuration of a liquid crystal drive circuit according to a seventh embodiment. FIG. 21 is a diagram illustrating a first configuration of a correction data generator according to a seventh embodiment. FIG. 52 is a diagram illustrating another configuration of the correction data generator illustrated in FIG. 51. FIG. 52 is a diagram illustrating another configuration of the correction data generator illustrated in FIG. 51. FIG. 52 is a diagram illustrating another configuration of the correction data generator illustrated in FIG. 51. FIG. 15 is a diagram illustrating a second configuration of the correction data generator according to the seventh embodiment. FIG. 15 is a diagram illustrating a third configuration of the correction data generator according to the seventh embodiment. FIG. 21 is a diagram illustrating a fourth configuration of the correction data generator according to the seventh embodiment. 15 is a flowchart showing the operation of the liquid crystal drive circuit according to the eighth embodiment. FIG. 15 is a diagram illustrating a configuration of a liquid crystal drive circuit according to an eighth embodiment. 15 is a flowchart showing the operation of the liquid crystal drive circuit according to the ninth embodiment. FIG. 15 is a diagram showing a configuration of a liquid crystal drive circuit according to a ninth embodiment. 21 is a flowchart showing the operation of the liquid crystal drive circuit according to the tenth embodiment. FIG. 21 is a diagram showing a configuration of a liquid crystal drive circuit according to a tenth embodiment. FIG. 21 is a diagram illustrating another configuration of the liquid crystal drive circuit according to the tenth embodiment. FIG. 21 is a diagram illustrating a first configuration of a liquid crystal drive circuit according to an eleventh embodiment. FIG. 26 is an explanatory diagram for describing an operation of the liquid crystal drive circuit according to the eleventh embodiment. FIG. 21 is a diagram showing a second configuration of the liquid crystal drive circuit according to the eleventh embodiment. FIG. 35 is a diagram illustrating a third configuration of the liquid crystal drive circuit according to the eleventh embodiment. FIG. 35 is a diagram illustrating a fourth configuration of the liquid crystal drive circuit according to the eleventh embodiment. FIG. 21 is a diagram showing a fifth configuration of the liquid crystal drive circuit according to the eleventh embodiment. FIG. 9 is a diagram illustrating a configuration of a conventional liquid crystal drive circuit. FIG. 9 is an explanatory diagram for describing a thinning process of an image memory. FIG. 9 is an explanatory diagram for describing a problem of a thinning process.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 Input terminal, 2 receiving means, 3 image data processing parts, 4 encoding means, 5 delay means, 6 encoding means, 7 encoding means, 8 correction data generator, 9 correction means, 10 display means, 11 correction data Generation means, St1 image data encoding step, St2 encoded data delay step, St3 image data encoding step, St4 correction data generation step, St5 image data correction step.

Claims (7)

A liquid crystal drive image processing circuit that corrects and outputs image data representing the gradation value of each pixel of the image corresponding to the voltage applied to the liquid crystal based on the temporal change in the gradation value of each pixel. So,
First color conversion means for converting image data consisting of R, G, and B signals representing the image of the current frame into a luminance signal and a color signal;
An encoding unit that outputs encoded image data corresponding to the image of the current frame by encoding the luminance signal and the color signal,
Decoding means for outputting the first decoded image data corresponding to the image data of the current frame by decoding the encoded image data output by the encoding means;
Delay means for delaying the encoded image data output by the encoding means for a period corresponding to one frame;
Decoding means for decoding the encoded image data output by the delay means to output second decoded image data corresponding to the image data one frame before the current frame;
Second color space conversion means for converting the first decoded image data into image data composed of R, G, B signals;
Third color space conversion means for converting the second decoded image data into image data consisting of R, G, B signals;
Based on the first decoded image data and the second decoded image data converted into image data composed of R, G, and B signals by the second color space conversion unit and the third color space conversion unit. Correction data generating means for outputting correction data for correcting the gradation value of the image of the current frame;
A liquid crystal driving image processing circuit, comprising: a correction unit configured to correct image data representing the image of the current frame based on the correction data. 2. The image processing circuit for driving a liquid crystal according to claim 1, wherein said encoding means sets a compression rate of the color signal higher than a compression rate of the luminance signal. 3. The liquid crystal driving image processing circuit according to claim 1, wherein the correction data is set so that the liquid crystal has a transmittance corresponding to a gradation value determined by the image data within one frame period. An image processing method for correcting image data representing a gradation value of each pixel of an image corresponding to a voltage applied to a liquid crystal based on a temporal change in a gradation value of each pixel,
Image data composed of R, G, and B signals representing the image of the current frame is converted into a luminance signal and a color signal;
Generate the encoded image data corresponding to the image data of the current frame by encoding the luminance signal and the color signal, respectively.
Decoding first encoded image data corresponding to the image data of the current frame obtained by decoding the encoded image data, and delaying the encoded image data by a period corresponding to one frame; Converting the second decoded image data corresponding to the image data one frame before the current frame obtained by the above into image data consisting of R, G, B signals, respectively,
An image processing method comprising: correcting the image data of the current frame based on the first decoded image data and the second decoded image data converted into image data including R, G, and B signals. . 5. The image processing method for driving a liquid crystal according to claim 4, wherein the compression ratio of the color signal is set higher than the compression ratio of the luminance signal. 6. The liquid crystal driving device according to claim 4, wherein the image data of the current frame is corrected so that the liquid crystal has a transmittance corresponding to a gradation value determined by the image data within one frame period. Image processing method. A liquid crystal display device characterized by comprising a liquid crystal driving image processing circuit according to any one of claims 1 to 3.

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