JP3574345B2 - RF control device and its application system - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an RF controller for applying a high-frequency signal for beam acceleration to an acceleration cavity in a medical accelerator system, and an RF controller and an application system thereof.
[0002]
[Prior art]
As a conventional example of the RF acceleration device, for example, Reference 1 (Heavy Particle Cancer Therapy Device Construction Comprehensive Report NIRS-M-109 HIMAC-009, May 1995 "High Frequency Acceleration" Mitsutaka Kanazawa, pp. 44-49. There is a heavy particle accelerator HIMAC described in General Research Institute.
[0003]
The general configuration of the ring accelerator will be described using the synchrotron shown in FIG. 10 as an example. The synchrotron includes an electromagnet 1 for forming a circular orbit, an accelerating cavity 2 for accelerating a beam using high frequency, and a vacuum duct 3 serving as a passage for passing the beam. Other devices include a pre-accelerator 6 for accelerating the beam in advance, an injector 5 for injecting the accelerated beam into the vacuum duct 3, a beam monitor 4 for measuring the position of the beam, and the like. It is composed of an emitting device 7 for sending out.
[0004]
The magnetic field of the electromagnet 1 changes according to a predetermined pattern as the beam accelerates. At the same time, the revolving frequency of the beam also changes, so that it is necessary to control the frequency of the high-frequency signal applied to the acceleration cavity 2 in accordance with a predetermined pattern in order to stably accelerate.
[0005]
Next, a general acceleration control system will be described with reference to FIG. Since the beam causes a phenomenon called synchrotron oscillation during acceleration, the beam becomes unstable if there is any disturbance to the beam as it is. As a countermeasure, a measure is usually taken to attenuate synchrotron oscillation by performing frequency feedback control based on the phase difference between the beam signal detected by the beam monitor 4 and the phase monitor circuit 14 and the high-frequency signal for acceleration. This is the phase control loop 20 shown in the figure.
[0006]
If the frequency of the accelerating cavity 2 deviates from the optimum frequency determined by the magnetic field of the electromagnet 1, the beam position deviates from the ideal center trajectory, and this is detected by the beam monitor 4 and the position monitor circuit 15. In addition, feedback control of the frequency of the high-frequency signal is also performed. This is the displacement control loop 21 shown in FIG.
[0007]
Further, the voltage actually applied to the acceleration cavity 2 is detected by the voltage monitor 13, and the amplitude of the high-frequency signal is controlled based on the detection signal. This is the cavity voltage control loop 22 shown in the figure.
[0008]
As another configuration of the acceleration control system, 9 is a digital control circuit, and the digital control circuit 9 is a device that performs an operation for feedback of a high-frequency signal. Reference numeral 8 denotes a memory module. The memory module 8 is a device for storing data for controlling the accelerating cavity. The digital control circuit 9 sequentially sends pattern data for accelerating cavity operation. 10 is a digital synthesizer for generating a high frequency signal for beam acceleration, 11 is an AM modulator for controlling the amplitude of the high frequency signal, 12 is an amplifying device for amplifying the modulation output, and 19 is for controlling the memory module 8. Is a calculator. The function of the computer 19 is to transmit pattern data to the memory module and the timing system 16.
[0009]
The pattern data transmission is performed before the operation of the accelerator starts, and the high-frequency control of the computer has no real-time property. A timing system 16 controls data read timing of the memory module 8. Reference numeral 18 denotes a B clock generator for generating a B clock signal in the memory module 8 according to the magnetic field monitor 17 of the bending electromagnet 1.
[0010]
Next, a general operation method of a pattern used for accelerating a synchrotron will be described with reference to a timing chart of FIG. In this timing chart, the magnetic field strength of the electromagnet and the name of the operation cycle are shown in time series in the order of times T1 to T7.
[0011]
The period indicated by T1 is called a flat bottom and is a state of the lowest energy of the synchrotron. In the flat bottom, a beam enters from the pre-accelerator 6 and accumulates in the synchrotron. Next, the high-frequency signal that was in the OFF state is turned on, and the voltage is increased so that the beam is captured so as to match the fixed phase of the high-frequency signal.
[0012]
Next, in a period indicated by T2, the beam is accelerated by controlling the frequency and voltage of the high-frequency signal based on the magnetic field fluctuation of the electromagnet. When the excitation speed of the magnetic field is mostly constant, the start and end of acceleration are distinguished from each other and called smoothing.
[0013]
Next, when the beam reaches a predetermined energy, the acceleration is terminated and the state enters a flat top state in which the magnetic field does not change. In the flat top, fine adjustment of the voltage and frequency of the high-frequency signal is performed in order to create conditions suitable for emitting the beam from the synchrotron. This period is defined as T3.
[0014]
Next, at T4, the beam is emitted out of the synchrotron according to the request of the beam user. During the period T4, the high-frequency signal may be turned off or may be kept on. Next, after a predetermined time has elapsed or when the beam has been used up, preparations are made to lower the magnetic field of the synchrotron. This preparation period is defined as T5.
[0015]
Next, the magnetic field of the synchrotron is reduced to the minimum value during the period T6. The synchrotron returns to the flat bottom state again, and returns the power supply to the initial state in a period of T7. Of the accelerated beam, the portion left behind in the synchrotron may be discarded with a flat top, but when the magnetic field is reduced, the high frequency signal may be turned on to hold the beam, decelerate, and then discarded. Therefore, T6, which is the fall period from the flat top to the flat bottom, is called deceleration. The above operation cycle is called an acceleration cycle or a pulse.
[0016]
Next, a clock for controlling data transfer sent from the memory module 8 to the digital control circuit 9 will be described. There are two types of clocks, a B clock and a T clock, and pattern data is transmitted from the memory module 8 to the digital control circuit 9 by these clocks. The B clock is generated by the B clock generator 18 based on the result of detecting the magnetic field of the electromagnet 1 with the magnetic field monitor 17. For example, it is a device that outputs one clock pulse every time the magnetic field changes by 0.2 Gauss.
[0017]
The two clocks are selectively used in T1 to T7 which determine the pattern operation. It is common to use the B clock in a portion where the magnetic field change is large in the operation pattern and use the T clock in a portion where the change in the magnetic field is zero or small. For example, the T clock is used in a portion where the magnetic field change is zero, such as T1, T3, T5 and T7, and the B clock is used in other portions.
[0018]
The B + clock is used for the portion where the magnetic field increases, and the B− clock is used for the portion where the magnetic field decreases. The event signals include a master signal, an operation start signal, a memory clock stop / restart signal, and a memory clock switching signal shown in FIG.
[0019]
[Problems to be solved by the invention]
The conventional acceleration control device as described above has a problem that flexibility in control is limited. In other words, at the time of start-up adjustment of the synchrotron, the optimal operation method and parameters are often not known in advance, and adjustment is generally performed by trial and error while actually operating the accelerator. It took a lot of effort and time to actually start up.
Further, the conventional acceleration control device lacks a function for searching for an optimal pattern.
In addition, flexibility such as changing a constant in real time was insufficient.
[0020]
In addition, in the conventional acceleration control device, the timing of switching between the B clock and the T clock depends on an external timing system, and thus is restricted by specifications such as the resolution of the timing system.
Further, there is a restriction due to the processing speed in the memory address control at the time of switching, and the switching time can be set to flat top or flat bottom, but it has not been easy to change to switching at any other time.
[0021]
If it is possible to operate under different conditions for each cycle, beam adjustment after the accelerator construction can be performed more smoothly, and in applications such as cancer treatment equipment, it is desirable to operate with different energy for each cycle, but conventional acceleration The control device stores a large number of patterns and operating constants, and cannot switch and operate each cycle.
[0022]
In addition, the conventional acceleration control device cannot change the operation parameters during the cycle, such as changing the feedback constant or the calculation method during the beam acceleration. Since the instability of the accelerator depends on the beam energy, such an operation that controls the feedback constant in real time may be desirable.
[0023]
The present invention has been made to solve the above-described problems, and has as its object to obtain an RF control device capable of improving flexibility during operation and operation adjustment.
[0024]
[Means for Solving the Problems]
The RF control device according to the first aspect of the present invention is created in advance by a computer in correspondence with the flat base period, the acceleration period, the flat top period, and the deceleration period indicating the change in the deflection magnetic field of the annular accelerator. Supports multiple driving patterns A frequency reference signal, a voltage reference signal, a beam position reference signal of a high-frequency signal for driving an acceleration cavity, and a bit data (switching bit) string as a final switching bit for notifying final data of a storage area are read by an external clock. A storage means comprising a data storage area and a control data storage area for storing pattern information and a start address of a data string in each area, and an external signal or a last switching bit in bit data, for storing the data. Means for switching the cycle of the data read clock of the means to a different cycle, and a memory control means for switching the area of the read data based on the address information previously stored in the control data storage area, and a high-frequency signal read from the storage means. Frequency reference signal, voltage reference Feedback control means for comparing the frequency signal and the beam position reference signal with the monitor signals corresponding to the beam position, the phase and the voltage, and feedback-controlling the frequency and voltage of the high-frequency signal for driving the acceleration cavity. .
[0025]
The memory control means of the RF controller according to the second aspect of the present invention selectively switches the T clock generated at a fixed interval generated by the timing system and the B clock output according to a change in the deflection magnetic field of the annular accelerator. Performs address jump and clock switching operation by an external signal based on arbitrary switching bit data in bit data Things.
[0027]
Claim 3 The storage means of the RF control apparatus according to the invention has a plurality of memory storage areas corresponding to one operation pattern, and stores the plurality of memory storage areas in a higher-level computer that creates pattern data for operating the accelerator. A memory access control means capable of accessing a higher-level communication control function for controlling data communication or a function of reading a reference signal to a calculation function in the feedback control means and writing data designated in advance of the calculation function to the memory storage area. It is provided.
[0028]
Claim 4 The feedback control means of the RF control apparatus according to the invention reads the reference signal read by the memory access control means and the monitor signal of the beam position, phase, and voltage, and subtracts the result of subtraction and subtraction of the beam position reference signal from the beam position monitor signal. Performs a proportional integration operation based on a constant, multiplies the result of the proportional integration operation by a constant, multiplies a phase monitor signal by a constant, adds each multiplication result to a frequency reference signal, and generates a frequency signal with a digital frequency oscillator. It is provided with frequency data calculation means for setting the amplitude of the frequency signal by subtracting the voltage monitor signal and the voltage reference signal and multiplying the subtraction result by a constant, and a function capable of rewriting each constant for each acceleration cycle.
[0029]
Claim 5 The storage means of the RF control apparatus according to the invention has a constant memory function of storing a plurality of operation constants and a memory function of having a constant switching bit for switching a constant in bit data, and the constant switching bit or an external A constant is read from the constant memory function according to a signal and an output frequency.
[0030]
Claim 6 The frequency data calculation means of the RF control apparatus according to the invention sets an upper limit and a lower limit to the frequency data to be sequentially updated according to the reference clock and applied to the digital frequency oscillator, and to the amount of change in the data indicating the amplitude of the high-frequency signal for each update. It has a function.
Claim 7 In the RF control apparatus according to the invention, at least a part of the configuration is configured using an FPGA (Filled Programmable Gate Array) which is a kind of programmable semiconductor device.
Claim 8 An application system of the RF control device according to the invention of Claims 1 to 6 The RF controller drives the accelerator to emit a beam.
Claim 9 An application system of the RF control device according to the invention of Claims 1 to 7 A beam emitted from an accelerator driven by an Rf control device is guided to an irradiation device, and the irradiation device irradiates the beam to an affected part.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a diagram showing a configuration of an RF control device according to Embodiment 1 of the present invention. In the figure, reference numeral 50 denotes a memory module that stores data for controlling the acceleration cavity and sequentially sends a reference signal to a feedback control unit 59; 59, a feedback control unit that performs an operation for feedback; and 62, a frequency setting unit. Yes, it is composed of a frequency generator, an AM modulator, a gain adjustment amplifier and the like. Reference numeral 63 denotes an AD conversion unit that converts the analog detection signals 103 to 105 detected by each monitor into digital signals.
[0032]
Reference numeral 51 denotes a higher-level communication control unit that controls communication with a higher-level computer, and 52a denotes a memory storage area that stores pattern data for controlling an acceleration cavity. Reference numeral 57 denotes a data reading function unit, which includes a pattern control setting unit 53 for setting a pattern control method, a memory clock switching control unit 54 for setting a memory clock switching signal, and an operation pattern timing for controlling a memory clock for reading pattern data. The control unit 55 includes an arithmetic memory control unit 56 that performs arithmetic memory control.
[0033]
Reference numeral 50 denotes a memory module, which includes a higher-level communication control unit 51, a memory storage area 52a, a data read function unit 57, and a memory access control unit 58a.
In the conventional example, a combination of the memory module 8, the digital control circuit 9, the digital synthesizer 10, and the AM modulator 11 corresponds to the RF control device of the present invention.
[0034]
The beam position monitor signal 103 indicates the displacement control loop 21, the beam phase monitor signal 104 indicates the phase control loop 20, and the voltage monitor signal 105 indicates the cavity voltage control loop 22. The B clock is input via the timing system. As the event signal 102, a master signal, an operation start signal, a memory clock stop / restart signal, a memory clock switching event, a monitor control signal for controlling each monitor (for each monitor) Independent), T clock, B (+) clock, B (-) clock.
[0035]
Here, the memory storage area 52a will be described in detail. The memory storage area 52a includes a control data storage area 60 having pattern control data indicating the type of operation pattern and a memory clock to be used, a start address indicating the address of read start data of each data area, and data corresponding to each operation period. It comprises a data storage area 61 having an area.
[0036]
In each storage area of the data storage area 61, a series of data is stored in the reading order for each clock. Each series of data is stored for each address, and the series of data is composed of pattern data of 20-bit frequency reference data, 12-bit voltage reference data, 12-bit beam position reference data, and 4-bit bit control data. The last data of each data area may be indicated by bit control data, or the address of the last data may be indicated in the control data storage area in the same manner as the start address.
[0037]
The pattern control setting unit 53 sets a pattern control command 128 indicating the order of clock switching and start address switching according to the pattern control data 117 read from the address 0 of the control data storage area 60 of the memory storage area 52a. The memory switching control unit 54 sets the memory clock switching method according to a command from the host computer, whether to perform switching using the memory clock switching event 129 and the final switching bit 118 or to perform switching using the ideal switching bit 119, and A memory clock switching signal 121 is output to the pattern timing controller 55.
[0038]
Next, a memory address control and a memory clock switching method in the present device will be described. As an example, the case where the T clock is used in the normal operation and the memory clock switching method uses the memory clock switching event 129 and the last switching data bit 118 will be described.
[0039]
First, the host computer outputs a pattern data write command and pattern data to the host communication control unit 51 in order to write the pattern data into the memory storage area 52a. The memory access control unit 58 that has received the data for data transfer 111 and the memory control signal for data transfer 110 from the higher-level communication control unit 51 turns the data for data transfer 111 into memory data 124, 123 and a memory control signal 122 are output, and writing is performed as needed in the memory storage area 52a.
[0040]
Regarding the cycle operation, first, the operation pattern timing control unit 55 outputs a pattern control data read command 114 according to the operation start command 108. The calculation memory control unit 56 outputs a calculation memory control signal 115 so as to read address 0 where the pattern control data is stored. The memory access control unit 58 outputs the memory address 123 and the memory control signal 112 in accordance with the operation memory control signal 115, reads out the pattern control data 117 at address 0, and outputs it to the pattern control setting unit 53.
[0041]
Since the pattern control data 117 indicates that the type of operation is the normal operation and the clock is the T clock, the pattern control setting unit 53 operates the pattern control command 128 indicating the order of clock switching and start address switching. Output to the pattern timing control unit 55. Further, the memory clock switching control section 54 outputs a memory clock switching signal 121 to the operation pattern timing control section 55 in accordance with the memory clock switching command 109.
[0042]
The operation pattern timing control unit 55 outputs a start address control signal to read the address 1 storing the start address of the data area # 1 at the rise of the operation start signal which is the event signal 102 in accordance with the pattern control command 128. Then, the arithmetic memory control unit 56 outputs the arithmetic memory control signal 115 according to the start address control signal 112.
[0043]
The memory access control unit 58a reads the start address of the data area # 1 and passes it to the arithmetic memory control unit 56. In the reading of the data area, the memory control signal 115 for operation is output while sequentially incrementing the address from the start address of the data area # 1 according to the memory clock 113 synchronized with the T clock which is the event signal 102. The memory access control unit 58a outputs the memory address 123 and the memory control signal 124 according to the operation memory control signal 115, reads the memory data 123, and performs feedback control on the frequency reference data 125, the beam position reference data 126, and the voltage reference data 127. It outputs the final switching bit 118 and the ideal switching bit 119 to the memory clock switching controller 54.
[0044]
The operation pattern timing control unit 55, which has received the memory clock switching event 129 as the event signal 102 as the memory clock switching signal 121, repeats the above operation with the T clock as the memory clock 112, and starts the data area from address 2 of the memory storage area 52a. The start address control signal 112 is output so as to read the start address of # 2, the start address 116 is read, and the memory clock 113 is output in synchronization with the B (+) clock which is the event signal 102.
[0045]
At the same time, the data of the frequency reference data 125, the beam position reference data 126, the voltage reference data 127, the last switching bit 118, and the ideal switching bit 119 are read from the newly read start address while sequentially incrementing the address according to the memory clock 113. Hereinafter, data reading is performed in the same manner.
[0046]
Here, when the last switching bit 118 in the bit data of the data read from the data storage area is input first from the memory clock switching event which is the event signal 102, the setting and start of the memory clock are performed by the last switching bit 118. The address is read.
[0047]
The memory clock switching method may have a configuration of only an ideal switching bit or only a memory clock switching event and a final switching bit.
[0048]
As described above, according to the present invention, when the memory clock switching event, which is the event signal 102, is not detected due to noise or the like, the final switching bit 118 of the memory storage area 52a can be used as a limiter, and operation can be performed without any trouble. Is continued.
[0049]
Conventionally, the memory clock can be switched only at a timing given by an external timing system. However, by using the switching bit, the switching timing can be determined independently only by the high frequency system, and the interface with the timing system can be reduced.
[0050]
Further, the switching timing accuracy can be determined without depending on the resolution of the timing system. Normally, the high-frequency system requires a stricter resolution than other devices of the synchrotron, and the resolution of the entire timing system can be reduced by separating the high-frequency system.
[0051]
Embodiment 2 FIG.
In the first embodiment, the case where the memory storage area 52a including one bank is provided has been described. As shown in FIG. 2, the RF control device according to the second embodiment includes a data read function 57, a feedback control unit 59, a frequency setting unit 62, an AD conversion unit 63, and a data reading function 57 having the same functions as those of the first embodiment. A memory storage area 52b having a plurality of banks according to the embodiment, a data transfer control with a host computer, a read control of pattern data to a feedback control unit 59, and a data specified in advance by an arithmetic unit are stored in a memory. It is composed of a memory access control unit 58b that performs control for saving data in a designated bank of the storage area 52b. Note that the frequency setting unit 62 and the AD conversion unit 63 are omitted in the figure.
[0052]
Next, the configuration of the memory storage area 52b according to the present embodiment will be described in detail. The memory function having a plurality of storage banks corresponding to one operation pattern is composed of two blocks # 1 and # 2 composed of one or more banks, and a memory address and a memory control are independently provided for each block. It has signals and memory data.
The memory access control unit 58b determines which block in which block the data transfer and operation control signals are to be output to, which data input / output destination, and a preset bank for storing operation data. And save timing settings.
[0053]
Next, the operation of the present embodiment will be described.
An example of operation in a case where pattern data for calculation is read from bank # 1 of block # 1 and pattern data is transferred from a host computer to bank # 11 of block # 2 will be described.
[0054]
First, assuming that the pattern data has been written to the bank # 1 from the higher-level computer, the higher-level communication control unit 51, which has received a command from the higher-level computer to read the pattern data from the bank # 1, In synchronization with the master signal, the control-specific bank designation 130 is output to the memory access control unit 58b so as to read the pattern data from the bank # 1 of the block # 1.
Further, an operation start command 108 is output to the operation pattern timing control unit 55, and pattern data is read out in the same manner as in the first embodiment.
[0055]
On the other hand, the host computer sends a command and data to the host communication control unit 51 to write the pattern data to the bank # 11. When the upper-level communication control unit 51 determines that the bank # 11 is the block # 2 and the memory access is not performed in the block # 2, the higher-level communication control unit 51 sets the control bank designation 130 so as to perform the data transfer to the bank # 11 of the block # 2. The data is output and the data is transferred to bank # 11 according to a preset procedure.
[0056]
By providing the memory access control unit 58b with timing control of data transfer control and read control for calculation, the memory access control unit 58b can be configured as a common one without having independent memory addresses, memory control signals, and memory data for each block. Is also good.
[0057]
An example of an operation method when writing calculation data such as frequency setting data and a position monitor signal to a memory will be described.
[0058]
The operation in the case of reading operation pattern data from bank # 1 and writing operation data to bank # 3 will be described.
[0059]
The higher-level communication control unit 51, which has received a command from the higher-level computer to read the pattern data from the bank # 1 and write the operation data to the bank # 3, synchronizes with the master signal of the event signal 102, The pattern data is read from the bank # 1 to the access control unit 58b, and the bank designation by control 130 is output so that the operation data is written to the bank # 3. At the same time, the operation start command 108 is transmitted to the operation pattern timing control unit 55. Output to Then, data reading is performed in the same manner as described above.
[0060]
After performing the arithmetic processing based on the read pattern data, the feedback control section 59 outputs arithmetic data such as a preset output frequency value and a position monitor signal to the memory access control section 58b. The memory access control unit 58b that has received the operation data writes the operation data to the bank # 3 using the address used for reading in the bank # 1 as it is. Similarly, every time pattern data is read from bank # 1, the operation data is written to bank # 3.
Note that the bank in which the arithmetic data is written may not be in the same block as the bank in which the arithmetic data is read.
[0061]
As described above, according to the present invention,
Not only pattern data but also operation data can be read out to a host computer. The operation data read out to the host computer is corrected in accordance with a preset method, and the pattern data is written back to the designated bank in the memory storage, and the operation is performed, whereby the repetitive control can be performed.
[0062]
In addition, by reading operation data such as an output frequency value and a monitor signal to a host computer, a beam state during operation can be monitored.
[0063]
Also, by having a plurality of banks, when switching and operating each cycle, there is no need to write data from the host computer between cycles, and since data stored in the bank is used in advance, reliability is improved. Switching can be performed in a short time. In the beam adjustment at the time when the construction of the accelerator has been completed, the optimal pattern data is rarely known in advance, and these are often obtained experimentally from measurements using a beam. Therefore, by writing a plurality of pattern data in the bank, it is possible to shorten the time for finding the optimum pattern data.
[0064]
Embodiment 3 FIG.
The RF control device according to the third embodiment includes a memory module 50 that stores data for controlling the high-frequency acceleration cavity and sends a reference signal to the sequential feedback control as shown in FIG. It comprises a switchable feedback control section 59, a frequency setting section 62 including a frequency oscillator, a gain adjustment amplifier, and the like, and an AD conversion section 63.
[0065]
The configuration of the feedback control unit 59 will be described in detail. The feedback control unit 59 generates an operation start clock having a constant cycle for updating data based on the event signal 102 from the timing system, and controls the timing of updating the reference signal, monitor signal, and output data from the memory module. , An arithmetic function 72 for performing an arithmetic operation for feedback using a reference signal, a monitor signal, and a constant, a constant for rewriting is temporarily held, and each constant is output to the arithmetic function 72. A constant buffer 73 a is configured by a data buffer 74 a that holds a reference signal and outputs the reference signal to the arithmetic function 72.
[0066]
The arithmetic function 72 includes a latch 78 for holding the monitor signal digitally converted by the AD converter 63, an arithmetic unit such as an addition 79, a subtraction 80, a multiplication 81, and a proportional integration 82, a frequency setting data 106, and an amplitude setting data 107. It comprises an output control unit 83 for adjusting the output timing.
Here, details regarding the frequency setting unit 62 and the AD conversion unit 63 are omitted.
[0067]
Next, the operation of the feedback control unit according to the present embodiment will be described.
Upon receiving the operation start signal, which is the event signal 102, the operation timing control unit 71 generates an operation start clock having a constant cycle. When the reference signal is stored in the data buffer 74a from the memory module, the reference signal is output to the calculation function 72 in synchronization with the calculation start clock.
[0068]
On the other hand, upon receiving the monitor control signal as the event signal 102, the operation timing control unit 71 outputs a monitor enable signal 144 for latching the monitor signal in synchronization with the operation start clock. The calculation function 72 starts the calculation in accordance with the calculation start clock, subtracts the beam position reference signal 126 and the beam position monitor signal 141, performs proportional integration based on a constant g3, and multiplies the data by a constant g4, The data obtained by multiplying the phase monitor signal 142 by the constant g2 and the frequency reference signal 125 are added to set the frequency.
[0069]
Further, the voltage reference signal 127 and the voltage monitor signal 143 are subtracted, multiplied by a constant g1, and the amplitude is set. The frequency setting data 106 and the amplitude setting data 107 are output by the output enable signal 145 at the end of the calculation. Based on the frequency setting data 106 and the amplitude setting data 107, the frequency setting unit 62 converts the frequency into a frequency using the frequency setting unit 62 or the like, sets the amplitude using a gain adjustment amplifier, and outputs the frequency as the frequency 101. The monitor signal is updated at each calculation start clock, and the calculation process and the frequency setting data 106 and the amplitude setting data 107 are updated.
[0070]
The reference signal updates data in synchronization with the operation start clock only when stored in the data buffer 74a. When the monitor control signal is OFF, the monitor signal is not input, and thus the arithmetic processing is performed with the monitor signal set to 0. When a new constant is stored in the constant buffer 73a by a command from the host computer during the pattern operation, the constant is updated in synchronization with the master signal. The same operation as described above is performed.
[0071]
As described above, according to the present invention, the feedback constant can be changed for each cycle operation, and the accelerator can be easily adjusted.
In the beam adjustment at the time of the completion of the accelerator construction, it is rare that the optimum feedback constant and filter constant are known in advance, and these are often obtained experimentally from measurements using a beam. Since these constants can be changed for each cycle as in the embodiment, optimization of the constants becomes easy.
In addition, since feedback control by digital operation is performed, stable and highly reliable operation can be performed.
[0072]
Embodiment 4 FIG.
FIG. 4 shows an operation timing control unit 71, an operation function 72, a constant buffer 73a for holding each constant output to the operation function 72 according to the third embodiment, and constant switch bit data other than the above-described pattern data. Fourth Embodiment A feedback control unit according to the fourth embodiment including a data buffer 74b, a constant control unit 91 for reading constants from a constant memory area, and a constant memory area 92 storing a plurality of constants used in the cycle operation. FIG. Note that the output from the arithmetic function 72 is omitted in the figure.
Further, 1 bit of the bit control data of the bank storage area shown in the first embodiment is set to a constant switching bit, or the bit control data is increased by 1 bit.
[0073]
Next, the operation of the present embodiment will be described.
Each constant at address 0 in the constant memory area is read out by the master signal before the start of the operation, and stored in the constant buffer 73b. The constant control unit 91, having received the constant switching bit from the data buffer 74b, increments the address in the constant memory area 92 in synchronization with the operation start clock, reads each constant at address 1, and updates the constant in the constant buffer 73b. Each time a constant switching bit is input, the address to be output to the constant memory area is incremented, read as needed, and the constant is updated.
[0074]
As described above, according to the present invention, the constant can be changed at any time during the cycle operation, so that an optimum constant can be set according to the assumed operating condition, which is advantageous for controlling instability.
In the operation of the synchrotron, the sign of the phase is inverted at a certain energy called a transition. Therefore, when passing this energy during acceleration, the sign of the feedback circuit must be reversed instantaneously.
[0075]
According to the present embodiment, the sign can be easily inverted, and the timing of the inversion can be set freely. Furthermore, for various beam instabilities depending on the energy generated in the accelerator, not only the phase but also the voltage control constant can be changed according to the energy.
[0076]
Embodiment 5 FIG.
FIG. 5 is a configuration diagram of a feedback control unit according to the fifth embodiment including an operation timing control unit 71, an operation function 72, a constant buffer 73a, a data buffer 74b, a constant control unit 91, and a constant memory function 92. Note that the output from the arithmetic function 72 is omitted in the figure.
[0077]
This embodiment is different from the fourth embodiment in that reading from the constant memory area 92, which has been performed by the constant switching bit in the embodiment H, is performed by a constant switching event from the event signal 102.
[0078]
As described above, according to the present embodiment, the constant can be changed by an external command during the cycle operation. For example, by controlling the beam disturbance and thereby changing the feedback constant, the control of the instability can be performed. Is advantageous.
[0079]
Embodiment 6 FIG.
FIG. 6 shows a case in which the frequency setting data 106 is received from the arithmetic timing control unit 71, arithmetic function 72, constant buffer 73a, data buffer 74b, constant control unit 91, constant memory function 92 arithmetic function 72, and a preset threshold value FIG. 15 is a configuration diagram of a feedback control unit according to a sixth embodiment including a comparator 93 for comparing with a control circuit; Note that the output from the arithmetic function 72 is omitted in the figure.
[0080]
The feedback control unit according to the present embodiment compares the reading from the constant memory area 92 performed by the constant switching bit 151 or the constant switching event 152 with the frequency setting data in the comparator 93 and a preset threshold value. This is different from the fifth embodiment.
[0081]
As described above, according to the present invention, an optimal constant can be set according to the acceleration frequency during the cycle operation, which is advantageous for controlling instability.
[0082]
Embodiment 7 FIG.
The seventh embodiment is provided with an arithmetic timing control having two or three constant switching methods as shown in the fourth to sixth embodiments and an arithmetic timing control function having a constant switching control function, and the constant switching is performed by a command from a host computer. The method can be set.
[0083]
As described above, according to the present invention, various operations can be performed by having a plurality of switching methods.
[0084]
Embodiment 8 FIG.
FIG. 7 shows that the output control unit 83 according to the third embodiment sets an upper limit and a lower limit for the amount of change in the frequency setting data and the amplitude setting data for each update, and outputs such that the frequency and amplitude do not change beyond the set values. Is provided with a function of performing the above control. 83b is an output control unit according to the present embodiment. Other configurations are the same as in the third embodiment.
[0085]
An example of the operation of restricting the output signal of the output control unit 83b that operates differently from the third embodiment will be described. The frequency setting data 106 and the amplitude setting data 107 updated by the operation clock are respectively subtracted from the immediately preceding data, and the difference between the obtained change amount and the preset upper and lower limit values of the respective change amounts are calculated. The comparison is performed, and if the variation is within the set value, the data is updated as it is. If the variation is equal to or greater than the set value, the excess is added or subtracted to update the data.
[0086]
As described above, according to the present embodiment, unnecessary frequency response can be suppressed, so that stable accelerator operation is possible. Further, even if the feedback control is hindered for some reason, the protection of the high-frequency amplifier and the like is provided.
It should be noted that the RF control device according to each of the above embodiments may be configured so that at least a part of its configuration is formed using an FPGA (Filled Programmable Gate Array) which is a kind of programmable semiconductor device.
[0087]
Embodiment 9 FIG.
FIG. 8 is a diagram showing an example in which the RF control device is applied to a high-frequency beam emitting device. A device called a high-frequency knockout electrode 29 as a means for emitting a beam from a synchrotron as described in Document 2 (P. Strolin “Resonant Extraction from the CERN Intercepting Storgae Rings”, CERN 69-6 (1969)). Is used.
[0088]
In this beam emission method, a perturbation is given to a beam circulating in the synchrotron by applying a high frequency of a specific frequency output from the RF control device and amplified by the power amplifier 31 between two electrodes of the high frequency knockout electrode 29, Some particles in the beam cause instability.
[0089]
Upon emission, real-time control of the amplitude and frequency of the high frequency applied to the electrodes is performed by the digital synthesizer 10 and the AM modulator 11 in the RF control device. In general, the beam current waveform is measured by the beam current monitor 27 and the information is fed back to the AM modulator 11 so that the current waveform of the output beam is generally in a desired shape.
If the above-described high-frequency module is applied to such an apparatus, it is easy to adjust the parameters of the feedback control for the reasons described above.
[0090]
Embodiment 10 FIG.
FIG. 9 shows an example of a cancer treatment apparatus in which an accelerator using the above high-frequency control module and an irradiation apparatus for irradiating a patient with a beam are combined. The irradiation device may be the same as that shown in, for example, Reference 3 (Mitsubishi Electric Technical Report Vol. 69 No. 2 (1995) p34 Kazuhiro Ueda et al., "HIMAC treatment / irradiation system").
[0091]
In the drawings, the same reference numerals as those in FIGS. 10 and 11 indicate the same or corresponding parts. In the figure, reference numeral 6 denotes a pre-stage accelerator for accelerating an incident beam and injecting it into the incident device 5. Reference numeral 24 denotes an irradiation device, which irradiates the beam emitted from the emission device 7 to the affected part of the patient. The operations of the high-frequency control module and the accelerator are the same as those described with reference to FIGS.
[0092]
【The invention's effect】
According to the present invention, a flat base period, an acceleration period, a flat top period, and a deceleration period indicating changes in the deflection magnetic field of the annular accelerator are created in advance by a computer. Supports multiple driving patterns A frequency reference signal, a voltage reference signal, a beam position reference signal of a high-frequency signal for driving an acceleration cavity, and a bit data (switching bit) string as a final switching bit for notifying final data of a storage area are read by an external clock. A storage means comprising a data storage area and a control data storage area for storing pattern information and a start address of a data string in each area, and an external signal or a last switching bit in bit data, for storing the data. Means for switching the cycle of the data read clock of the means to a different cycle, and a memory control means for switching the area of the read data based on the address information previously stored in the control data storage area, and a high-frequency signal read from the storage means. Frequency reference signal, voltage reference And a feedback control means for feedback-controlling the frequency and voltage of the high-frequency signal for driving the acceleration cavity by comparing the monitor signal corresponding to the beam signal, the beam position reference signal and the beam position, the phase, and the voltage. Since control can be performed, there is an effect that adjustment at the time of starting the accelerator can be easily performed.
[0093]
According to the present invention, the memory control means selectively switches between the T clock generated at a fixed interval generated by the timing system and the B clock output in accordance with the change in the deflection magnetic field of the annular accelerator, whereby the B clock and the T clock are output. There is an effect that the switching is facilitated and the operation of the accelerator can be made flexible.
[0094]
According to the present invention, the address jump and the clock switching operation by the external signal are performed based on arbitrary switching bit data in the bit data, so that the switching timing can be independently determined only by the high frequency system. Interface can be reduced, and the resolution of the entire timing system can be reduced.
[0095]
According to the present invention, the storage means has a plurality of memory storage areas corresponding to one operation pattern, and performs data communication between the memory storage areas and a higher-level computer that creates pattern data for operating the accelerator. Since the host communication control function to control or the arithmetic function in the feedback control means can be accessed by the function of reading the reference signal, and the memory access control means capable of writing the data specified in advance to the memory storage area is provided. When operating by switching the pattern data for each cycle, there is no need to write data from the host computer between cycles, and the reliability is improved by using the data stored in the memory area in advance, and the switching can be performed. There is an effect that it can be performed in a short time.
[0096]
According to the present invention, the feedback control unit reads the reference signal and the beam position, phase, and voltage monitor signals read by the memory access control unit, subtracts the beam position reference signal from the beam position monitor signal, and determines the result of the subtraction based on a constant. Performs a proportional integral operation, multiplies the result of the proportional integral operation by a constant, multiplies a phase monitor signal by a constant, adds each multiplication result to a frequency reference signal, generates a frequency signal with a digital frequency oscillator, and generates a voltage monitor signal. Frequency data calculation means for setting the amplitude of the frequency signal by performing subtraction of the voltage reference signal and the subtraction result and a constant, and a function capable of rewriting each constant for each acceleration cycle. Can be updated, and the accelerator can be easily adjusted. There is an effect that kill.
[0097]
According to the present invention, the storage means has a constant memory function for storing a plurality of operation constants, and a memory function having a constant switching bit for switching constants in bit data. By reading the constant from the constant memory function according to the frequency, the constant can be changed at any time during the cycle operation, so that there is an effect that an optimum constant can be set according to the assumed operating condition.
[0098]
According to the present invention, the frequency data calculation means has a function of setting upper and lower limits to the frequency data to be sequentially updated according to the reference clock and to be applied to the digital frequency oscillator, and the amount of change in the data indicating the amplitude of the frequency signal for each update. Therefore, unnecessary frequency response can be suppressed, so that there is an effect that stable operation of the accelerator becomes possible.
[0099]
According to the present invention, there is an effect that the time from the start-up of the apparatus to the actual treatment by beam irradiation can be shortened.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an RF control device according to a first embodiment of the present invention.
FIG. 2 is a configuration diagram of an RF control device according to Embodiment 2 of the present invention.
FIG. 3 is a configuration diagram of an RF control device according to a third embodiment of the present invention.
FIG. 4 is a configuration diagram of feedback control according to Embodiment 4 of the present invention.
FIG. 5 is a configuration diagram of feedback control according to Embodiment 5 of the present invention.
FIG. 6 is a configuration diagram of feedback control according to Embodiment 6 of the present invention.
FIG. 7 is a configuration diagram of feedback control according to Embodiment 8 of the present invention.
FIG. 8 is a configuration diagram of a high-frequency beam emitting device according to a ninth embodiment of the present invention.
FIG. 9 is a configuration diagram of a cancer treatment apparatus according to Embodiment 10 of the present invention.
FIG. 10 is a configuration diagram of a conventional annular accelerator.
FIG. 11 is an explanation of a general acceleration control system.
FIG. 12 is an explanatory view of a general operation method used for accelerating a synchrotron.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Bending electromagnet, 2 accelerating cavities, 3 vacuum ducts, 4 beam monitors, 5 injectors, 6 pre-accelerators, 7 emitting devices, 8 memory modules, 9 digital control circuits, 10 digital synthesizers, 11 AM modulators, 12 power amplifiers , 13 voltage monitor, 14 phase monitor circuit, 15 position monitor circuit, 16 timing system, 17 magnetic field monitor, 18 B clock generator, 19 computer, 20 phase control loop, 21 displacement control loop, cavity voltage control loop 50 memory Module, 51 upper-layer communication control, 52a, 52b memory storage area, 53 pattern control setting section, 54 memory clock switching control section, 55 operation pattern timing control section, 56 operation memory control section, 57 data reading section, 58a, 58b memory access Control unit, 59 feedback Control section, 60 control data storage area, 61 data storage area, 62 frequency setting section, 63 AD conversion section, 71 operation timing control section, 72 operation functions, 73a, 73b constant buffer, 83b output control section, 91 constant control section, 92 Constant memory area, 93 comparator.

Claims (9)

A frequency reference signal of a high-frequency signal for driving an accelerating cavity corresponding to a plurality of operation patterns prepared in advance by a computer in correspondence with a flat base period, an acceleration period, a flat top period, and a deceleration period indicating a change in the deflection magnetic field of the annular accelerator. , A voltage reference signal, a beam position reference signal, and a bit data (switching bit) string, which is a final switching bit for notifying the final data of the storage area, are read out by an external clock. A data read clock cycle of the storage means is switched to a different cycle in accordance with an external signal or a last switching bit in the bit data, and a storage means comprising a control data storage area storing a start address of a data string in the area. Together with the control data storage area. Memory control means for switching a read data area based on the read address information, and a frequency reference signal, a voltage reference signal, a beam position reference signal of the high frequency signal read from the storage means and corresponding to the beam position, phase, and voltage. An RF control device, comprising: feedback control means for performing feedback control of the frequency and voltage of a high-frequency signal for driving an acceleration cavity by comparing with a monitor signal. The memory control means selectively switches the T clock generated at a fixed interval generated by the timing system and the B clock output in response to a change in the deflection magnetic field of the annular accelerator, and performs an address jump and a clock switching operation by an external signal in the bit data. 2. The RF control device according to claim 1, wherein the control is performed based on arbitrary switching bit data . The storage means has a plurality of memory storage areas corresponding to one operation pattern, and stores the memory storage areas in a higher-level communication controller that controls data communication with a higher-level computer that creates pattern data for operating the accelerator. And a memory access control means capable of accessing a function or an arithmetic function of the feedback control means by a function of reading a reference signal and writing data designated in advance of the arithmetic function to the memory storage area. Item 7. The RF control device according to Item 1 . The feedback control unit reads the reference signal and the beam position, phase, and voltage monitor signals read by the memory access control unit, subtracts the beam position reference signal from the beam position monitor signal, and calculates the result of the subtraction as a proportional integral operation based on a constant. The result of the integration operation is multiplied by a constant, the phase monitor signal is multiplied by a constant, the result of each multiplication is added to a frequency reference signal, and a frequency signal is generated by a digital frequency oscillator. 2. The apparatus according to claim 1, further comprising frequency data calculating means for setting the amplitude of the frequency signal by performing subtraction, multiplication of the subtraction result and a constant, and a function capable of rewriting each constant for each acceleration cycle . RF controller. The storage means has a constant memory function for storing a plurality of operation constants, and a memory function having a constant switching bit for switching a constant in bit data, and the constant memory is provided by the constant switching bit or an external signal and an output frequency. The RF controller according to claim 1, wherein a constant is read from the function . The frequency data calculating means has a function of setting upper and lower limits on frequency data to be sequentially updated according to a reference clock and applied to a digital frequency oscillator, and a change amount of data indicating the amplitude of a frequency signal for each update. The RF controller according to claim 5 , wherein 7. The RF controller according to claim 1, wherein at least a part of the configuration is configured using an FPGA (Filled Programmable Gate Array), which is a kind of programmable semiconductor device . 7. An application system of an RF controller, wherein the RF controller according to claim 1 drives an accelerator to emit a beam . 8. An application system of an RF control device, wherein a beam emitted from an accelerator driven by the Rf control device according to claim 1 is guided to an irradiation device, and the irradiation device irradiates the beam to an affected part. .

Images