JP3559774B2 - Ultrasonic receiving beam forming apparatus using multi-stage delay elements - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an ultrasonic imaging apparatus using a digital beam focusing technique, and more particularly to a reception beam forming apparatus including a multi-stage delay element and processing a plurality of scan lines or beams.
[0002]
[Prior art]
As is known, ultrasound imaging systems using transducer arrays include a large number of transducers in a phased, convex or linear array. Such a system comprises a plurality of channels each having a transmitter and a receiver connected to a corresponding transducer. The transmitter transmits an ultrasonic pulse to a target such as a human body. In order to focus the ultrasound energy so transmitted on a specific portion of the target, a sequential time delay is applied to the pulses. The amount of time delay for each pulse is determined so that each transmission pulse reaches the target point at the same time. These pulses pass through different materials / media and are focused on the target, and the reflected pulses then pass through the material / media again to return to the transducer train.
[0003]
Since the distances from the target to the respective array elements are different from each other, the ultrasonic energy reflected from the target reaches the respective array elements at different times. The receive beamformer amplifies the signal received from each array element, time-delays the amplified signal, and sums all the delayed signals. In this case, the delay value for each delay element is determined such that the receive scan line is focused at a predetermined point. Also, the delay value for each delay element changes constantly so that the focus point advances in the radial direction.
[0004]
An ultrasound image is shaped by scanning a desired area in the body with a transmission scan line and processing the signals / data reflected therefrom. In this case, it is important to increase the frame rate in order to obtain a high-quality image. The frame rate is determined by the number of scanning lines used for imaging, the frequency of ultrasonic waves, and the depth of a region where an image is to be formed. A method for improving the frame rate is a multi-beam focusing technique in which ultrasonic pulses are transmitted to form a large number of scan lines or beams simultaneously.
[0005]
In the multiple beam forming apparatus, since different delay amounts are applied to each channel and each beam, there is a disadvantage that the complexity of the system is increased as compared with the case of a single beam. In particular, the capacity of a memory element used as a delay element is greatly increased. The required memory element capacity of a conventional beamforming apparatus increases in proportion to the number of channels, the maximum delay, and the number of beams shaped after one transmission. For example, for a system with 64 channels, quad beams, a maximum delay of 1000 system clock periods, and each data is represented by 10 bits, a considerable memory space corresponding to 64 × 4 × 1000 × 10 Is required.
[0006]
[Problems to be solved by the invention]
Accordingly, an object of the present invention is to provide a beam forming apparatus having a novel structure capable of reducing the size of a delay memory.
[0007]
Another object of the present invention is to provide a multi-focus ultrasonic imaging apparatus that focuses a large number of receiving scan lines from a reflected signal of an ultrasonic signal that forms one transmission scan line, and has data for a large number of receiving scan lines. Is to provide a beam forming apparatus that time-multiplexes and generates the same.
[0008]
[Means for Solving the Problems]
To achieve the above object, according to a preferred embodiment of the present invention, there is provided an ultrasonic receiving beam forming apparatus for processing signals received from an ultrasonic transducer train, wherein N and M are smaller than the number of transducers. when an integer, added delay for forming the N reception beam for the data samples of the M channels to be supplied from the M transducers, summing the delayed data samples of M channels and generating an intermediate output of the M channels, a plurality of beam shaping means, summing and outputting data representing the N received beams by summing the intermediate output of the M channels from the plurality of beam shaping means Means for each channel corresponding to an integer multiple of the system clock period for data samples of the channel for each channel . A coarse delay element for adding a first delay, and a fine delay element for adding a second delay smaller than the system clock period, and further comprising at least two data samples delayed by the coarse delay element and the fine delay element of each channel . comprises a first adder for adding about the channel, and a plurality of multi-channel delay element to add a third delay relative to the output from the first adder, data samples coarse delay elements are used in the molding of each beam Means for controlling the data write pointers of the N first-in, first-out storage means, and means for independently controlling the data read pointers of the N first-in, first-out storage means. And wherein each data sample stored in the N first-in first-out storage means is determined based on the value of the first delay. And the intermediate outputs of the M channels for the N received beams are supplied to the summing means in a time multiplexed manner, and the summing means is means for outputting data representing the N received beams in a time multiplexed manner. An ultrasonic receiving beam forming device is provided.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.
[0010]
FIG. 1 is a schematic block diagram of a four-channel beamforming apparatus according to a preferred embodiment of the present invention, which simultaneously processes data samples received from a four-channel ultrasonic transducer array.
[0011]
The beam forming apparatus shown in FIG. 1 applies a coarse time delay to each channel data sample in four different stages, filters and time-multiplexes each time-delayed channel data, and adds the time-multiplexed channel data to each channel data sample. The intermediate data is multiplied by an apodization factor obtained from a predetermined apodization curve, and the resultant data is summed to generate an intermediate output. Summing the intermediate outputs from multiple beamformers produces a time-multiplexed final output representing up to four focused beams, with each time gap in the time-multiplexed output data corresponding to each received beam. I do. In an ultrasonic imaging apparatus that generates one reception scanning line or beam by combining data from 64 channels, 16 beam forming apparatuses as shown in FIG. 1 are required.
[0012]
Although a beamforming device can simultaneously provide intermediate outputs for shaping up to four received beams, the number of beams formed at one time can vary, for example, depending on the center frequency of the ultrasound signal.
[0013]
The time delay generated by the beamforming device includes a coarse delay and a fine delay. The coarse delay is a delay corresponding to an integral multiple of the system clock period, and as shown in FIG. Embodied in Each register or delay element delays data by controlling the time at which read data is output. Fine delays smaller than the system clock period are implemented in each channel by finite impulse response (FIR) filter and multiplexer (MUX) blocks 18a-18d as shown in FIG. In each channel, the apodization for adjusting the size of the data sample is determined by multipliers 24a to 24d and apodization generators 22a to 22d. The summation is performed by four adders 26a, 26b, 30 and 34 in three different stages.
[0014]
Referring to FIG. 1, data from each transducer element (not shown) or each channel is input to analog-to-digital (A / D) converters 10a to 10d and sampled. The sample data from each of the A / D converters 10a to 10d is supplied to a corresponding input buffer, that is, I_FIFOs 12a to 12d, and time-delayed. That is, the coarse delay for the first channel input is provided by a series of FIFOs 14a, 20a, 28a and 32, the coarse delay for the second channel input is provided by a series of FIFOs 14b, 20b, 28a and 32, and the coarse delay for the third channel input. The delay is provided by a series of FIFOs 14c, 20c, 28b and 32, and the coarse delay for the fourth channel input is provided by a series of FIFOs 14d, 20d, 28b and 32. The fine delay for each channel input is performed by the corresponding FIR filters & MUXs 18a to 18d.
[0015]
In each channel, each I_FIFO 12a to 12d is connected in parallel to E_FIFOs 14a1 to 14a4, 14b1 to 14b4, 14c1 to 14c4, 14d1 to 14d4 having four E_FIFOs. For example, the sample data from the first channel is simultaneously recorded in all four E_FIFOs 0 to 3 in the E_FIFO 14a1. These four E_FIFOs 0 to 3 each perform a time delay corresponding to each receive beam to generate each output delayed at a different time. The delay outputs from the four E_FIFOs 0 to 3 are time-multiplexed by a multiplexer (see FIG. 3) and filtered by an FIR filter to perform a fine delay on the sample data. Hereinafter, the time multiplexing and the filtering will be described in more detail with reference to FIGS.
[0016]
In each channel, the filtered and time-multiplexed data is input to the second stage G_FIFOs 20a to 20d. These G_FIFOs 20a-20d perform a second coarse time delay. Thereafter, the output data from each G_FIFO 20a-20d is apodized by corresponding multipliers 24a-24d and apodization generators 22a-22d. More specifically, each of the multipliers 24a to 24d calculates an output from the corresponding G_FIFO 20a to 20d and an apodization coefficient obtained from a predetermined apodization curve in the corresponding apodization generator 22a to 22d. Multiply. Here, each apodization generator 22a-22d may include a memory (not shown) for storing the apodization curve.
[0017]
Outputs from two adjacent channels (multipliers 24a and 24b and multipliers 24c and 24d) are added in adders 26a and 26b, respectively. The added data is stored in the M_FIFOs 28a and 28b, respectively. These M_FIFOs 28a and 28b perform a third coarse time delay on the input data. Subsequently, the time-delayed data from the M_FIFOs 28 a and 28 b are added together in the adder 30 and stored in the L_FIFO 32. The L_FIFO 32 performs a fourth coarse time delay on the input data from the adder 30.
[0018]
The reasons for applying the coarse time delay in four different stages are as follows. The difference in delay applied to data samples from multiple channels to shape multiple beams will vary with the distance between channels and / or between beams. Specifically, the difference in delay between two adjacent channels and / or between beams is smaller than the difference between non-adjacent channels. Therefore, the E_FIFOs 14a1 to 14d4 that perform the first coarse delay process the maximum delay difference between the four beams in the respective channels. Each of the G_FIFOs 20a to 20d performing the second coarse delay processes the maximum delay difference between two adjacent channels not processed in the first stage. The M_FIFOs 28a and 28b, which perform the third coarse delay, process the delay differences between four adjacent channels that were not processed in the first and second stages, respectively. The L_FIFO 32 that performs the fourth coarse delay processes a delay difference between channels processed by another beamforming apparatus.
[0019]
As described above, since the delayed sample data from the two channels is added in the adders 26a and 26b, only two M_FIFOs 28a and 28b are required in the third stage. Similarly, since the delay sample data from the four channels is added by the adder 30, only one L_FIFO 32 is required in the fourth stage. Therefore, by arranging the delay elements and the adders in a hierarchical structure as shown in FIG. 1, the size of the memory required for obtaining the focusing delay can be greatly reduced.
[0020]
In one embodiment of the present invention, the maximum time delays applied by E_FIFO, G_FIFO, M_FIFO and L_FIFO are 64, 256, 256 and 1024 clock periods, respectively. That is, by setting the time delay caused by the L_FIFO to be longer than the time delay caused by the other FIFOs, the size of the memory can be reduced as much as possible.
[0021]
As shown in FIG. 1, the summation process is performed in three different stages. The adder 26a in the first stage sums the delayed sample data output from the upper two channels (ie, channel 0 and channel 1), and the adder 26b in the first stage adds the lower two channels (ie, channel 2 and channel 3). ) Are added together. The adder 30 in the second stage sums the delayed outputs from the adders 26a and 26b. An adder 34 in the third stage sums the intermediate outputs from the multiple beamformers (only one shown in FIG. 1) to produce a final result representing up to four received beams.
[0022]
FIG. 2 is a diagram illustrating an operation of the E_FIFO according to a preferred embodiment of the present invention. In FIG. 2, _{D i} is a data supplied from each channel is written into each one by 1 E_FIFO0~E_FIFO3. As shown in FIG. 2, the write pointer (Wr_Ptr) indicating the data write bit position is located at the same place on all E_FIFOs and moves one bit at a time for each data write. Thus, the sample data from the four channels is written at the same time. However, the time to be input to the FIR filter & MUX registers subsequent stages _{D i} written in each E_FIFO is read (described later with reference to FIG. 3) each beam (or each E_FIFO) phase against different. As shown in FIG. 2, the read pointer (Rd_Ptr) indicating the data read position can specify a different position.
[0023]
In FIG. 2, in the case of E_FIFO0, data is read out 5 clock cycles after writing, and in the case of E_FIFO2, it is read out 3 clock cycles and different delays are applied to the two beams. As described above, the amount of delay applied to each channel and each beam is adjusted by the difference in position between the write pointer and the read pointer. The positions of these pointers are adjusted by the FDCU 16 in FIG. Specifically, the amount of delay is adjusted by moving the read pointer one memory location per clock cycle based on the delay curve.
[0024]
FIG. 3 is a diagram illustrating the FIR & MUX 18 in FIG. 1 in detail. As shown in FIG. 3, the shift register unit 110 includes four sets of 16-tap registers. Each set of registers stores 16 consecutive data read from the corresponding E_FIFO. In one embodiment of the present invention, each data from the E_FIFO includes 10 bits, and each register can store 10 bits.
[0025]
These 16 consecutive data are filtered by a 16 tap filter indicated by Cij. The coefficients of each filter are selected from eight predetermined coefficient sets (Ci0 to Ci7) using 8: 1 MUXs 120, 122, and 124. In one embodiment of the present invention, the filter coefficients Cij are predetermined in a separate filter coefficient bank (not shown) and supplied to the FIR & MUX unit 18. The coefficient selection signal is used to control the 8: 1 MUXs 120 to 124 to select any one of the eight filter coefficient sets. This coefficient selection signal is determined by the fine delay amount applied in the FIR & MUX unit 18.
[0026]
The filtering of the 16 continuous data is performed in a time multiplexing manner by selecting one set of 16 tap registers of the four sets in the shift register unit 110 using the 4: 1 MUXs 112, 114, and 116. The beam select signal is input to each of the 4: 1 MUXs 112, 114, and 116 and indicates which of the four beams is to be processed. Thereafter, the filter coefficients selected by the 8: 1 MUX are multiplied by the 16 data selected by the 4: 1 MUXs 112, 114, 116. Filtering is performed on data sequentially supplied from E_FIFO0, E_FIFO1, E_FIFO2, and E_FIFO3. That is, the filtering is sequentially repeated for each beam.
[0027]
The shift enable signal in FIG. 3 functions to control the shift of data in the register at a specific clock cycle when data from each E_FIFO is input to the 16-tap register. In the clock cycle in which the read pointer moves in FIG. 2, the shift enable signal controls each register so that data is shifted in the register. If the read pointer remains to adjust the delay value, the shift enable signal is disabled so that data is not shifted in the register. By synchronizing the movement of the read pointer with the movement of the data in the shift register in this way, the same data is prevented from being redundantly written to the register. This is because if the same data is repeatedly written into the register, an error may occur when obtaining the interpolation data from the corresponding data.
[0028]
FIG. 4 is a diagram for explaining the function of the FIR filter in FIG. The fine delay is implemented using an interpolation filter. By properly selecting the FIR filter coefficients, a fine delay with a value less than the system clock period can be applied to the delayed sample data. By applying a fine delay smaller than the system clock period to data samples in this manner, a delay error can be eliminated.
[0029]
The input waveform shown in FIG. 4 represents data input from the E_FIFO to the register set. The FIR filter in FIG. 3 is an interpolation filter for finding an intermediate value between sample data in an input waveform. FIG. 4 illustrates the function for a 4-tap interpolation filter for convenience.
[0030]
While the preferred embodiments of the present invention have been described above, those skilled in the art will be able to make various modifications without departing from the scope of the present invention.
[0031]
【The invention's effect】
Therefore, according to the present invention, it is possible to reduce the size of a memory required for implementing a delay element by using a delay element having a multi-stage structure and sharing some of the delay elements in the plurality of channels. Can be. In addition, processing multiple beams in a time multiplexed manner can further reduce overall hardware complexity.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of a 4-channel beam forming apparatus according to a preferred embodiment of the present invention.
FIG. 2 is a diagram illustrating an operation of an E_FIFO according to a preferred embodiment of the present invention;
FIG. 3 is a diagram showing FIR & MUX in FIG. 1 in detail.
FIG. 4 is a diagram for explaining a function of an FIR filter in FIG. 3;
[Explanation of symbols]
14a1-14d4 First-stage delay elements 20a-20d Second-stage delay elements 28a, 28b Third-stage delay element 32 Fourth-stage delay elements 18a, 18b, 18c, 18d FIR & MUX
26a, 26b, 30, 34 adder

Claims (3)

An ultrasonic receiving beam forming apparatus for processing a signal received from an ultrasonic transducer array,
When N and M are positive integers less than the number of transducers, a delay for shaping N receive beams is added to the data samples of M channels supplied from the M transducers, and the M A plurality of beamforming means for summing the delayed data samples of the plurality of channels to generate an intermediate output of the M channels;
Summing means for summing the intermediate outputs of the M channels from the plurality of beamforming means and outputting data representing the N received beams,
Each of the beam forming means,
A coarse delay element for adding a first delay corresponding to an integral multiple of a system clock period to a data sample of the channel, and a fine delay element for adding a second delay smaller than the system clock period for each channel; further,
A first adder for adding data samples delayed by the coarse delay element and the fine delay element of each channel for at least two channels;
A plurality of multi-channel delay elements for adding a third delay to the output from the first adder;
The coarse delay element,
N-channel first-in first-out storage means for storing data samples used for shaping each beam;
Means for controlling the data write pointers of the N first-in first-out storage means identically;
Means for independently controlling data read pointers of said N first-in first-out storage means,
Each data sample stored in the N first-in first-out storage means is read at a time determined based on the value of the first delay,
An intermediate output of the M channels for the N receive beams is supplied to the summing means in a time multiplexed manner, and the summing means outputs data representing the N received beams in a time multiplexed manner. An ultrasonic receiving beam forming apparatus, characterized in that: 2. The ultrasonic receiver according to claim 1, wherein the fine delay element includes a plurality of interpolation filters, each of the interpolation filters using a data sample set from a channel to determine interpolation data between the data samples. Beam forming equipment. The fine delay element,
N shift register sets each having L shift registers, each set storing L consecutive data samples from each channel;
Multiplexing means for selecting any one of the N shift register sets and supplying the L consecutive data samples stored in the selected shift register set;
Selecting means for selecting any one of a plurality of predetermined filter coefficient sets, each set having L filter coefficients, based on the value of the second delay;
Means for multiplying the L consecutive data samples supplied from the multiplexing means with the L filter coefficients supplied from the selecting means, and summing the L multiplied results. The ultrasonic receiving beam forming apparatus according to claim 1, wherein:

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