JP3549471B2 - Electronic circuit block - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electronic circuit block including a plurality of functional components such as an SIO chip.
[0002]
[Prior art]
In recent years, further miniaturization of portable small electric equipment using batteries has been attempted, but the capacity of the built-in battery has become a bottleneck, and the limitation of miniaturization has been pointed out. That is, the proportion of the battery in this type of electrical equipment is relatively large, and the overall size of the equipment can be reduced by reducing the size and weight of the battery. However, as the battery capacity decreases, the usable time of the equipment also decreases.
[0003]
In response to such inconveniences, efforts have been made to reduce the power consumption of each functional component and electronic circuit constituting the electric device. For example, a CPU is provided with a power saving mode to minimize power consumption during standby. Further, for example, it is conceivable that the operation is stopped by always turning off the power supply, and the corresponding function is turned on at a necessary timing, for example, in units of an IC chip having a predetermined function.
[0004]
[Problems to be solved by the invention]
However, in the method of controlling the energization on / off in units of IC chips as described above, the chances of turning off the power in an actual use state are limited, and the rate of contributing to power saving is small.
[0005]
The present inventor has continued to consider such inconvenience, and as a result, the IC chip is composed of a plurality of functionally separable small pieces, and even if the IC chip as a whole is required to be constantly energized. Even so, when considering the operation timing of each small piece, the small pieces that need to be operated at all times are limited to a very small number, and even for other small pieces, the time when the operation is required It was found that it was limited to a short time.
[0006]
The present invention has been made based on such knowledge, and an electronic circuit capable of effectively saving power by separating an electronic circuit into functional pieces that can operate at the same time and regulating the operation timing of each functional piece. The purpose is to provide blocks.
[0007]
The “functional component piece” described above and below includes a component having a predetermined function or an electronic circuit having a new function by combining the component, and if the operation timing can be individually controlled, the size of the component is small. The contents of the functions and functions are not limited. The “electronic circuit block” includes not only a single IC chip composed of only functional component pieces, but also a combination of a plurality of IC chips or a partial electronic circuit having a plurality of functional component pieces. However, the configuration is not limited.
[0008]
[Means for Solving the Problems]
The electronic circuit block 11 according to the present invention, as schematically shown in FIG. 1, separates an electronic circuit having a predetermined function into functional component pieces 10 that can operate simultaneously. Only the necessary minimum functional component pieces 10a are operated, and the operation of the functional component pieces 10 that have finished operation is stopped by turning off the drive signal 12 such as a power supply voltage or a clock signal by the switching means 14. On the other hand, a signal is sent to the functional component pieces 10 to be operated next, and the functional component pieces 10 to be operated are sequentially changed.
[0009]
The electronic circuit block 11 is an SIO chip illustrated in FIGS. 2 and 3 and uses a data signal output from the functional component piece 10 whose operation has been completed to operate the functional component piece 10 to be operated next. At the same time, the operation of the own functional component piece 10 is stopped.
[0010]
Further, the operation timing of the functional component piece 10 is regulated by controlling the applied driving voltage Vcc or the clock signal 24 on / off.
[0011]
【The invention's effect】
As described above, the present invention separates the electronic circuit into functional pieces 10 that can operate at the same time, and further regulates the operation timing of each functional component piece 10, thereby effectively saving power. Furthermore, by applying the electronic circuit block 11 to the SIO chip and regulating the operation timing of the functional component piece 10 by turning on and off the drive voltage Vcc and the clock signal 24, even if the electronic circuit block 11 has an interrupt, it can save power. ICs can be easily formed while effectively implementing the structure.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an electronic circuit block according to the present invention will be described based on an example in which an SIO block 16 is configured by implementing an SIO chip such as RS232C or 422. However, such as a controller for a LAN or a touch panel, or a CPU having no pipeline processing function, it is composed of a plurality of circuit components and has a portion that operates in a chain without operating in parallel. The same can be applied to an electronic circuit.
[0013]
The SIO block 16 according to the present invention is configured as a single chip by, for example, a custom LSI. The SIO block 16 is connected to the CPU 18 as shown in FIG. The CPU 18 can perform necessary data processing as read data 66 by sending out or receiving data 22 received from outside.
[0014]
Here, the SIO block 16 shows a basic concept in FIG. 1 and, as specifically exemplified by being surrounded by a dashed line in FIG. 3, a plurality of circuit components constituting an electronic circuit are provided for each function and operation unit. The functional component pieces 10 are classified and electrically divided into a plurality of functional component pieces 10 for designing, and the operation time of each functional component piece 10 is regulated.
[0015]
In the present embodiment, the timing of application of the drive voltage Vcc supplied to the SIO block 16 is regulated using the switching element 40 while the clock signal 24 is constantly supplied, so that the functional component piece 10 It is configured so that the operation time can be regulated. However, substantially the same operation can be performed by regulating the application timing of the clock signal 24 using the switching element 40 while the drive voltage Vcc is constantly applied. In addition, the method of restricting the operation of the small functional component piece 10 is not limited, for example, the reset signal is continuously applied while the clock signal 24 and the drive voltage Vcc are constantly applied.
[0016]
As the functional component piece 10 in this embodiment, as specifically illustrated in FIG. 3, a control register section 26, a start signal monitoring section 28, a serial / parallel conversion section 30, a data holding section 32, It comprises a FIFO section 34, a transmission FIFO section 36, and a parallel / serial conversion section 38.
[0017]
Here, the control register section 26 is for storing a predetermined value such as a baud rate at the time of data communication, and for regulating the output timing of the interrupt signal INT to the CPU 18, and therefore must always be operated. . Therefore, by constantly applying the drive voltage Vcc, the operation timing is not restricted.
[0018]
Next, since the start signal monitoring unit 28 detects the input timing of the start signal in the received data 22, the input signal is always monitored, while the input of the start signal is detected and the input of the series of received signals is performed. When that is started, it ends its role. Therefore, the drive voltage Vcc is connected via the switching element 40a, and a normally closed switching element is used as the switching element 40a.
[0019]
Then, the detection signal 42 is output in conjunction with the reception of the start signal in the reception data 22, the switching element 40 b is turned off by the detection signal 42, and the detection signal 42 is sent to the next serial / parallel conversion unit 30. .
[0020]
The serial / parallel converter 30 extracts a data portion of the received data 22 input in a serial state in accordance with the baud rate set in the control register 26, and uses a built-in shift register 44 to output, for example, an 8-bit parallel signal. 46.
[0021]
The serial / parallel converter 30 starts operation after a start signal is input, and ends the operation when data of 8 bits has been input. Therefore, the driving voltage Vcc is applied via the normally open switching element 40c, and the switching element 40c is turned on by the detection signal 42 sent from the start signal monitoring unit 28 to start the operation. Further, the switching element 40b is turned off by the data ready signal 48 output when 8-bit data is input, and at the same time, the switching element 40a of the start signal monitoring unit 28 is turned on to input the next start signal. Wait for.
[0022]
The data holding unit 32 is composed of two D-type flip-flops 50a and 50b, and receives the parallel signal 46 and the data ready signal 48 output from the serial / parallel conversion unit 30 to the next receiving FIFO unit 34. Used to pass. Therefore, it is sufficient to operate only at the time of data transfer, but in this embodiment, the drive voltage Vcc is fixedly supplied because the circuit scale is small.
[0023]
The reception FIFO unit 34 is constituted by a first-in first-out memory, and writes 8-bit parallel data output from the serial / parallel conversion unit 30 in synchronization with the input of the data ready signal 48, thereby making it possible to store the data in units of 8 bits. Store the data. Therefore, the drive voltage Vcc is connected via the normally open switching element 40c, and the switching element 40c is turned on by the data ready signal 48 output from the serial / parallel converter 30. This on state is maintained until the empty signal 52 is output and the switching element 40c is turned off, and the reception data 22 is held inside.
[0024]
When the chip select signal CS * and the read signal RW * are input from the CPU 18, the held reception data 22 outputs the read signal RD from the determination unit 54 to the reception FIFO unit 34, and further outputs the read signal RD. The FIFO unit 34 sends out the read data 66 to the CPU 18.
[0025]
The transmission FIFO unit 36 is a first-in first-out memory that can store transmission data therein by writing parallel write data 64 output from the CPU 18 by 8 bits. It is necessary to start the operation when the write signal WR is input from the unit 54, to continue the ON state while data is held therein, and to repeat the operation to turn OFF when the held data is exhausted. .
[0026]
Therefore, in the present embodiment, the driving voltage Vcc is applied to the transmission FIFO unit 36 via the normally open switching element 40d, and the switching element 40d is turned on by the write signal RD sent from the CPU 18, and the empty signal is output. The switching element 40d is turned off by the output of 56.
[0027]
Next, the parallel-to-serial conversion unit 38 converts the 8-bit parallel data extracted from the transmission FIFO unit 36 into serial data in accordance with a predetermined baud rate, and can output the serial data as transmission data 20.
[0028]
Therefore, the parallel-to-serial converter 38 is connected to the drive voltage Vcc via the normally open switching element 40e, and the switching element 40e is inverted by the inverter 57 from the empty signal 56 output from the transmission FIFO 36. By turning it on, the operation is started when data is written to the transmission FIFO unit 36.
[0029]
Then, the parallel / serial conversion unit 38 sends a read signal RD to the transmission FIFO unit 36 and reads data into the shift register 58 byte by byte. When all the transmission data 20 is read from the transmission FIFO unit 36, the empty signal 56 is output and the data end signal 60 output when the data is completely output from the parallel / serial conversion unit 38 is output. When confirmed by the AND circuit 62, the switching element 40e is turned off, and the state returns to the standby state for data transmission / reception.
[0030]
In addition, as described above, instead of or in addition to the method of sequentially activating the next-stage functional component pieces 10 by the signals output from the preceding functional component pieces 10, the control means that is always in the active state is used. Alternatively, a small functional component piece to be activated by a command from the control means can be selected.
[0031]
Which part in the electronic circuit is configured as the functional component piece can be arbitrarily set in accordance with the circuit to be applied. However, for example, in the case of the receiving portion in the above-described SIO block, it is preferable that the small active component pieces are always set as small as possible, while the other functional component pieces are configured such that the OFF probability is as large as possible. .
[Brief description of the drawings]
FIG. 1 is an explanatory diagram schematically showing a basic configuration of the present invention.
FIG. 2 is an example in which the present invention is applied to an SIO chip, and is a block diagram showing a connection state with a CPU.
FIG. 3 is a block diagram illustrating an example of a specific configuration of an SIO block.
[Explanation of symbols]
Reference Signs List 10 functional component small piece 12 drive signal 14 switching means 16 SIO block 18 CPU
Reference Signs List 20 transmission data 22 reception data 24 clock signal 26 control register unit 28 start signal monitoring unit 30 serial / parallel conversion unit 32 data holding unit 34 reception FIFO unit 36 transmission FIFO unit 38 parallel / serial conversion unit 40 switching element 42 detection signal 44 shift register 46 parallel signal 48 data ready signal 50 flip-flop 52 empty signal 54 discriminator 56 empty signal 57 inverter 58 shift register 60 data end signal 62 AND circuit 64 write data 66 read data

Claims (3)

A plurality of circuit components constituting an SIO circuit are classified according to their functions and operation units and separated into three or more functional component pieces , and the operation timing can be individually controlled for each of the separated functional component pieces. Electronic circuit block,
By connecting the input / output terminals of the functional component pieces in series in the order of data processing, the functional component pieces to be subjected to data processing are arranged so as to be sequentially changeable in response to input of a data signal to be processed. As well as
Only the minimum functional component pieces required for data processing of the input data signal are operated, and the other functional component pieces are stopped,
The functional component piece that has completed the data processing starts the operation of the functional component piece to be subjected to the next data processing by the control signal output in response to the end of the data processing,
An electronic circuit block , wherein the control signal is used to stop the operation of the functional component piece that has completed the data processing in response to the transfer of the data signal between the functional component pieces . The electronic circuit block according to claim 1, wherein the operation timing of each of the functional component pieces is regulated by on / off controlling the applied drive voltage . 2. The electronic circuit block according to claim 1, wherein the operation timing of each of the functional component pieces is regulated by controlling on / off of a clock signal applied thereto .

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