JP3548970B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a technology effective when applied to a semiconductor integrated circuit device, and further to a semiconductor integrated circuit device incorporating a tri-state output buffer. For example, the present invention relates to a CMOS or Bi operated by a low-voltage power supply of 3V system. The present invention relates to a technology effective for use in a semiconductor integrated circuit device of a CMOS process.
[0002]
[Prior art]
In the field of semiconductor integrated circuit devices for logic, 3V-based semiconductor integrated circuit devices that operate at a + 3.3V power supply voltage lower than a standard + 5V power supply voltage have been used in order to achieve higher integration density, higher speed, and lower power consumption. Are provided.
[0003]
In order to use this 3V semiconductor integrated circuit device connected to a bus line of a standard 5V system, a tri-state output buffer capable of operating normally even when a system signal having a 5V amplitude is reversely applied is incorporated. (See, for example, "Nikkei Micro Devices," published by Nikkei BP, October 1992, pages 83-88.)
[0004]
For example, the CMOS type tri-state output buffer shown in FIG. 7 operates at a power supply voltage of 3V, and the p-channel MOS transistor P1 is turned on and the n-channel MOS transistor N1 is turned off in accordance with the logic states of the input signal and the enable signal. (High level) output state, an L (low level) output state in which P1 is off and N1 is on, and a high impedance output state in which both P1 and N1 are off.
[0005]
However, in the tri-state output buffer shown in the figure, when the output is in a high impedance state and a 5 V amplitude system signal is reversely applied to the output via the bus line, the drain and the well (back gate) of P1 are output. The current flows from the output to the power supply potential Vcc (+3.3 V) through the forward direction of the parasitic diode DP structurally formed during the step 11). Further, when the reverse applied voltage to the output becomes equal to or higher than the gate threshold voltage of P1 with respect to Vcc (+3.3 V), P1 itself is turned on and the output through this P1 causes Vcc (+3.3 V). ) Will flow current.
[0006]
Therefore, the 3V semiconductor integrated circuit device having the tristate output buffer as shown in FIG. 7 cannot be used for exchanging signals with the 5V system.
[0007]
Therefore, a semiconductor integrated circuit device having a tri-state output buffer as shown in FIG. 8 or 9 has been developed.
[0008]
In the tri-state output buffer shown in FIG. 8, the output stage 1 is formed of a CMOS circuit, and a p-type gate whose output is connected between the well 11 of the power supply side p-channel MOS transistor P1 of the output stage 1 and the power supply potential Vcc. By interposing the channel MOS transistor P3, the well 11 of P1 is separated from Vcc and floated when the output is brought into a high impedance state. This prevents current from flowing from the output to Vcc through the parasitic diode DP structurally formed between the drain of P1 and the well 11 when the output is in the high impedance state.
[0009]
Further, an n-channel MOS transistor N2 whose gate is connected to Vcc and a p-channel MOS transistor P2 whose gate is connected to the output are connected in parallel between the gate (n3) of P1 and the input circuit 2 (n4). When the output is brought into the high impedance state, the gate (n3) of P1 and the input circuit 2 (n4) are cut off.
[0010]
In addition, by connecting a p-channel MOS transistor P4 having a gate connected to Vcc between the drain (output) of P1 and the gate, the reverse voltage applied to the output is reduced by a threshold value of P1 with respect to Vcc. Even if the voltage rises above, by conducting P4 first to bypass the voltage between the drain and gate of P1, voltage clamping is performed so that the voltage between the drain and gate of P1 does not exceed the threshold value. As a result, the off state of P1 is maintained, and the flow of current from the output to Vcc is prevented.
[0011]
As described above, in the tri-state output buffer shown in FIG. 8, when the output is in the high impedance state, any path of the parasitic diode DP and the power supply side p-channel MOS transistor P1 changes from the output to the power supply potential Vcc. The current is prevented from flowing.
[0012]
In the tri-state output buffer shown in FIG. 9, an output stage 1 is constituted by Schottky type npn bipolar transistors Q1 and Q2 and a p-channel MOS transistor P1 for assisting an output pull-up drive (Japanese Patent Application Laid-Open No. H10-163873). No. 5-259883).
[0013]
In this tri-state output buffer, a current flows from the output to the power supply potential Vcc when the output is in a high impedance state by interposing a Schottky diode D1 between the well 11 of the p-channel MOS transistor P1 and the power supply potential Vcc. I try to prevent it from flowing.
[0014]
At the same time, a Schottky diode D2 is interposed in series between the power supply potential Vcc and the preceding CMOS circuit 12 driving the gate of the p-channel MOS transistor P1 of the output stage 1 to H or L, so that the power supply from the gate of P1 The current path to the potential Vcc is cut off, and in addition, the gate of P1 and the output are connected by p-channel MOS transistors P2 and P3. When the output is in a high impedance state, a system signal is applied to the output. Is applied, the voltage bypass formed by P2 and P3 causes a voltage clamp such that the drain-gate voltage of P1 does not exceed the threshold value. As a result, even when the reverse voltage applied to the output rises above the threshold value of P1 with respect to Vcc, the off state of P1 is maintained to prevent the current from flowing from the output to Vcc. is there.
[0015]
[Problems to be solved by the invention]
However, the present inventors have clarified that the above-described technique has the following problems.
[0016]
That is, in the tri-state output buffer shown in FIG. 8, when the output is driven from H to L in the enable state where the output becomes H or L according to the input signal, the gate (n3 ) And the input circuit 2 (n4) cannot turn on the p-channel MOS transistor P2 until the output goes low. Therefore, a delay occurs in the rise of the gate voltage of P1, and a timing occurs in which P1 and N1 are simultaneously turned on. As a result, there arises a problem that a leak current flowing through P1 and N1 increases and power consumption increases.
[0017]
In addition, when the output is in a high impedance state, the wells 11 of the p-channel MOS transistors P1 to P4 are in a floating state, and the potential thereof is not determined. Was.
[0018]
Further, since the gates of the MOS transistors P2 and P3 are directly connected to the output, there is a high danger that the gates will be electrostatically damaged by an external surge or the like. Was required.
[0019]
In the tristate output buffer shown in FIG. 9, the gate of P1 reliably turns off P1 due to the forward voltage drop of Schottky diode D2 interposed in series between pre-stage CMOS circuit 12 and power supply potential Vcc. In this case, a sufficient H level cannot be given, thereby increasing the leak current flowing through P1 and Q1 and causing an increase in power consumption.
[0020]
Also, the wells 11 of the p-channel MOS transistors P1 to P3 are pulled up to the power supply potential Vcc by the Schottky diode D1, so that the floating state when the output is in the high impedance state is temporarily avoided. Alternatively, there is no way to return the potential of the well 11 when returning to the enable state of driving to L. To the well 11 when the output is in the high impedance state, a system signal voltage (5 V amplitude) reversely applied from the bus line to the output is applied via the parasitic diode DP between the drain and the well of the p-channel MOS transistor. The potential (+5 V) of the well 11 due to this applied voltage remains even after the output is returned to the enable state because there is no escape because the diodes DP and D1 stand in the opposite directions. Therefore, when the gate (n3) of P1 is set to L in order to set the output to H, a relatively high potential difference (5 V) occurs between the well 11 of P1 and the gate (n3). In addition, the potential difference (5 V) causes a danger such as element destruction.
[0021]
An object of the present invention is to provide a semiconductor integrated circuit device incorporating a tri-state output buffer, which can safely operate even when connected to a bus line of a system having a high power supply voltage without increasing through leakage current. To provide the technology of
[0022]
The above and other objects and features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0023]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0024]
That is, a diode for cutting off the current from the well of the p-channel MOS transistor serving as the pull-up drive side of the output stage toward the power supply potential, and the p-channel MOS transistor when a voltage exceeding the power supply potential is reversely applied to the output. A voltage bypass circuit for controlling the voltage between the drain and the gate of the p-channel MOS transistor so as not to exceed a threshold value, and an enable signal interposed between the gate of the p-channel MOS transistor and the input circuit and directly enabling an output. That is, a switch circuit that is turned on is provided.
[0025]
[Action]
According to the above-described means, when a voltage exceeding the power supply potential is reversely applied to the output in the high impedance state, the current flows into the power supply potential via the p-channel MOS transistor forming the pull-up drive side of the output stage. Can be prevented, and the p-channel MOS transistor in the enabled state can be turned on / off quickly and reliably.
[0026]
Thereby, in the semiconductor integrated circuit device in which the tri-state output buffer is incorporated, it is possible to safely operate the semiconductor integrated circuit device even when connected to a bus line of a system having a high power supply voltage without increasing a through leakage current. Is achieved.
[0027]
【Example】
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
In the drawings, the same reference numerals indicate the same or corresponding parts.
[0028]
FIG. 1 shows an embodiment of a main part of a semiconductor integrated circuit device to which the technology of the present invention is applied, wherein 1 is a CMOS output stage, 11 is a well, 2 is an input circuit, and P1 to P5. Is a p-channel MOS transistor, N1 to N3 are n-channel MOS transistors, 11 is a well (back gate) of p-channel MOS transistors P1 to P5, and DP is a parasitic formed structurally between the drain and the well 11 of the p-channel MOS transistor. A diode, D1 is a Schottky diode, Vcc is a 3V system power supply potential (+ 3.3V), G1 is a NAND gate, and G2 is an OR gate having an undefined logic input.
[0029]
Reference numeral 13 denotes a voltage bypass circuit formed by a p-channel MOS transistor P3, 14 denotes a switch circuit formed by an n-channel MOS transistor N2 and a p-channel MOS transistor P2, and 15 denotes an n-channel MOS transistor N3 and a p-channel MOS transistor P5. Is a control circuit formed by
[0030]
In the figure, the main part of the output stage 1 is composed of a p-channel MOS transistor P1 that pulls up the output from the power supply potential Vcc side and an n-channel MOS transistor N1 that pulls down the output from the reference potential (0V) side. Have been.
[0031]
The input circuit 2 includes gates G1 and G2, and generates a logic signal for driving the gates of the MOS transistors P1 and N1 of the output stage 1 to H or L, respectively, according to the input signal and the enable signal. That is, in the enable state set by setting the enable signal to H, when the input signal is L, the H signal is applied to both the gates of P1 and N2 to make the output L, and when the input signal is H, An L signal is applied to both gates of P1 and N2 to make the output H. Also. In the disable state in which the enable signal is set to L, while applying H to the gate of P1 and applying L to the gate of N1, both P1 and N1 are turned off, thereby setting the output to a high impedance state. I do.
[0032]
The pull-up drive side p-channel MOS transistor P1 of the output stage 1 has its well 11 connected to the same potential as the other p-channel MOS transistors P2 to P5, and has the power supply potential Vcc via the Schottky diode D1. It is connected. That is, the Schottky diode D1 is interposed between the well 11 of P1 and the power supply potential Vcc, and pulls up the well 11 from the power supply potential Vcc side, and when a voltage exceeding the power supply potential Vcc is reversely applied to the output, , And prevents a current from flowing from the output to power supply potential Vcc.
[0033]
At the same time, a p-channel MOS transistor P3 is connected between the drain and the gate of the pull-up driving side p-channel MOS transistor P1 of the output stage 1. When a constant potential Vg is given to the gate and the reverse applied voltage to the output becomes higher than the power supply potential Vcc, the P3 is turned on before the P1 to perform the voltage bypass, thereby performing the voltage bypass. A kind of voltage clamp control is performed so that the drain-gate voltage of P1 does not exceed the gate threshold voltage of P1. That is, P3 forms a voltage bypass circuit that controls the voltage between the drain and gate of P1 so as not to exceed the threshold value when a voltage exceeding the power supply potential Vcc is reversely applied to the output. As a result, even if a voltage significantly exceeding Vcc is reversely applied to the output, it is possible to prevent the current from flowing through P1.
[0034]
The constant potential Vg is set higher than a voltage (Vcc-Vth (p)) obtained by subtracting the gate threshold Vth (p) of the p-channel MO transistor from the power supply potential Vcc (+3.3 V). It is also given to each gate of P5. The power supply potential Vcc (+3.3 V) may be used as it is for the constant potential Vg.
[0035]
The source of the p-channel MOS transistor P4 is connected to the well 11, the drain is connected to the output, the gate is connected to the constant potential Vg, and the p-channel MOS transistor P4 is turned on when the potential of the well 11 becomes equal to or higher than Vg + Vth (p). Has become. As a result, the potential of the well 11 is clamp-controlled so as not to exceed Vg + Vth (p), and the risk of element destruction due to the high potential of the well 11 is avoided.
[0036]
The n-channel MOS transistor N2 and the p-channel MOS transistor P2 form a kind of switch circuit 14 interposed between the gate (n3) of the pull-down drive side p-channel MOS transistor P1 of the output stage 1 and the input circuit 2 (n4), respectively. However, when the switch circuit 14 is in the disable state, the switch circuit 14 operates so as to cut off the gate (n3) of P1 from the input circuit 2 (n4) so as not to apply a reverse voltage applied to the output to the input circuit 2 side. I do.
[0037]
The n-channel MOS transistor N3 and the p-channel MOS transistor P5 form a control circuit 15 for directly turning on the switch circuit 14 by an enable signal. P5 acts as a drain load of N3, and N3 is turned on in an enable state set by the enable signal becoming H, and the gate of P2 falls to L.
[0038]
Thereby, P2 is in a pass state in which the H signal from the input circuit 2 is transmitted to the gate of P1 when in the enable state. Accordingly, the p-channel MOS transistor P1 on the pull-up drive side can immediately switch from the on state to the off state in response to the H signal from the input circuit 2 without waiting for the output to go low (see FIG. 8). . As a result, a through leakage current caused by turning on P1 and N1 simultaneously is avoided.
[0039]
As described above, when a voltage exceeding the power supply potential Vcc is reversely applied to the output in the high impedance state, the power supply potential Vcc via the p-channel MOS transistor P1 forming the pull-up drive side of the output stage 1 is applied. Of the p-channel MOS transistor P1 in the enabled state can be quickly and reliably performed.
[0040]
Further, since the well 11 of P1 is connected to the power supply potential Vcc or the output via the diode D1 or the MOS transistor P4, the well 11 is prevented from being in a floating state with a risk of latch-up.
[0041]
Further, since none of the gates of the MOS transistors P1 to P5 and N1 to N3 are directly connected to the output, there is no danger of electrostatic breakdown due to an external surge or the like, and thus no special protective measures are required. is there.
[0042]
In this way, a tri-state output buffer that operates safely without increasing through-leakage current and without risk of latch-up or electrostatic breakdown, even when connected to the bus line of a system with a high supply voltage. can get.
[0043]
FIG. 2 is a waveform chart showing the voltage at each part (output and n1 to n6) of the above-described tristate output buffer for each state. In this figure, Vcc is the power supply voltage (+3.3 V), Vout is the H output voltage of the tri-state output buffer (about +3.3 V), Vx is the voltage applied reversely from the 5 V system to the output, and Vy is the 3 V system. Vth (p) is a threshold voltage of a p-channel MOS transistor, and Vf (D1) is a forward voltage of the Schottky diode D1. Here, it should be noted that in the above-described tri-state output buffer, even when the power supply is cut off and the power supply potential Vcc becomes 0 V, the same operation as in the case where the output is in the high-impedance state is performed. This is to prevent the current from flowing due to the applied voltage. As a result, it is also possible to use the power supply shut off to reduce the power consumption of the entire system.
[0044]
FIG. 3 shows a second embodiment of the present invention. Differences from the embodiment shown in FIG. 1 will be described. In the second embodiment, p-channel MOS transistors P3, P4, The constant potential Vg applied to the gate of P5 is generated by the Schottky diode D31 and the resistor R31. Thus, the constant potential Vg is set to a value lower than the power supply potential Vcc (+3.3 V) by the forward voltage of the Schottky diode D31.
[0045]
FIG. 4 shows a third embodiment of the present invention. In this third embodiment, a constant potential Vg applied to the gates of p-channel MOS transistors P3, P4 and P5 is applied to a p-channel MOS transistor. It is generated by P41 and resistor R41.
[0046]
FIG. 5 shows a fourth embodiment of the present invention. In the fourth embodiment, an output is provided by an inverter 51 and an n-channel MOS transistor N51 whose well is connected to a reference potential (0 V). To assist the pull-up drive. N5 assists the pull-up driving operation in the output stage 1 by transmitting the signal from the input circuit 2 to the output by the source follower. In this case, since the parasitic diode structurally formed in the n-channel MOS transistor N51 has the opposite direction to the output and the power supply potential Vcc, there is no fear that the reverse applied voltage flows to the output.
[0047]
FIG. 6 shows a fourth embodiment of the present invention. In the fifth embodiment, an inverter 61 and an npn-type Schottky transistor Q61 assist output pull-up driving. . The Q61 assists the pull-up driving operation in the output stage 1 by transmitting the signal from the input circuit 2 to the output by the emitter follower. Also in this case, the diode formed structurally in the npn-type Schottky transistor Q61 has the opposite direction to both the output and the power supply potential Vcc. Absent.
[0048]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and it can be said that various modifications can be made without departing from the gist of the invention. Not even. For example, n-channel MOS transistor N1 serving as the bull-down drive side of output stage 1 may be a bipolar transistor.
[0049]
In the above description, the case where the invention made by the present inventor is applied to a semiconductor integrated circuit device for logic, which is a field of use as a background, has been mainly described. However, the present invention is not limited to this case. The present invention can also be applied to a digital mixed type semiconductor integrated circuit device.
[0050]
【The invention's effect】
The effects of typical inventions disclosed in the present application will be briefly described as follows.
[0051]
That is, in a semiconductor integrated circuit device in which a tri-state output buffer is incorporated, it is possible to operate safely even when connected to a bus line of a system having a high power supply voltage without increasing through leakage current. Is obtained.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a main part of a first embodiment of a semiconductor integrated circuit device to which the technology of the present invention is applied. FIG. 2 is a waveform chart showing the voltage in each part of the circuit shown in FIG. FIG. 3 is a circuit diagram showing a main part of a second embodiment of the present invention. FIG. 4 is a circuit diagram showing a main part of a third embodiment of the present invention. FIG. 5 is a circuit diagram showing a main part of a fourth embodiment of the present invention. FIG. 6 is a circuit diagram showing a main part of a fifth embodiment of the present invention. FIG. 7 is a circuit diagram showing a first configuration example of a conventional tri-state output buffer. FIG. 9 is a circuit diagram showing a second configuration example of the tri-state output buffer of FIG. 9; FIG. 9 is a circuit diagram showing a third configuration example of the conventional tri-state output buffer;
1 CMOS type output stage 11 well 2 input circuits P1 to P5 p channel MOS transistors N1 to N3 n channel MOS transistor 11 well (back gate)
DP Parasitic diode D1 Schottky diode Vcc 3V system power supply potential (+ 3.3V)
G1 NAND gate G2 OR gate 13 Voltage bypass circuit 14 Switch circuit 15 Control circuit 41, 51 Inverter N41 N-channel MOS transistor Q51 npn bipolar transistor

Claims (6)

A diode for cutting off the current from the well of the p-channel MOS transistor forming the pull-up drive side of the output stage toward the power supply potential, and a drain of the p-channel MOS transistor when a voltage exceeding the power supply potential is reversely applied to the output. A voltage bypass circuit for controlling a voltage between gates so as not to exceed a threshold value, and a direct on-setting by an enable signal interposed between the gate of the p-channel MOS transistor and the input circuit and for enabling an output; And a tri-state output buffer having a switch circuit to be implemented. The voltage bypass circuit is connected between the drain and the gate of the p-channel MOS transistor which forms the pull-up drive side of the output stage, and is turned on when a constant voltage is applied to the gate and the gate voltage to the drain becomes higher than a certain value. 2. The semiconductor integrated circuit device according to claim 1, wherein said semiconductor integrated circuit device is formed by a p-channel MOS transistor. The switch circuit is formed by an n-channel MOS transistor and a p-channel MOS transistor which are interposed in parallel with each other between a gate of the p-channel MOS transistor forming the pull-up drive side of the output stage and the input circuit. The semiconductor integrated circuit device according to claim 1. 4. The semiconductor integrated circuit according to claim 1, wherein the switch circuit includes a MOS transistor that is turned on by an enable signal to transmit a signal from the input circuit to the output stage. Circuit device. A MOS transistor which is turned on when the potential of the well of the first p-channel MOS transistor forming the pull-up drive side of the output stage becomes equal to or higher than a fixed potential so as to control the potential of the well so as not to exceed the fixed potential. The semiconductor integrated circuit device according to any one of claims 1 to 4, further comprising: 6. The semiconductor according to claim 1, further comprising an n-channel MOS transistor that assists a pull-up driving operation in an output stage by transmitting a signal from an input circuit to an output by a source follower. Integrated circuit device.

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