JP3548642B2 - Image information generating apparatus and method, image information processing apparatus and method, and recording medium - Google Patents

Description

画面サイズすなわちディスプレイ画面上のピクセル数は可変で、図３のように、水平方向、垂直方向それぞれ独立に表示開始位置（座標（ＤＴＸ，ＤＴＹ））、表示終了位置（座標（ＤＢＸ，ＤＢＹ））を指定することができる。
【００６５】
また、各座標に指定可能な値と画面モードとの関係は、以下のようになっている。なお、座標値のＤＴＸ，ＤＢＸは４の倍数になるように設定する必要がある。したがって、最小画面サイズは、横４ピクセル、縦２ピクセル（ノンインターレス時）又は４ピクセル（インターレス時）になる。
【００６６】
〔Ｘ座標の指定可能範囲〕
〔モード〕 〔ＤＴＸ〕 〔ＤＢＸ〕
０，４ ０〜２７６ ４〜２８０
１，５ ０〜３４８ ４〜３５２
２，６ ０〜５５６ ４〜５６０
３，７ ０〜７００ ４〜７０４
８，９ ０〜３９６ ４〜４００
〔Ｙ座標の指定可能範囲〕
〔モード〕 〔ＤＴＹ〕 〔ＤＢＹ〕
０〜３，８ ０〜２４１ ２〜２４３
４〜７，９ ０〜４８０ ４〜４８４
次に、ＧＰＵ６２は、表示色数に関するモードとして、１６ビットダイレクトモード（３２７６８色）と、２４ビットダイレクトモード（フルカラー）の２つをサポートしている。上記１６ビットダイレクトモード（以下１６ビットモードと呼ぶ）は３２７６８色表示モードである。この１６ビットモードでは、２４ビットダイレクトモード（以下２４ビットモードと呼ぶ）に較べ表示色数に限りはあるが、描画時のＧＰＵ６２内部での色計算は２４ビットで行われ、また、諧調を疑似的に増やすいわゆるディザ機能も搭載しているので、疑似フルカラー（２４ビットカラー）表示が可能となっている。また、上記２４ビットモードは、１６７７７２１６色（フルカラー）表示のモードである。但し、フレームバッファ６３内に転送されたイメージデータの表示（ビットマップ表示）のみが可能で、ＧＰＵ６２の描画機能を実行することはできない。ここで、１ピクセルのビット長は２４ビットとなるが、フレームバッファ６３上での座標や表示位置の値は１６ビットを基準として指定する必要がある。すなわち、６４０×４８０の２４ビット画像データは、フレームバッファ６３中では９６０×４８０として扱われる。また、前記座標値ＤＢＸは８の倍数になるように設定する必要があり、したがって、この２４ビットモードでの最小画面サイズは横８×縦２ピクセルになる。
【００６７】
また、ＧＰＵ６２には次のような描画機能が搭載されている。
【００６８】
先ず、１×１ドット〜２５６×２５６ドットのポリゴン又はスプライトに対して、４ビットＣＬＵＴ（４ビットモード、１６色／ポリゴン、スプライト）や８ビットＣＬＵＴ（８ビットモード、２５６色／ポリゴン、スプライト），１６ビットＣＬＵＴ（１６ビットモード、３２７６８色／ポリゴン、スプライト）等の描画が可能なポリゴン又はスプライト描画機能と、
ポリゴンやスプライト（三角形や四角形等の多角形）の各頂点の画面上の座標を指定して描画を行うと共に、ポリゴンやスプライト内部を同一色で塗りつぶすフラットシェーディング、各頂点に異なる色を指定して内部をグラデーションするグーローシェーディング、ポリゴンやスプライト表面に２次元のイメージデータ（テクスチャパターン、特にスプライトに対するものをスプライトパターンと呼ぶ）を用意して張り付けるテクスチャマッピング等を行うポリゴン描画機能と、
グラデーションが可能な直線描画機能と、
ＣＰＵ５１からフレームバッファ６３への転送、フレームバッファ６３からＣＰＵ５１への転送、フレームバッファ６３からフレームバッファ６３への転送等のイメージ転送機能と、
その他の機能として、各ピクセルの平均をとって半透明化する機能（各ピクセルのピクセルデータを所定比率αで混合することからαブレンディング機能と呼ばれる）、色の境界にノイズを乗せてぼかすディザ機能、描画エリアを越えた部分を表示しない描画クリッピング機能、描画エリアに応じて描画原点を動かすオフセット指定機能等がある。
【００６９】
また、描画を行う座標系は符号付きの１１ビットを単位としており、Ｘ，Ｙそれぞれに−１０２４〜＋１０２３の値をとる。また、図４に示すように、本構成例でのフレームバッファ６３のサイズは１０２４×５１２となっているので、はみ出した部分は折り返すようになっている。描画座標の原点は、座標値のオフセット値を任意に設定する機能により、フレームバッファ６３内で自由に変更することができる。また、描画は、描画クリッピング機能により、フレームバッファ６３内の任意の矩形領域に対してのみ行われる。
【００７０】
さらに、ＧＰＵ６２は、最大２５６×２５６ドットのテクスチャをサポートしており、縦，横それぞれの値を自由に設定することができる。
【００７１】
上記ポリゴン又はスプライトに張りつけるイメージデータ（テクスチャパターン又はスプライトパターン）は、図５に示すように、フレームバッファ６３の非表示領域に配置する。テクスチャパターン又はスプライトパターンは、描画コマンド実行に先立ってフレームバッファ６３に転送される。テクスチャパターン又はスプライトパターンは、２５６×２５６ピクセルを１ページとして、フレームバッファ６３上にメモリの許す限り何枚でも置くことができ、この２５６×２５６の領域をテクスチャページと呼んでいる。１枚のテクスチャページの場所は、描画コマンドのＴＳＢと呼ぶテクスチャページの位置（アドレス）指定のためのパラメータに、ページ番号を指定することで決定される。
【００７２】
テクスチャパターン又はスプライトパターンには、４ビットＣＬＵＴ（４ビットモード）、８ビットＣＬＵＴ（８ビットモード）、１６ビットＣＬＵＴ（１６ビットモード）の３種類の色モードがある。４ビットＣＬＵＴ及び８ビットＣＬＵＴの色モードでは、ＣＬＵＴを使用する。
【００７３】
このＣＬＵＴとは、図６に示すように、最終的に表示される色を表す３原色のＲ，Ｇ，Ｂ値が１６乃至２５６個、フレームバッファ６３上に並んだものである。各Ｒ，Ｇ，Ｂ値はフレームバッファ６３上の左から順に番号付けされており、テクスチャパターン又はスプライトパターンはこの番号により各ピクセルの色を表す。また、ＣＬＵＴはポリゴン又はスプライト単位で選択でき、全てのポリゴン又はスプライトに対して独立したＣＬＵＴを持つことも可能である。また、図６において、１個のエントリは１６ビットモードの１ピクセルと同じ構造となっており、したがって、１セットのＣＬＵＴは１×１６（４ビットモード時）、１×２５５（８ビットモード時）のイメージデータと等しくなる。フレームバッファ６３内でのＣＬＵＴの格納位置は、描画コマンド内のＣＢＡと呼ぶＣＬＵＴの位置（アドレス）指定のためのパラメータに、使用するＣＬＵＴの左端の座標を指定することで決定する。
【００７４】
さらに、ポリゴン又はスプライト描画の概念を模式的に示すと図７のように表すことができる。なお、図７の例ではスプライトを例に挙げている。また図７中の描画コマンドのＵ，Ｖはテクスチャページのどの位置かを横（Ｕ），縦（Ｖ）で指定するパラメータであり、Ｘ，Ｙは描画エリアの位置を指定するためのパラメータである。
【００７５】
また、ＧＰＵ６２は、動画表示の方式として、フレームダブルバッファリングという手法を用いるようにしている。このフレームダブルバッファリングとは、図８に示すように、フレームバッファ６３上に２つの矩形領域を用意し、一方のエリアに描画をしている間はもう片側を表示し、描画が終了したら２つのエリアをお互いに交換するものである。これにより、書き換えの様子が表示されるのを回避することができることになる。なお、バッファの切り換え操作は、垂直帰線期間内に行う。また、ＧＰＵ６２では、描画の対象となる矩形領域と座標系の原点を自由に設定できるので、この２つを移動させることにより、複数のバッファを実現することも可能である。
【００７６】
次に、本構成例の画像処理システムにおけるテクスチャマッピング及びグーローシェーディング時のＣＰＵ５１が出力する命令形式（インストラクションセット）について説明する。
【００７７】
先ず、描画命令形式について説明する。
【００７８】
命令形式（１）として、描画命令をＣＰＵ５１が直接指定するために、図９に示すようなパケット構成を用いる。なお、この図９において、Ｒ，Ｇ，Ｂは多角形の全ての頂点で共有する輝度値を、Ｘｎ，Ｙｎは頂点ｎの描画空間上の２次元座標を示す。この命令形式（１）に対して、例えば、（Ｘ０，Ｙ０）−（Ｘ１，Ｙ１）−（Ｘ２，Ｙ２）で囲まれる領域を輝度値（Ｒ，Ｇ，Ｂ）で塗りつぶす命令の場合には、図１０に示すようになり、以降の描画の座標オフセットを（０ＦＸ，０ＦＹ）に変更する。
【００７９】
次に、命令形式（２）として、図１１に示すように、命令形式（１）の型の描画命令に命令のワード数と次の命令へのポインタを付加したタグを設けたパケット構成を用いる。なお、この図１１中のＳＩＺＥは命令のワード長（この例では４）を、ＡＤＤＲは次の命令の先頭アドレスを示す。これによって、フレームバッファ６３上で連続した領域におかれていない複数の命令列をつなげて一度に実行できるようになる。この場合の描画命令の転送は専用のハードウエアが行い、ＣＰＵ５１は一切関与しない。また、この命令形式（２）において、例えば、（Ｘ０，Ｙ０）−（Ｘ１，Ｙ１）−（Ｘ２，Ｙ２）で囲まれる領域を輝度値（Ｒ，Ｇ，Ｂ）で塗りつぶす命令の場合には、図１２に示すようになり、以降の描画の座標オフセットを変更する。
【００８０】
次に、本発明のデータ形式について詳細に説明する。
【００８１】
ＧＰＵ６２はホスト（ＣＰＵ５１）より供給されるパケット化されたコマンド（描画命令）列を順次実行する。なお、以下の説明では下記の記号を使用する。
【００８２】

なお、Ｘｎ，Ｙｎは、コマンドでは１６ビットが割り当てられているが、実際には各々下位１１ビットまでが有効である。ＣＢＡ及びＴＳＢのビットアサインは図１３及び図１４に示す通りである。なお、図１３中ＣＬＸはＣＬＵＴのＸ軸の先頭アドレス（６ビット）で、ＣＬＹはＣＬＵＴのＹ軸の先頭アドレス（９ビット）である。また、図１４に示すＴＳＢは、ＭＯＤＥコマンド（後述する設定コマンド参照）の下位ビットと同じビットアサインである。この図１４中のＴＰＦはテクスチャパターンのピクセルの深さで、００のとき４ビットモード（ＣＬＵＴ）、０１のとき８ビットモード（ＣＬＵＴ）、１０のとき１６ビットモード（ＣＬＵＴ）である。図１４中のＡＢＲは半透明レートを示し、００のとき０．５０×Ｆ＋０．５０×Ｂ、０１のとき１．００×Ｆ＋１．００×Ｂ、１０のとき０．５０×Ｆ＋１．００×Ｂ、１１のとき０．２５×Ｆ＋１．００×Ｂとなる（なおＦは前景、Ｂは背景に対応する）。また、図１４中のＴＢＸはテクスチャパターンソース空間ｘ方向のベースアドレス（上位５ビット）で、ＴＢＹはテクスチャパターンソース空間ｙ方向のベースアドレス（上位１ビット）である。
【００８３】
次に三角形描画コマンド（コマンドコード＝１ｈ）は、図１５に示すように、コマンドコード（オプションを含む）の後に、頂点情報をコマンド引数として与える。オプションにより、引数の数、フォーマットが異なる。この図１５中のＩＩＰが０のときは１種類の輝度値（Ｒ，Ｇ，Ｂ）で三角形を描画（フラットシェーディング）し、１のときは三頂点の輝度値を線形補間して、三角形を描画（グーローシェーディング）する。ＣＮＴが０のときコマンド以降に続く３頂点で三角形を一つ描画し、１のときコマンド以降に続く４頂点で連結三角形を描画（四角形）する。ＴＭＥが０のときテクスチャマッピングオフとなり、１のときテクスチャマッピングがオンとなる。ＡＢＥが０のとき半透明処理がオフとなり、１のとき半透明処理がオンとなる。ＴＧＥはＴＭＥの時のみ有効で、０のときテクスチャパターンと輝度値とを掛け合わせて表示し、１のときテクスチャパターンのみを描画する。ここでのデータ構成は、２^３通りとなるが、その一部を図１６に示す。
【００８４】
次に直線描画コマンド（コマンドコード＝２ｈ）は、図１７に示すように、コマンドコード（オプションを含む）の後に、端点情報をコマンド引数として与える。オプションにより引数の数やフォーマットが異なる。なお図１７中のＩＩＰが０のときはピクセルを描画指定された輝度値で描画し、１のときは２頂点の輝度値を線分の長軸方向の変位で線形補間して描画する。ＣＮＴが０のときはコマンド以降に続く２端点で直線を１つ描画し、１のとき連結直線を描画する。ＡＢＥが０のとき半透明処理がオフとなり、１のとき半透明処理がオンとなる。
【００８５】
連結直線を描画するときは、最後にコマンドの終了を示す終端コード（ＴＥＲＭＩＮＡＴＩＯＮ ＣＯＤＥ）が必要となる。終端コードのフォーマットは図１８に示すようになり、そのデータ構成例を図１９に示す。なお、座標値Ｘｎ，Ｙｎは下位１１ビットのみが有効であるので、通常の使用では座標値と終端コードが衝突することはない。
【００８６】
次にスプライト描画コマンド（コマンドコード＝３ｈ）は、図２０に示すようになり、データ構成例を図２１に示す。このスプライト描画コマンドでは、コマンドコード（オプションを含む）の後に、輝度情報、矩形領域の左下端点、テクスチャソース空間の左上端点、矩形領域の幅と高さをコマンド引数として与える。オプションにより引数の数、フォーマットが異なる。また、スプライト描画コマンドは２ピクセル同時に処理をするため、Ｕｎは偶数を指定しなければならない（下位１ビットは意味を持たない）。なお、図２０中のＴＭＥが０のときはテクスチャマッピングがオフし、１のときはテクスチャマッピングがオンする。ＡＢＥが０のときは半透明処理がオフし、１のときは半透明処理がオンする。ＴＧＥ（ＴＭＥの時のみ有効）が０のときはテクスチャパターン（この場合にはスプライトパターン）に一定の輝度値を掛け合わせて描画し、１のときはテクスチャパターン（スプライトパターン）のみを描画する。ＳＩＺは矩形領域のサイズを指定し、００のときにはＨ，Ｗフィールドで指定し、０１のときは１×１、１０のときは８×８、１１のときは１６×１６のサイズ指定となる。
【００８７】
次にローカルローカル転送コマンド（コマンドコード＝４ｈ）すなわちフレームバッファ間の転送コマンドとして、例えば矩形領域転送コマンドは、図２２に示す通りであり、データ構成は図２３に示すようになる。この矩形領域転送コマンドは、コマンドコード（オプションを含む）の後に、ソース矩形領域の左上端点、ディスティネーション矩形領域の左上端点、矩形領域の幅と高さをコマンド引数として与える。なお、図中のＣＯＤＥはコマンドコード及びオプションを示し、ＳＸ，ＳＹはソース（転送元）矩形領域の左上端点の座標を、ＤＸ，ＤＹはディスティネーション（転送先）矩形領域の左上端点の座標を、Ｗは矩形領域の幅を、Ｈは矩形領域の高さを示す。
【００８８】
次に、ホストローカル転送コマンド（コマンドコード＝５ｈ）は、図２４に示す通りとなり、データ構成は図２５に示すようになる。このホストローカル転送コマンドは、ＣＰＵとフレームバッファ間の転送コマンドであり、コマンドコード（オプションを含む）で例えばディスティネーション矩形領域の左上端点、矩形領域の幅と高さ、転送データをコマンド引数として与える。なお、図中のＣＯＤＥはコマンドコード及びオプションを示し、ＤＸ，ＤＹはディスティネーション（転送先）矩形領域の左上端点の座標を、Ｗは矩形領域の幅を、Ｈは矩形領域の高さを、ＦＲＡＭ０〜ＦＲＡＭｎは転送データを示す。
【００８９】
次にローカルホスト転送コマンド（コマンドコード＝６ｈ）は、図２６に示す通りであり、このデータ構成は図２７に示すようになる。このローカルホスト転送コマンドは、フレームバッファとＣＰＵとの間の転送コマンドであり、例えばソース矩形領域の左上端点、矩形領域の幅と高さをコマンド引数として与える。なお、図中のＣＯＤＥはコマンドコード及びオプションを示し、ＳＸ，ＳＹはソース（転送元）矩形領域の左上端点の座標を、Ｗは矩形領域の幅を、Ｈは矩形領域の高さを示す。また、汎用ポートを使用するコマンド（パラメータリード）をローカルホスト転送中に行うことはできない。
【００９０】
次に、設定コマンド（コマンドコード＝７ｈ）は、図２８に示すように、各種パラメータレジスタを設定するコマンドである。これはコマンドコード（アドレスを含む）と、設定値を与える。なお、図中のＣＯＤＥはコマンドコード及びオプションを示し、ＡＤＤＲはアドレスを、ＤＡＴＡはパラメータを示す。
【００９１】
ここで、この設定コマンドのうちモード（ＭＯＤＥ）設定コマンド（アドレス＝１ｈ）は、図２９に示す構成であり、図中のＴＰＦはテクスチャパターン（スプライの場合はスプライトトパターン）のピクセルの深さを示し、００のとき４ビットモード（ＣＬＵＴ）、０１のとき８ビットモード（ＣＬＵＴ）、１０のとき１６ビットモード（ダイレクト）を示す。ＤＴＤは０のときディザリングを行わないことを示し、１のときディザリングを行うことを示す。ＤＦＥは０のときインターレース時に表示されていないフィールドのみ描画し、１のときインターレース時に両フィールドとも描画する。ＡＢＲは半透明レートを示し、００のとき０．５０×Ｆ＋０．５０×Ｂを、０１のとき１．００×Ｆ＋１．００×Ｂを、１０のとき０．５０×Ｆ＋１．００×Ｂを、１１のとき０．２５×Ｆ＋１．００×Ｂを示す（なお、Ｆは前景、Ｂは背景に対応する）。ＴＢＸはテクスチャパターンソース空間ｘ方向ベースアドレス（上位４ビット）を、ＴＢＹはテクスチャパターンソース空間ｙ方向ベースアドレス（上位１ビット）を示す。
【００９２】
また、設定コマンドのうちテクスチャパターンリピート（ＴＥＸＴＵＲＥ ＰＡＴＴＥＲＮ ＲＥＰＥＡＴ ）設定コマンド（ アドレス＝２ｈ）は、図３０に示す構成であり、図中ＴＵＭはテクスチャパターンＵ座標繰り返しマスクを、ＴＶＭはテクスチャパターンＶ座標繰り返しマスクを、ＴＵＡはテクスチャパターン繰り返しＵ上位固定アドレスを、ＴＶＡはテクスチャパターン繰り返しＶ上位固定アドレスを示す。
【００９３】
次に、設定コマンドのうちクリッピングスタート（ＣＬＩＰＰＩＮＧ ＳＴＡＲＴ）設定コマンド（アドレス＝３ｈ）とクリッピングエンド（ＣＬＩＰＰＩＮＧ ＥＮＤ）設定コマンド（アドレス＝４ｈ）は、図３１に示す構成を有する。なお、図３１の（ａ）にはクリッピングスタート設定コマンドを、図３１の（ｂ）にはクリッピングエンド設定コマンドを示す。クリッピッグはポリゴン（三角形）／直線／スプライト描画コマンドに対して有効であり、ホストローカル／ローカルローカル転送には作用しない。図中のＣＴＸはクリッピングの左上端点のＸアドレス（１０ビット）を、ＣＴＹはクリッピングの左上端点のＹアドレス（９ビット）を、ＣＢＸはクリッピングの右下端点のＸアドレス（１０ビット）を、ＣＢＹはクリッピングの右下端点のＹアドレス（９ビット）を示す。
【００９４】
次に、設定コマンドのうちオフセット（ＯＦＦＳＥＴ）設定コマンド（アドレス＝５ｈ）は図３２に示す構成をとり、図中ＯＦＸは座標オフセット値（Ｘ）（有符号１１ビット）を、ＯＦＹは座標オフセット値（Ｙ）（有符号１１ビット）を示す。
【００９５】
次に特殊コマンド（アドレス＝０ｈ）は、図３３に示す構成をとり、特殊コマンドとしては割り込み要求イネーブルコマンドと後述するＮＯＰコマンド等がある。これはコマンドとオプションで指定する。
【００９６】
上記特殊コマンドのうちＩＲＱ（ｉｎｔｅｒｒｕｐｔ ｒｅｑｕｅｓｔ） 発生コマンドは、図３４に示す構成をとり、ＩＲＱピンをアサートする。
【００９７】
また特殊コマンドのうちＮＯＰ（ｎｏ ｏｐｅｒａｔｉｏｎ）コマンドは、図３５に示す構成をとり、このときは何もしない。
【００９８】
さらに、特殊コマンドのうちキャッシュフラッシュコマンドは、図３６に示す構成をとり、テクスチャキャッシュとＣＬＵＴの内容をフラッシュする。ただし、ホストローカル転送，ローカルホスト転送を行うとテクスチャキャッシュだけは自動的にフラッシュされる（ＣＬＵＴは保存される）。
【００９９】
また、特殊コマンドのうちブロックライトコマンドは、図３７に示す構成となり、データ構成は図３８に示すようになる。このコマンドは、高速で矩形を初期化する。なお、図中のＷ，Ｈは矩形領域のサイズを示す。また、Ｒ，Ｇ，Ｂは８ビットで指定されるが、実際にメモリ上へ書き込まれる値は、上記４ビットのみである。矩形領域の開始位置（Ｘ０，Ｙ０）、サイズ（Ｈ，Ｖ）は共に３２ピクセルの整数倍で指定する。下位４ビットは意味を持たない。
【０１００】
ところで、ＧＰＵ６２は専用のローカルメモリを持ち、これは表示用のフレームバッファであると同時にテクスチャパターンやテクスチャＣＬＵＴの領域としても使用する。すなわち、このローカルメモリが図１のフレームバッファ６３である。
【０１０１】
上記フレームバッファ６３へのアドレッシングとして、ＧＰＵ６２が描画する領域はｘ方向０〜１０２３、ｙ方向０〜５１１のサイズであり、ローカルメモリ（フレームバッファ６３）の１次元アドレスとの対応は、
１次元アドレス＝Ｘ_Ａ＋Ｙ_Ａ×１０２４
である。ただし、２４ビットモードの場合は、
１次元アドレス＝（３／２）×Ｘ_Ａ＋Ｙ_Ａ×１０２４
である。
【０１０２】
なお、フレームバッファ６３のページサイズは１０２４固定なので、実際にはＸＡ がカラムアドレス、Ｙ_Ａがロウアドレスに対応する。フレームバッファ６３内にはどこでも描画可能で、また、フレームバッファ６３内の任意の領域を表示することもできる。ただし、表示できる大きさは、モードに応じて制限がある。さらに、フレームバッファ６３のアドレスＸ_Ａ，Ｙ_Ａはそれぞれ１０ビット，９ビット無符号で指定される。ただし、ポリゴンの描画で使用する座標値ｘ，ｙは、それぞれ１１ビット有符号で指定される。またさらに、描画は（ｘ，ｙ）にオフセットレジスタで指定されたオフセット（ＯＦＸ，ＯＦＹ）が加算された値をアドレスとして、フレームバッファ６３に描画される。ただし、マウントされるフレームメモリの大きさ、１０２４×５１２を越えた領域には描画されない。
【０１０３】
次に、ピクセルフォーマットについて説明する。ＧＰＵ６３は、図３９の（ａ）に示すようにＲ：Ｇ：Ｂ＝８：８：８（ビット）の２４ビットモードと、同図中（ｂ）に示すようにＲ：Ｇ：Ｂ＝５：５：５（ビット）の１６ビットモードをサポートする。ただし、２４ビットモードは表示のみで描画することはできない。なお、図中のＲは赤色成分を、Ｇは緑色成分を、Ｂは青色成分を、ＳＴＰはオーバーライトフラグを示す。モードによっては、ＳＴＰに１が指定されると、以降そのピクセル上に新たに描画が実行されてもピクセルの内容は保存される。これによって最初に描画したパターンを保持しておくことができる。
【０１０４】
次に、本構成例フォーマットによれば、ポリゴン／スプライトを描画する際に、テクスチャページにおかれたパターン（テクスチャパターン又はスプライトパターン）を使用してテクスチャマッピングを行うことができるようになる。以降の説明では（ｘ，ｙ）は描画空間の座標を、（ｕ，ｖ）はテクスチャページ空間の座標を表す。
【０１０５】
先ず、テクスチャパターンやスプライトパターンの置かれているフレームバッファ内の領域をテクスチャページ或いはテクスチャページ空間と呼ぶ。テクスチャパターンやスプライトパターンのピクセルフォーマットとしては、４，８，１６ビット／ピクセルの３種類のモードがある。４ビット，８ビットモードは疑似カラーであり、１６ビットモードはダイレクトカラーである。これらモードはポリゴン又はスプライト単位で切り換えることができる。１６ビットモード以外のテクスチャパターンやスプライトパターンは１ワード内に何個かのピクセルがパックされている。したがって、テクスチャパターンやスプライトパターンのピクセルとフレームバッファのアドレスは１対１に対応していない。そのため、フレームバッファにテクスチャパターンやスプライトパターンをロードする場合のアドレスの指定には注意が必要である。各モードの場合のピクセルフォーマットは以下の図４０に示す通りである。
【０１０６】
図４０の（ａ），（ｂ）に示す４ビット／ピクセル，８ビット／ピクセルの場合、ピクセル値は実際の輝度値ではなく、ＣＬＵＴへのインデックスとなる。これから、ピクセルはＣＬＵＴを用いて、図４１のように１６ビットのカラーフォーマットに変換される。なお、図中Ｒは赤色成分を、Ｇは緑色成分を、Ｂは青色成分を、ＳＴＰは半透明フラグを示す。
【０１０７】
また、１６ビット／ピクセルの場合はＣＬＵＴは用いられず、直接、輝度値として使用される。このフォーマットは、図４１と同様の図４２の通りである。なお、図中Ｒは赤色成分を、Ｇは緑色成分を、Ｂは青色成分を、図中ＳＴＰは半透明フラグを示す。ＳＴＰに１が指定されたピクセルは半透明で描画され、半透明レートはポリゴン又はスプライト毎に独立に設定できる。
【０１０８】
さらに、４ビットモード、８ビットモードの場合は、テクスチャＣＬＵＴを用いてテクスチャの色（輝度）を決定することができるようになっている。テクスチャＣＬＵＴはフレームバッファに幾つも持つことができるが、一回の描画コマンドで使用できるＣＬＵＴは１種類に限られる。ＣＬＵＴの選択はフレームバッファ上の先頭アドレスを指定することで選択できる。先頭アドレスの指定はコマンド引数のＣＢＡで行う。
【０１０９】
ＧＰＵ６２は内部にテクスチャＣＬＵＴキャッシュを持っており、ポリゴン描画に先立ち、キャッシュ内に必要なＣＬＵＴがなければ、新しくＣＬＵＴをロードする。このため、同じＣＬＵＴを繰り返し使用する場合の描画はＣＬＵＴロードの分だけ高速になる。
【０１１０】
次に、上述したような本構成例のシステム及びフォーマットが適用される画像情報生成及び画像情報処理の流れを、図４３にて説明する。
【０１１１】
この図４３において、ステップＳ１０では複数のポリゴンからなる３次元画像データをＣＤ−ＲＯＭのディスクから読み出してメインメモリ５３に記憶し、ステップＳ１１では各ポリゴン毎に指定される特性データとして色情報テーブル、テクスチャパターン情報、半透明率指定データをフレームバッファ６３に記憶する。
【０１１２】
ステップＳ１２では、前記グラフィックシステム６０にて透視変換等の座標変換処理を行って上記３次元画像データから２次元画像情報を生成し、次のステップＳ１３では当該２次元画像情報と各ポリゴンの特性を指定するための情報とを合成してポリゴン毎にパケット化された描画命令を生成する。
【０１１３】
ステップＳ１４では、当該生成された描画命令により指定された特性データに基づき２次元画像をフレームバッファ６３に描画する。
【０１１４】
次のステップＳ１５では当該フレームバッファ６３から２次元画像データをテレビジョン同期信号に同期して読み出し、ビデオ出力手段６５を介してディスプレイ装置に供給する。
【０１１５】
上述したように、本発明構成例においては、テクスチャ座標にオフセットをもたせてテクスチャ座標の語長を短縮することで、描画命令が短くて済む。また、描画ポリゴンやスプライト毎にテクスチャのＣＬＵＴを指定できるので、疑似カラーテクスチャを使用していても色数の制限が少ない。また、描画ポリゴンやスプライト毎に半透明率を指定するので画素毎の半透明率を指定する情報が必要でない。さらに、テクスチャ座標と頂点座標が同時に指定できるのでテクスチャパターン自体を変更せずにテクスチャマップポリゴンの色合いを変化させることができる。またさらに、半透明率として通常の０から１．０までの値ではなくて、マイナス（減算）の値が指定できるので、すでに描画されているピクセルの輝度値を減算することができる。その他、連結頂点を用いて、描画する多角形の頂点座標を指定する場合において、連結頂点数を３及び４に限定することで、終端コードを不要にし、描画命令長を短縮させた頂点指定が可能となる。また、描画の座標オフセットを描画命令の途中で変更できるため、オブジェクト（現実感のある物体すなわち描画対象の物体）単位の表示画面での平行移動を容易にすることができる。
【０１１６】
また、本発明構成例においては、画像をテクスチャパターンとして使用する際に、そのピクセルの最上位ビットで半透明のオン／オフを指定するので、半透明率の設定のための特定のαプレーンが必要にならない。さらに、画像を背景画面として使用する最に、そのピクセルの最上位ビットで上書きの禁止・許可を指定できるので、近景から先に描画することができる。また、画像をテクスチャパターンとして使用する場合には、カラーモードに応じて複数のモード（前記４ビットモード，８ビットモード，１６ビットモード等）を選ぶことができ、したがって、その中にダイレクトカラー方式と疑似カラー方式を混在できる。またさらに、フレームバッファとテクスチャ画像の品質に応じて様々なテクスチャタイプも選択できる。
【０１１７】
【発明の効果】
以上の説明からも明らかなように、本発明においては、複数のポリゴンからなる３次元画像データを記憶し、各ポリゴン毎に指定される特性データを記憶し、３次元画像データに透視変換を施して表示画面に対応する２次元画像情報に変換し、ポリゴンの特性を指定するための情報と２次元画像情報とを合成してポリゴン毎にパケット化された描画命令を生成することにより、命令語長を短縮できると共に、ソースビデオメモリの消費量も減らすことができる画像情報を生成すること可能となる。
【図面の簡単な説明】
【図１】本発明が適用される画像処理システムの概略的な構成を示すブロック回路図である。
【図２】ディスプレイ上への表示について説明するための図である。
【図３】ディスプレイ上の表示の設定について説明するための図である。
【図４】描画クリッピングの機能について説明するための図である。
【図５】テクスチャページについて説明するための図である。
【図６】ＣＬＵＴ構造について説明するための図である。
【図７】ポリゴン又はスプライト描画の概念を説明するための図である。
【図８】フレームダブルバッファリングについて説明するための図である。
【図９】描画命令の命令形式（１）の構成を示す図である。
【図１０】命令形式（１）において座標オフセットを行う例を示す図である。
【図１１】描画命令の命令形式（２）の構成を示す図である。
【図１２】命令形式（２）において座標オフセットを行う例を示す図である。
【図１３】ＣＢＡの構成を示す図である。
【図１４】ＴＳＢの構成を示す図である。
【図１５】三角形描画コマンドのフォーマットを示す図である。
【図１６】三角形描画コマンドのデータ構成例を示す図である。
【図１７】直線描画コマンドのフォーマットを示す図である。
【図１８】連結直線を描画する際に必要な終端コードのフォーマットを示す図である。
【図１９】直線描画コマンドのデータ構成例を示す図である。
【図２０】スプライト描画コマンドのフォーマットを示す図である。
【図２１】スプライト描画コマンドのデータ構成例を示す図である。
【図２２】ローカルローカル転送コマンドのフォーマットを示す図である。
【図２３】ローカルローカル転送コマンドのデータ構成例を示す図である。
【図２４】ホストローカル転送コマンドのフォーマットを示す図である。
【図２５】ホストローカル転送コマンドのデータ構成例を示す図である。
【図２６】ローカルホスト転送コマンドのフォーマットを示す図である。
【図２７】ローカルホスト転送コマンドのデータ構成例を示す図である。
【図２８】設定コマンドのフォーマットを示す図である。
【図２９】モード設定コマンドのフォーマットを示す図である。
【図３０】テクスチャパターン繰り返し設定コマンドのフォーマットを示す図である。
【図３１】クリッピングスタート及びクリッピングエンド設定コマンドのフォーマットを示す図である。
【図３２】オフセット設定コマンドのフォーマットを示す図である。
【図３３】特殊コマンドのフォーマットを示す図である。
【図３４】ＩＲＱ発生コマンドのフォーマットを示す図である。
【図３５】ＮＯＰコマンドのフォーマットを示す図である。
【図３６】キャッシュフラッシュコマンドのフォーマットを示す図である。
【図３７】ブロックライトコマンドのフォーマットを示す図である。
【図３８】ブロックライトコマンドのデータ構成例を示す図である。
【図３９】ピクセルフォーマットを示す図である。
【図４０】テクスチャパターンフォーマットを示す図である。
【図４１】４ビット／ピクセル，８ビット／ピクセルがＣＬＵＴを用いて変換された１６ビットカラーフォーマットを示す図である。
【図４２】１６ビット／ピクセルのフォーマットを示す図である。
【図４３】本構成例のシステムにて適用される画像情報生成及び画像情報処理の処理の流れを示すフローチャートである。
【図４４】従来の画像作成装置（家庭用ゲーム機）の構成例を示すブロック回路図である。
【図４５】従来の画像作成装置による画像作成方法の説明に用いる図である。
【符号の説明】
５１ ＣＰＵ
５２ 周辺デバイスコントローラ
５３ メインメモリ
５４ ＲＯＭ
６０ グラフィックシステム
６１ ジオメトリトランスファエンジン（ＧＴＥ）
６２ グラフィックスプロセッシングユニット
６３ フレームバッファ
６４ 画像デコーダ（ＭＤＥＣ）
６５ ビデオ出力手段（ディスプレイ装置）
７０ サウンドシステム
７１ サウンドプロセッシングユニット（ＳＰＵ）
７２ サウンドバッファ
７３ スピーカ
８０ 光学ディスク制御部
８１ ディスクドライブ装置
８２ デコーダ
８３ バッファ
９０ 通信制御部
９１ 通信制御機
９２ コントローラ
９３ メモリカード
１０１ パラレルＩ／Ｏポート
１０２ シリアルＩ／Ｏポート[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image information generating apparatus and method for creating image information by information processing, an image information processing apparatus and method, and a recording medium on which image information is recorded.
[0002]
[Prior art]
For example, in a home game machine, a personal computer device, a graphic computer device, or the like, most of the images output and displayed on a television receiver, a monitor receiver, a CRT display device, or the like are two-dimensional. , An image is displayed in such a form that a two-dimensional character or the like is appropriately arranged on a two-dimensional background and moved or changed.
[0003]
However, in the above-described two-dimensional image display or video, there are limitations on expressible backgrounds and characters and their movements, and for example, it is difficult to enhance the sense of reality of the game.
[0004]
Therefore, for example, a pseudo three-dimensional image or video is created by the following method. That is, images viewed from several directions are prepared as the character, and one of these images is selected and displayed according to a change in the viewpoint on the display screen or the like. To represent a pseudo three-dimensional image by superimposing the images in the depth direction. When generating or creating image data, a texture mapping method such as attaching a so-called texture (fabric, ground pattern) image to a desired surface such as a polyhedron or the like, and color data of the image through a so-called color lookup table. A method of changing a display color by conversion is employed.
[0005]
Here, FIG. 44 shows an example of a schematic configuration of a conventional home game machine. In FIG. 44, a CPU 391 composed of a microprocessor or the like extracts operation information of an input device 394 such as an input pad or a joystick through the main bus 399 via the interface 393. Simultaneously with the extraction of the operation information, the data of the three-dimensional image stored in the main memory 392 is transferred to the source video memory 395 by the video processor 396 and stored.
[0006]
Further, the CPU 391 sends to the video processor 396 a reading order of image data for superimposing and displaying images stored in the source video memory 395. The video processor 396 reads the image data from the source video memory 395 in accordance with the reading order of the image data, and superimposes and displays the images.
[0007]
At the same time as displaying the image as described above, the audio processor 397 outputs audio data corresponding to the displayed image stored in the audio memory 398 based on the audio information in the extracted operation information.
[0008]
FIG. 45 is a diagram illustrating a procedure for outputting a three-dimensional image using data of a two-dimensional image in a consumer game machine having the configuration illustrated in FIG. 44. FIG. 45 illustrates a case where a cylindrical object is displayed as a three-dimensional image on a checkered background image.
[0009]
In the source video memory 395 in FIG. 45, a checkered background image 200 and a rectangular image representing a cross section in the depth direction of a cylindrical object on the background image 200, so-called sprites 201, 202, 203, and 204, are stored. Is stored. It should be noted that a polygon having more than a triangle is called a polygon, and a quadrilateral polygon is particularly called a sprite. Portions other than the image of the cross section of the cylinder on the sprites 201, 202, 203, and 204, which are rectangular images, are drawn in a transparent color.
[0010]
The sync generator 400 in the video processor 396 generates a read address signal according to the synchronization signal of the image to be displayed. The sync generator 400 sends the read address signal to the read address table 401 provided from the CPU 391 in FIG. 44 via the main bus 399. Further, the sync generator 400 reads the image data in the source video memory 395 according to the information from the read address table 401.
[0011]
The read image data is sequentially superimposed by the superimposition processing unit 403 based on the superimposition order of the images in the priority table 402 provided via the main bus 399 by the CPU 391. In this case, the background image 200 has the lowest rank and the rectangular images 201, 202, 203, and 204 have higher ranks in this order.
[0012]
Next, in the transparent color processing unit 404, in order to display a portion other than the cylinder as a background image, a portion other than the cylinder displayed by the images 201, 202, 203, and 204 of the cross section of the overlapped cylinder is made transparent. Is performed.
[0013]
By the above-described processing, the data of the two-dimensional image of the cylindrical object is output as the image data of the three-dimensional image VD0 shown in FIG.
[0014]
[Problems to be solved by the invention]
By the way, a color is specified by texture mapping or a color lookup table, and pixel data of an image displayed before (for example, data composed of three primary color data of R, G, and B, the same applies hereinafter) is to be drawn next. Specifying the translucent processing when performing translucent processing by mixing pixel data of an image with a predetermined ratio α, and specifying ON / OFF of dither processing for adding noise to a color boundary to blur. In this case, the CPU 391 outputs drawing instructions for these, but the instruction word length for specifying a plurality of textures and color look-up tables, for specifying translucent processing, for specifying dither processing, and the like becomes longer. , The amount of data held in the source video memory 395 also increases.
[0015]
In the above-described apparatus, for example, the translucent processing is performed by the transparent processing unit 404 of the video processor 396. In the transparent processing unit 404, based on the data of the mixture ratio α supplied from the CPU 391, the previous pixel The translucent process is performed by mixing the data and the pixel data to be drawn at a predetermined mixing ratio α. In this case, in the conventional translucent processing, the value of the mixture ratio α is included in the drawing command, and is stored in the source video memory 395 for each pixel based on the drawing command. Therefore, if the mixing ratio is to be set finely, the number of bits representing the value of the mixing ratio α increases, the data amount of the drawing command increases, and the capacity in the source video memory 395 is consumed.
[0016]
Accordingly, the present invention provides an image information generating apparatus and method, an image information processing apparatus and method, and an image information generating method capable of generating image information capable of reducing the instruction word length and reducing the consumption of a source video memory. Is provided.
[0017]
[Means for Solving the Problems]
In the image information generating apparatus and method of the present invention, three-dimensional image data composed of a plurality of polygons is stored, characteristic data designated for each polygon is stored, and the three-dimensional image data is subjected to perspective transformation to display a screen. The above-mentioned problem is solved by converting the two-dimensional image information into two-dimensional image information corresponding to the above, and combining the information for designating the characteristics of the polygon and the two-dimensional image information to generate a drawing command packetized for each polygon. I do.
[0018]
Also, in the image information processing apparatus and method of the present invention, three-dimensional image data composed of a plurality of polygons is stored, characteristic data designated for each polygon is stored, and perspective transformation is performed on the three-dimensional image data. The information is converted into two-dimensional image information corresponding to the display screen, and information for designating the characteristics of the polygon is combined with the two-dimensional image information to generate a drawing command packetized for each polygon. The above-mentioned problem is solved by drawing a two-dimensional image in an image memory based on characteristic data specified by a drawing command, reading the two-dimensional image data from the image memory in synchronization with a television synchronization signal, and supplying the data to a display unit. I do.
[0019]
Further, in the recording medium according to the present invention, the above-mentioned problem is solved by recording the three-dimensional image data composed of a plurality of polygons and the characteristic data designated for each polygon by packetizing them in polygon units. .
[0020]
That is, according to the present invention, the instruction word length is reduced by synthesizing the information specifying the characteristics of the polygon and the two-dimensional image information to generate a drawing instruction packetized for each polygon.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0022]
First, an image processing system that generates and displays three-dimensional graphics data using image data generated by the image information generation method and the image information processing method of the present invention will be described. The image processing system of this configuration example is applied to, for example, a home game machine, a personal computer device, a graphic computer device, or the like, and the example of FIG. 1 shows an example in which the image processing system is applied to a home game machine.
[0023]
The image processing system according to this configuration example is configured to store data (for example, a game program or the like) from, for example, an optical disk (for example, a CD-ROM disk) which is a recording medium of the present invention in which data of an image data format of the present invention described later is recorded. ) Is read out and executed, whereby a display (for example, a game or the like) in accordance with an instruction from the user can be performed, and specifically, has a configuration as shown in FIG.
[0024]
Further, the image processing system of this configuration example includes a main memory 53 for storing three-dimensional image data read from a CD-ROM disk, a color information table and texture pattern information as characteristic data designated for each polygon. , A frame buffer 63 for storing translucency designation data and the like, and coordinate transformation means for performing perspective transformation processing on three-dimensional image data read from a CD-ROM disc to convert the data into two-dimensional image information. A geometry transfer engine (GTE) 61, a CPU 51 as drawing command generating means for generating a drawing command packetized for each polygon by combining the two-dimensional image information and information designating the characteristics of the polygon; The two-dimensional image information is stored in the frame buffer 63 based on the characteristic data specified by the drawn drawing command. A graphics processing unit (GPU 62) for displaying images, and video output means 65 for reading out two-dimensional image data from the frame buffer 63 in synchronization with a television synchronization signal and supplying the data to display means such as a display device. Things.
[0025]
That is, the image processing system includes a control system 50 including a central processing unit (CPU 51) and its peripheral devices (peripheral device controller 52 and the like), a graphics processing unit (GPU 62) for drawing on the frame buffer 63, and the like. A graphic system 60, a sound system 70 including a sound processing unit (SPU 71) for generating musical tones, sound effects and the like, and an optical disk (CD-ROM disk) drive 81 as an auxiliary storage device for controlling and reproducing information. An optical disk control unit 80 for performing decoding and the like, and a communication control unit for controlling input and output from an auxiliary memory (memory card 93) for storing an instruction input from a controller 92 for inputting an instruction from a user and game settings and the like. 90 and communication control from the control system 50. And a main bus B, etc. until the part 90 is connected.
[0026]
The control system 50 includes a CPU 51, a peripheral device controller 52 that performs interrupt control, time control, memory control, direct memory access (DMA) transfer control, and the like, and a main storage device (main memory) including, for example, 2 megabytes of RAM. And a ROM 54 of, for example, 512 kilobytes in which a program such as a so-called operating system for managing the main memory 53, the graphic system 60, the sound system 70, and the like is stored.
[0027]
The CPU 51 is, for example, a 32-bit reduced instruction set computer (RISC) CPU, and controls the entire apparatus by executing an operating system stored in the ROM 54. The CPU 51 has an instruction cache and a scratch pad memory, and also manages a real memory.
[0028]
The graphic system 60 includes a main memory 53 for temporarily storing data read from a CD-ROM, and a geometry co-processor for performing coordinate conversion and the like on the data stored in the main memory 53. A transfer engine (GTE) 61, a graphics processing unit (GPU) 62 for performing drawing based on a drawing instruction (drawing command) from the CPU 51, and a 1-megabyte frame buffer 63 for storing an image drawn by the GPU 62, for example. And an image decoder (hereinafter referred to as MDEC) 64 for decoding image data that has been subjected to orthogonal transformation such as so-called discrete cosine transformation and is compressed and encoded.
[0029]
The GTE 61 includes, for example, a parallel operation mechanism that executes a plurality of operations in parallel. As a coprocessor of the CPU 51, the GTE 61 performs coordinate transformation such as perspective transformation and an inner product operation of a normal vector and a light source vector in response to an operation request from the CPU 51. Light source calculations, for example, calculations on fixed-point matrices and vectors, can be performed at high speed.
[0030]
More specifically, the GTE 61 can perform a coordinate calculation of a maximum of about 1.5 million polygons per second in the case of performing the flat shading for drawing the same color on one triangular polygon. Accordingly, in this image processing system, the load on the CPU 51 can be reduced, and high-speed coordinate calculation can be performed. The polygon is a minimum unit of a figure for forming a three-dimensional object displayed on the display, and is a polygon such as a triangle or a quadrangle.
[0031]
The GPU 62 operates according to a polygon drawing command from the CPU 51 and draws a polygon (polygon) or the like on the frame buffer 63. The GPU 62 is capable of rendering a maximum of about 360,000 polygons per second. The GPU 62 has a two-dimensional address space independent of the CPU 51, and the frame buffer 63 is mapped in the two-dimensional address space.
[0032]
The frame buffer 63 is formed of a so-called dual-port RAM, and can simultaneously perform drawing from the GPU 62 or transfer from the main memory 53 and reading for display.
[0033]
The frame buffer 63 has a capacity of, for example, 1 megabyte, and is handled as a matrix of 1024 horizontal pixels and 512 vertical pixels each having 16 bits.
[0034]
An arbitrary display area of the frame buffer 63 can be output to video output means 65 such as a display device.
[0035]
The frame buffer 63 is a second area in which a color lookup table (CLUT) that the GPU 62 refers to when drawing a polygon or the like is stored in addition to a display area output as a video output. A CLUT area and a texture area which is a first storage area for storing a material (texture) to be inserted (mapped) into a polygon or the like which is subjected to coordinate conversion at the time of drawing and drawn by the GPU 62. Area Is provided. The CLUT area and the texture area are dynamically changed according to a change in the display area. That is, the frame buffer 63 can perform drawing access to the area being displayed, and can also perform high-speed DMA transfer with the main memory 53.
[0036]
In addition to the flat shading described above, the GPU 62 performs Gouraud shading, which determines the color in the polygon by interpolating from the colors of the vertices of the polygon, and texture mapping, which pastes the texture stored in the texture area on the polygon. Can be done.
[0037]
When performing such Gouraud shading or texture mapping, the GTE 61 can perform a coordinate calculation of a maximum of about 500,000 polygons per second.
[0038]
Under the control of the CPU 51, the MDEC 64 decodes the still or moving image data read from the CD-ROM disk and stored in the main memory 53, and stores the decoded data in the main memory 53 again. Specifically, the MDEC 64 can execute an inverse discrete cosine transform (inverse DCT) operation at a high speed, and can compress a color still image read from a CD-ROM disc (so-called JPEG) or a moving image encoding standard (accumulated media system). It is possible to decompress compressed data of so-called MPEG (only compression within a frame in this configuration example).
[0039]
The reproduced image data is stored in the frame buffer 63 via the GPU 62, so that the reproduced image data can be used as a background of the image drawn by the GPU 62.
[0040]
The sound system 70 includes a sound reproduction processing processor (SPU) 71 for generating musical tones and sound effects based on instructions from the CPU 51, and data and sound source data of voices and musical sounds read from a CD-ROM disk. And the like, and a sound buffer 72 of, for example, 512 kilobytes, and a speaker 73 as sound output means for outputting musical sounds, sound effects, and the like generated by the SPU 71.
[0041]
The SPU 71 performs an ADPCM decoding function of reproducing audio data that has been subjected to adaptive differential coding (ADPCM) using 16-bit audio data as a 4-bit differential signal, and reproduces sound source data stored in the sound buffer 72. , A reproduction function of generating sound effects and the like, and a modulation function of modulating and reproducing audio data and the like stored in the sound buffer 72. That is, the SPU 71 has a built-in ADPCM sound source 24 voice having functions such as looping and automatic change of operation parameters using time as a system factor, and operates by operation from the CPU 51. The SPU 71 manages a unique address space to which the sound buffer 72 is mapped, transfers ADPCM data from the CPU 51 to the sound buffer 72, and reproduces data by directly passing key-on / key-off and modulation information.
[0042]
By providing such a function, the sound system 70 can be used as a so-called sampling sound source that generates musical tones, sound effects, and the like based on audio data and the like recorded in the sound buffer 72 in accordance with an instruction from the CPU 51. It has become.
[0043]
The optical disk control unit 80 includes a disk drive device 81 that reproduces programs, data, and the like recorded on an optical disk that is a CD-ROM disk, and a program that is recorded with an error correction (ECC) code, for example. , A decoder 82 for decoding data, etc., and a buffer 83 of, for example, 32 kilobytes for temporarily storing reproduction data from the disk drive device 81. That is, the optical disk control unit 80 includes components necessary for reading a disk, such as the drive device 81 and the decoder 82. Here, data such as CD-DA and CD-ROM XA can be supported as a disk format. The decoder 82 also constitutes a part of the sound system 70.
[0044]
The audio data recorded on the disk reproduced by the disk drive device 81 includes, in addition to the above-described ADPCM data (such as the CD-ROM XA ADPCM data), so-called PCM data obtained by converting an audio signal from analog to digital. is there.
[0045]
As ADPCM data, for example, audio data in which a difference between 16-bit digital data is represented by 4 bits and recorded is subjected to error correction and decoding by a decoder 82, and then supplied to the above-described SPU 71, where the SPU 71 converts the digital / digital data. After being subjected to processing such as analog conversion, it is used to drive the speaker 73.
[0046]
Further, audio data recorded as PCM data, for example, as 16-bit digital data, is decoded by the decoder 82 and then used to drive the speaker 73. Note that the audio output of the decoder 82 enters the SPU 71 once, is mixed with this SPU output, and becomes the final audio output via the reverb unit.
[0047]
The communication control unit 90 includes a communication control device 91 that controls communication with the CPU 51 via the main bus B, a controller 92 that inputs instructions from a user, and a memory card 93 that stores game settings and the like. And
[0048]
The controller 92 is an interface for transmitting the user's intention to the application, and has, for example, 16 instruction keys for inputting an instruction from the user. Is transmitted to the communication control device 91 about 60 times per second by synchronous communication. Then, the communication control device 91 transmits the state of the instruction key of the controller 92 to the CPU 51. Note that the controller 92 has two connectors on the main body, and it is also possible to connect many controllers using a multi-tap.
[0049]
As a result, an instruction from the user is input to the CPU 51, and the CPU 51 performs processing according to the instruction from the user based on the game program or the like being executed.
[0050]
Further, the CPU 51 transmits the stored data to the communication control device 91 when it is necessary to store the settings of the game being executed, the end of the game, or the results during the game or the like, and the communication control device 91 The data from the CPU 51 is stored in the memory card 93.
[0051]
Since this memory card 93 is separated from the main bus B, it can be inserted and removed with the power on. As a result, game settings and the like can be stored in the plurality of memory cards 93.
[0052]
The configuration example system includes a 16-bit parallel input / output (I / O) port 101 connected to the main bus B and an asynchronous serial input / output (I / O) port 102.
[0053]
In addition, connection with peripheral devices can be performed via the parallel I / O port 101, and communication with other video game devices and the like can be performed via the serial I / O port 102. Is available.
[0054]
By the way, between the main memory 53, the GPU 62, the MDEC 64, the decoder 82, and the like, it is necessary to transfer a large amount of image data at high speed when reading a program, displaying an image, or drawing.
[0055]
For this reason, in this image processing system, a so-called DMA that directly transfers data between the main memory 53, the GPU 62, the MDEC 64, the decoder 82, and the like under the control of the peripheral height controller 52 without the intervention of the CPU 51 as described above. The transfer can be performed.
[0056]
As a result, the load on the CPU 51 due to data transfer can be reduced, and high-speed data transfer can be performed.
[0057]
In this video game device, when the power is turned on, the CPU 51 executes the operating system stored in the ROM 54.
[0058]
By executing the operating system, the CPU 51 controls the graphic system 60, the sound system 70, and the like.
[0059]
When the operating system is executed, the CPU 51 initializes the entire apparatus such as operation check, and then controls the optical disk control unit 80 to execute a program such as a game recorded on the optical disk. I do.
[0060]
By executing a program such as a game, the CPU 51 controls the graphic system 60, the sound system 70, and the like in accordance with an input from a user to control display of an image, generation of sound effects, and generation of musical sounds. ing.
[0061]
Next, display on the display in the image processing system of this configuration example will be described.
[0062]
The GPU 62 displays the contents of an arbitrary rectangular area in the frame buffer 634 on a display such as a CRT of the video output unit 65 as it is. This area is hereinafter referred to as a display area. The relationship between the rectangular area and the display on the display screen is as shown in FIG.
[0063]
The GPU 62 supports the following ten screen modes.
[0064]

The screen size, that is, the number of pixels on the display screen is variable. As shown in FIG. 3, the display start position (coordinates (DTX, DTY)) and the display end position (coordinates (DBX, DBY)) are independent of each other in the horizontal and vertical directions. Can be specified.
[0065]
The relationship between the value that can be specified for each coordinate and the screen mode is as follows. The coordinate values DTX and DBX need to be set to be a multiple of four. Therefore, the minimum screen size is 4 pixels horizontally, 2 pixels vertically (non-interlace) or 4 pixels (interlace).
[0066]
[Specifiable range of X coordinate]
[Mode] [DTX] [DBX]
0,40 0-276 4-280
1,5 0-348 4-352
2,60-556 4-560
3,7 0-700 4-704
8,90-396 4-400
[Specifiable range of Y coordinate]
[Mode] [DTY] [DBY]
0-3,80-241 2-243
4-7,90-480 4-484
Next, the GPU 62 supports two modes relating to the number of display colors: a 16-bit direct mode (32768 colors) and a 24-bit direct mode (full color). The 16-bit direct mode (hereinafter referred to as 16-bit mode) is a 32768-color display mode. In the 16-bit mode, the number of display colors is limited as compared with the 24-bit direct mode (hereinafter referred to as the 24-bit mode), but the color calculation inside the GPU 62 at the time of drawing is performed in 24 bits, and the gradation is simulated. Since a so-called dither function is provided, the pseudo full color (24-bit color) display is possible. The 24-bit mode is a mode for displaying 16777216 colors (full color). However, only the display (bitmap display) of the image data transferred in the frame buffer 63 is possible, and the drawing function of the GPU 62 cannot be executed. Here, the bit length of one pixel is 24 bits, but the values of the coordinates and the display position on the frame buffer 63 need to be specified on the basis of 16 bits. That is, 640 × 480 24-bit image data is treated as 960 × 480 in the frame buffer 63. Further, the coordinate value DBX needs to be set to be a multiple of 8, so that the minimum screen size in this 24-bit mode is 8 × 2 pixels.
[0067]
In addition, the GPU 62 has the following drawing function.
[0068]
First, a 4-bit CLUT (4-bit mode, 16 colors / polygon, sprite) or an 8-bit CLUT (8-bit mode, 256 colors / polygon, sprite) for a polygon or sprite of 1 × 1 dot to 256 × 256 dots , 16-bit CLUT (16-bit mode, 32768 colors / polygon, sprite), etc. capable of drawing polygons or sprites,
Specifying the coordinates of each vertex of a polygon or sprite (a polygon such as a triangle or a quadrangle) on the screen and drawing it, flat shading that fills the inside of the polygon or sprite with the same color, and specifying a different color for each vertex A polygon drawing function that performs Gouraud shading for gradation inside, texture mapping that prepares and attaches two-dimensional image data (texture patterns, especially those for sprites are called sprite patterns) on the surfaces of polygons and sprites,
Straight line drawing function with gradation,
Image transfer functions such as transfer from the CPU 51 to the frame buffer 63, transfer from the frame buffer 63 to the CPU 51, transfer from the frame buffer 63 to the frame buffer 63,
Other functions include the function of translucent by taking the average of each pixel (referred to as the α blending function because pixel data of each pixel is mixed at a predetermined ratio α), and the dither function that blurs by adding noise to color boundaries And a drawing clipping function that does not display a portion beyond the drawing area, an offset designation function that moves the drawing origin according to the drawing area, and the like.
[0069]
Further, the coordinate system for drawing is in units of 11 bits with a sign, and each of X and Y takes a value of -1024 to +1023. Further, as shown in FIG. 4, the size of the frame buffer 63 in this configuration example is 1024 × 512, so that the protruding portion is folded back. The origin of the drawing coordinates can be freely changed in the frame buffer 63 by the function of arbitrarily setting the offset value of the coordinate values. The drawing is performed only on an arbitrary rectangular area in the frame buffer 63 by the drawing clipping function.
[0070]
Further, the GPU 62 supports a texture of a maximum of 256 × 256 dots, and the values of the vertical and horizontal can be freely set.
[0071]
The image data (texture pattern or sprite pattern) to be attached to the polygon or sprite is arranged in a non-display area of the frame buffer 63 as shown in FIG. The texture pattern or sprite pattern is transferred to the frame buffer 63 before executing the drawing command. The texture pattern or sprite pattern can be placed on the frame buffer 63 as many as the memory allows, with 256 × 256 pixels as one page, and this 256 × 256 area is called a texture page. The location of one texture page is determined by specifying the page number in a parameter for specifying the position (address) of the texture page called TSB of the drawing command.
[0072]
The texture pattern or the sprite pattern has three types of color modes: a 4-bit CLUT (4-bit mode), an 8-bit CLUT (8-bit mode), and a 16-bit CLUT (16-bit mode). In the 4-bit CLUT and 8-bit CLUT color modes, the CLUT is used.
[0073]
As shown in FIG. 6, the CLUT has 16 to 256 R, G, and B values of three primary colors representing colors to be finally displayed, which are arranged on the frame buffer 63. The R, G, and B values are numbered sequentially from the left on the frame buffer 63, and the texture pattern or sprite pattern represents the color of each pixel by this number. The CLUT can be selected in units of polygons or sprites, and it is possible to have an independent CLUT for all polygons or sprites. In FIG. 6, one entry has the same structure as one pixel in the 16-bit mode. Therefore, one set of CLUTs is 1 × 16 (in the 4-bit mode) and 1 × 255 (in the 8-bit mode). ) Is equal to the image data. The storage position of the CLUT in the frame buffer 63 is determined by specifying the left end coordinate of the CLUT to be used as a parameter for specifying the position (address) of the CLUT called CBA in the drawing command.
[0074]
Furthermore, the concept of polygon or sprite drawing can be schematically shown in FIG. In the example of FIG. 7, a sprite is taken as an example. In addition, U and V of the drawing command in FIG. 7 are parameters for specifying the position of the texture page in horizontal (U) and vertical (V), and X and Y are parameters for specifying the position of the drawing area. is there.
[0075]
The GPU 62 uses a method called frame double buffering as a moving image display method. This frame double buffering means, as shown in FIG. 8, that two rectangular areas are prepared on a frame buffer 63, the other side is displayed while one area is being drawn, and 2 The two areas are exchanged for each other. This makes it possible to avoid displaying the state of rewriting. Note that the buffer switching operation is performed during the vertical blanking period. In the GPU 62, since the rectangular area to be drawn and the origin of the coordinate system can be freely set, a plurality of buffers can be realized by moving the two.
[0076]
Next, a description will be given of an instruction format (instruction set) output by the CPU 51 at the time of texture mapping and Gouraud shading in the image processing system of this configuration example.
[0077]
First, the drawing command format will be described.
[0078]
As the command format (1), a packet configuration as shown in FIG. 9 is used in order for the CPU 51 to directly specify a drawing command. In FIG. 9, R, G, and B indicate luminance values shared by all vertices of the polygon, and Xn and Yn indicate two-dimensional coordinates of the vertex n in the drawing space. For this instruction format (1), for example, in the case of an instruction to fill an area surrounded by (X0, Y0)-(X1, Y1)-(X2, Y2) with luminance values (R, G, B), , And the coordinate offset for subsequent drawing is changed to (0FX, 0FY).
[0079]
Next, as the instruction format (2), as shown in FIG. 11, a packet configuration in which a tag in which a word number of the instruction and a pointer to the next instruction are added to the drawing instruction of the type of the instruction format (1) is used. . Note that SIZE in FIG. 11 indicates the word length of the instruction (4 in this example), and ADDR indicates the start address of the next instruction. As a result, a plurality of instruction sequences that are not placed in a continuous area on the frame buffer 63 can be connected and executed at a time. In this case, the transfer of the drawing command is performed by dedicated hardware, and the CPU 51 is not involved at all. In the instruction format (2), for example, in the case of an instruction to fill an area surrounded by (X0, Y0)-(X1, Y1)-(X2, Y2) with a luminance value (R, G, B), 12, and the coordinate offset of the subsequent drawing is changed.
[0080]
Next, the data format of the present invention will be described in detail.
[0081]
The GPU 62 sequentially executes a packetized command (rendering command) sequence supplied from the host (CPU 51). In the following description, the following symbols are used.
[0082]

Although 16 bits are assigned to Xn and Yn in the command, actually, up to the lower 11 bits are effective. The bit assignments of CBA and TSB are as shown in FIGS. In FIG. 13, CLX is the head address (6 bits) of the CLUT on the X axis, and CLY is the head address (9 bits) of the CLUT on the Y axis. The TSB shown in FIG. 14 has the same bit assignment as the lower bits of the MODE command (see the setting command described later). The TPF in FIG. 14 is the depth of the pixel of the texture pattern, which is 00 in 4-bit mode (CLUT), 01 in 8-bit mode (CLUT), and 10 in 16-bit mode (CLUT). ABR in FIG. 14 indicates a translucent rate, and when it is 00, it is 0.50 × F + 0.50 × B, when it is 01, it is 1.00 × F + 1.00 × B, and when it is 10, it is 0.50 × F + 1.00 × B. , 11 is 0.25 × F + 1.00 × B (F corresponds to the foreground and B corresponds to the background). In FIG. 14, TBX is a base address (upper 5 bits) in the texture pattern source space x direction, and TBY is a base address (upper 1 bit) in the texture pattern source space y direction.
[0083]
Next, as shown in FIG. 15, the triangle drawing command (command code = 1h) gives vertex information as a command argument after the command code (including options). The number and format of the arguments differ depending on the option. When IIP in FIG. 15 is 0, a triangle is drawn (flat shading) with one type of luminance value (R, G, B). When IIP is 1, the luminance value of three vertices is linearly interpolated to convert the triangle. Draw (Gouraud shading). When CNT is 0, one triangle is drawn with three vertices following the command, and when CNT is 1, a connected triangle is drawn (quadrilateral) with four vertices following the command. When TME is 0, texture mapping is turned off, and when TME is 1, texture mapping is turned on. When ABE is 0, the translucent processing is turned off, and when ABE is 1, the translucent processing is turned on. TGE is effective only in the case of TME. When TGE is 0, the texture pattern is multiplied by the luminance value, and when it is 1, only the texture pattern is drawn. The data structure here is 2 ³ As shown in FIG.
[0084]
Next, as shown in FIG. 17, a straight line drawing command (command code = 2h) gives end point information as a command argument after a command code (including an option). The number and format of the arguments differ depending on the option. When the IIP in FIG. 17 is 0, the pixel is drawn with the designated luminance value, and when the IIP is 1, the luminance value of the two vertices is linearly interpolated with the displacement in the long axis direction of the line segment. When CNT is 0, one straight line is drawn at the two end points following the command, and when CNT is 1, a connected straight line is drawn. When ABE is 0, the translucent processing is turned off, and when ABE is 1, the translucent processing is turned on.
[0085]
When drawing a connected straight line, an end code (TERMINATION CODE) indicating the end of the command is finally required. The format of the termination code is as shown in FIG. 18, and an example of the data structure is shown in FIG. Since only the lower 11 bits of the coordinate values Xn and Yn are valid, the coordinate values do not collide with the termination code in normal use.
[0086]
Next, the sprite drawing command (command code = 3h) is as shown in FIG. 20, and an example of the data structure is shown in FIG. In this sprite drawing command, after the command code (including options), luminance information, the lower left point of the rectangular area, the upper left point of the texture source space, and the width and height of the rectangular area are given as command arguments. The number and format of arguments differ depending on the option. Also, since the sprite drawing command processes two pixels at the same time, Un must specify an even number (the lower one bit has no meaning). When TME in FIG. 20 is 0, texture mapping is turned off, and when TME is 1, texture mapping is turned on. When ABE is 0, the translucent process is turned off, and when ABE is 1, the translucent process is turned on. When TGE (valid only for TME) is 0, the texture pattern (in this case, sprite pattern) is drawn by multiplying it by a constant luminance value, and when TGE is 1, only the texture pattern (sprite pattern) is drawn. SIZ designates the size of the rectangular area, 00 designates the H and W fields, 01 designates 1 × 1, 10 designates 8 × 8, and 11 designates 16 × 16.
[0087]
Next, as a local-local transfer command (command code = 4h), that is, a transfer command between frame buffers, for example, a rectangular area transfer command is as shown in FIG. 22, and the data configuration is as shown in FIG. This rectangular area transfer command gives, after the command code (including options), the upper left point of the source rectangular area, the upper left point of the destination rectangular area, and the width and height of the rectangular area as command arguments. In the figure, CODE indicates a command code and an option, SX and SY indicate the coordinates of the upper left point of the source (transfer source) rectangular area, and DX and DY indicate the coordinates of the upper left point of the destination (transfer destination) rectangular area. , W indicates the width of the rectangular area, and H indicates the height of the rectangular area.
[0088]
Next, the host local transfer command (command code = 5h) is as shown in FIG. 24, and the data configuration is as shown in FIG. The host local transfer command is a transfer command between the CPU and the frame buffer, and gives, as a command argument, a command code (including an option), for example, the upper left point of the destination rectangular area, the width and height of the rectangular area, and the transfer data. . In the figure, CODE indicates a command code and an option, DX and DY indicate the coordinates of the upper left point of the destination (destination) rectangular area, W indicates the width of the rectangular area, H indicates the height of the rectangular area, FRAM0 to FRAMn indicate transfer data.
[0089]
Next, the local host transfer command (command code = 6h) is as shown in FIG. 26, and the data configuration is as shown in FIG. The local host transfer command is a transfer command between the frame buffer and the CPU, and gives, for example, the upper left point of the source rectangular area and the width and height of the rectangular area as command arguments. In the figure, CODE indicates a command code and an option, SX and SY indicate the coordinates of the upper left corner of the source (transfer source) rectangular area, W indicates the width of the rectangular area, and H indicates the height of the rectangular area. Also, a command (parameter read) using a general-purpose port cannot be performed during local host transfer.
[0090]
Next, the setting command (command code = 7h) is a command for setting various parameter registers as shown in FIG. This gives the command code (including the address) and the set value. In the figure, CODE indicates a command code and an option, ADDR indicates an address, and DATA indicates a parameter.
[0091]
Here, among these setting commands, the mode (MODE) setting command (address = 1h) has the configuration shown in FIG. 29, and the TPF in the figure is the pixel depth of the texture pattern (sprite pattern in the case of splice). 00 indicates a 4-bit mode (CLUT), 01 indicates an 8-bit mode (CLUT), and 10 indicates a 16-bit mode (direct). DTD is 0 when dithering is not performed, and 1 when dithering is performed. When DFE is 0, only fields not displayed during interlace are drawn, and when 1, DFE is drawn in both fields during interlace. ABR indicates a translucent rate, when 00 is 0.50 × F + 0.50 × B, when 01 is 1.00 × F + 1.00 × B, when 10 is 0.50 × F + 1.00 × B, 11 indicates 0.25 × F + 1.00 × B (F corresponds to the foreground and B corresponds to the background). TBX indicates a texture pattern source space x direction base address (upper 4 bits), and TBY indicates a texture pattern source space y direction base address (upper 1 bit).
[0092]
A texture pattern repeat (TEXTURE PATTERN REPEAT) setting command (address = 2h) among the setting commands has a configuration shown in FIG. 30, in which TUM is a texture pattern U coordinate repetition mask and TVM is a texture pattern V coordinate repetition mask. TUA indicates a texture pattern repetition U upper fixed address, and TUA indicates a texture pattern repetition V upper fixed address.
[0093]
Next, among the setting commands, the clipping start (CLIPPING START) setting command (address = 3h) and the clipping end (CLIPPING END) setting command (address = 4h) have the configuration shown in FIG. FIG. 31A shows a clipping start setting command, and FIG. 31B shows a clipping end setting command. Clipping is valid for polygon (triangle) / straight line / sprite drawing commands and has no effect on host local / local local transfers. In the figure, CTX indicates the X address (10 bits) of the upper left point of clipping, CTY indicates the Y address (9 bits) of the upper left point of clipping, CBX indicates the X address (10 bits) of the lower right point of clipping, and CBY Indicates the Y address (9 bits) of the lower right point of clipping.
[0094]
Next, among the setting commands, an offset (OFFSET) setting command (address = 5h) has a configuration shown in FIG. 32, where OFX is a coordinate offset value (X) (signed 11 bits), and OFY is a coordinate offset value. (Y) (signed 11 bits).
[0095]
Next, the special command (address = 0h) has a configuration shown in FIG. 33. The special commands include an interrupt request enable command and a NOP command described later. This is specified by command and option.
[0096]
Among the special commands, an IRQ (interrupt request) generation command has a configuration shown in FIG. 34 and asserts the IRQ pin.
[0097]
In addition, among special commands, a NOP (no operation) command has a configuration shown in FIG. 35, and does nothing at this time.
[0098]
Further, the cache flush command among the special commands has a configuration shown in FIG. 36, and flushes the contents of the texture cache and the CLUT. However, when the host local transfer and the local host transfer are performed, only the texture cache is automatically flushed (the CLUT is saved).
[0099]
Also, among the special commands, the block write command has the configuration shown in FIG. 37, and the data configuration becomes as shown in FIG. This command initializes the rectangle at high speed. Note that W and H in the figure indicate the size of the rectangular area. Further, R, G, and B are designated by 8 bits, but the values actually written into the memory are only the above 4 bits. The start position (X0, Y0) and size (H, V) of the rectangular area are both specified as integral multiples of 32 pixels. The lower 4 bits have no meaning.
[0100]
The GPU 62 has a dedicated local memory, which is used not only as a frame buffer for display but also as an area for a texture pattern or a texture CLUT. That is, this local memory is the frame buffer 63 of FIG.
[0101]
As the addressing to the frame buffer 63, the area drawn by the GPU 62 has a size of 0 to 1023 in the x direction and 0 to 511 in the y direction. The correspondence with the one-dimensional address of the local memory (frame buffer 63) is as follows.
One-dimensional address = X _A + Y _A × 1024
It is. However, in the case of 24-bit mode,
One-dimensional address = (3/2) × X _A + Y _A × 1024
It is.
[0102]
Since the page size of the frame buffer 63 is fixed at 1024, XA is actually a column address and Y is _A Corresponds to the row address. Drawing can be performed anywhere in the frame buffer 63, and an arbitrary area in the frame buffer 63 can be displayed. However, the size that can be displayed is limited depending on the mode. Further, the address X of the frame buffer 63 _A , Y _A Are designated by 10-bit and 9-bit unsigned, respectively. However, the coordinate values x and y used for drawing the polygon are each specified by an 11-bit signed code. Further, the drawing is performed in the frame buffer 63 using the value obtained by adding the offset (OFX, OFY) specified by the offset register to (x, y) as an address. However, no image is drawn in an area exceeding the size of the mounted frame memory, 1024 × 512.
[0103]
Next, the pixel format will be described. The GPU 63 has a 24-bit mode of R: G: B = 8: 8: 8 (bit) as shown in (a) of FIG. 39 and an R: G: B = 5 as shown in (b) of FIG. : 5: 5 (bit) 16-bit mode is supported. However, it is not possible to draw in the 24-bit mode only for display. In the figure, R indicates a red component, G indicates a green component, B indicates a blue component, and STP indicates an overwrite flag. In some modes, when 1 is designated as STP, the contents of the pixel are saved even if a new drawing is executed on that pixel thereafter. As a result, the pattern drawn first can be held.
[0104]
Next, according to this configuration example format, when rendering a polygon / sprite, texture mapping can be performed using a pattern (texture pattern or sprite pattern) placed on a texture page. In the following description, (x, y) indicates coordinates in the drawing space, and (u, v) indicates coordinates in the texture page space.
[0105]
First, an area in the frame buffer where a texture pattern or a sprite pattern is placed is called a texture page or a texture page space. As the pixel format of the texture pattern or the sprite pattern, there are three modes of 4, 8, and 16 bits / pixel. The 4-bit and 8-bit modes are pseudo colors, and the 16-bit mode is direct colors. These modes can be switched for each polygon or sprite. For texture patterns and sprite patterns other than the 16-bit mode, several pixels are packed in one word. Therefore, the pixels of the texture pattern or sprite pattern and the addresses of the frame buffer do not correspond one-to-one. Therefore, care must be taken in specifying addresses when loading texture patterns and sprite patterns into the frame buffer. The pixel format in each mode is as shown in FIG. 40 below.
[0106]
In the case of 4 bits / pixel and 8 bits / pixel shown in FIGS. 40A and 40B, the pixel value is not an actual luminance value but an index into the CLUT. From this, the pixels are converted to a 16-bit color format using the CLUT as shown in FIG. In the figure, R indicates a red component, G indicates a green component, B indicates a blue component, and STP indicates a translucent flag.
[0107]
In the case of 16 bits / pixel, the CLUT is not used and is directly used as a luminance value. This format is as shown in FIG. 42 similar to FIG. In the drawing, R indicates a red component, G indicates a green component, B indicates a blue component, and STP indicates a translucent flag. Pixels for which 1 is designated as STP are rendered translucent, and the translucent rate can be set independently for each polygon or sprite.
[0108]
Further, in the case of the 4-bit mode or the 8-bit mode, the color (luminance) of the texture can be determined using the texture CLUT. Although there can be any number of texture CLUTs in the frame buffer, only one type of CLUT can be used in one drawing command. CLUT can be selected by designating the start address on the frame buffer. The start address is specified by the CBA of the command argument.
[0109]
The GPU 62 has a texture CLUT cache inside, and loads a new CLUT if there is no necessary CLUT in the cache prior to polygon rendering. Therefore, when the same CLUT is used repeatedly, the drawing speed is increased by the load of the CLUT.
[0110]
Next, the flow of image information generation and image information processing to which the system and the format of the above configuration example are applied will be described with reference to FIG.
[0111]
In FIG. 43, in step S10, three-dimensional image data composed of a plurality of polygons is read out from a CD-ROM disk and stored in the main memory 53. In step S11, a color information table as characteristic data designated for each polygon is provided. The texture pattern information and the translucency specifying data are stored in the frame buffer 63.
[0112]
In step S12, two-dimensional image information is generated from the three-dimensional image data by performing coordinate transformation processing such as perspective transformation in the graphic system 60. In the next step S13, the two-dimensional image information and the characteristics of each polygon are determined. The information is combined with the information for designation to generate a drawing command packetized for each polygon.
[0113]
In step S14, a two-dimensional image is drawn in the frame buffer 63 based on the characteristic data specified by the generated drawing command.
[0114]
In the next step S15, the two-dimensional image data is read out from the frame buffer 63 in synchronization with the television synchronization signal, and supplied to the display device via the video output means 65.
[0115]
As described above, in the configuration example of the present invention, the rendering command can be shortened by giving an offset to the texture coordinates to shorten the word length of the texture coordinates. In addition, since the CLUT of the texture can be specified for each drawing polygon or sprite, the number of colors is not limited even if a pseudo color texture is used. Further, since the translucency is specified for each drawing polygon or sprite, information for specifying the translucency for each pixel is not required. Further, since the texture coordinates and the vertex coordinates can be specified at the same time, the color of the texture map polygon can be changed without changing the texture pattern itself. Further, since a value of minus (subtraction) can be designated as the translucency instead of the usual value of 0 to 1.0, the luminance value of the pixel already drawn can be subtracted. In addition, when specifying the vertex coordinates of the polygon to be drawn using the connected vertices, by limiting the number of connected vertices to 3 and 4, the end code is not required, and the vertex specification in which the drawing instruction length is shortened can be performed. It becomes possible. In addition, since the coordinate offset of the drawing can be changed in the middle of the drawing command, it is possible to easily perform the parallel movement on the display screen in units of objects (real objects, that is, objects to be drawn).
[0116]
Further, in the configuration example of the present invention, when an image is used as a texture pattern, on / off of the translucency is designated by the most significant bit of the pixel, so that a specific α plane for setting the translucency is not included. Not needed. Further, when the image is used as a background screen, overwriting prohibition / permission can be designated by the most significant bit of the pixel, so that the foreground can be drawn first. When an image is used as a texture pattern, a plurality of modes (the 4-bit mode, 8-bit mode, 16-bit mode, etc.) can be selected according to the color mode. And the pseudo color method can be mixed. Furthermore, various texture types can be selected according to the quality of the frame buffer and the texture image.
[0117]
【The invention's effect】
As is clear from the above description, in the present invention, three-dimensional image data composed of a plurality of polygons is stored, characteristic data designated for each polygon is stored, and perspective transformation is performed on the three-dimensional image data. By converting the information into two-dimensional image information corresponding to the display screen, and combining the information for designating the characteristics of the polygon and the two-dimensional image information to generate a drawing instruction packetized for each polygon. It is possible to generate image information that can shorten the length and reduce the consumption of the source video memory.
[Brief description of the drawings]
FIG. 1 is a block circuit diagram showing a schematic configuration of an image processing system to which the present invention is applied.
FIG. 2 is a diagram for describing display on a display.
FIG. 3 is a diagram for describing display settings on a display.
FIG. 4 is a diagram for explaining a drawing clipping function;
FIG. 5 is a diagram illustrating a texture page.
FIG. 6 is a diagram for explaining a CLUT structure.
FIG. 7 is a diagram for explaining the concept of polygon or sprite drawing.
FIG. 8 is a diagram for explaining frame double buffering.
FIG. 9 is a diagram showing a configuration of a command format (1) of a drawing command.
FIG. 10 is a diagram illustrating an example of performing coordinate offset in the command format (1).
FIG. 11 is a diagram illustrating a configuration of a command format (2) of a drawing command.
FIG. 12 is a diagram illustrating an example of performing coordinate offset in the command format (2).
FIG. 13 is a diagram showing a configuration of a CBA.
FIG. 14 is a diagram illustrating a configuration of a TSB.
FIG. 15 is a diagram showing a format of a triangle drawing command.
FIG. 16 is a diagram illustrating a data configuration example of a triangle drawing command.
FIG. 17 is a diagram showing a format of a straight line drawing command.
FIG. 18 is a diagram showing a format of a termination code required when drawing a connection straight line.
FIG. 19 is a diagram illustrating a data configuration example of a straight line drawing command.
FIG. 20 is a diagram showing a format of a sprite drawing command.
FIG. 21 is a diagram illustrating a data configuration example of a sprite drawing command.
FIG. 22 is a diagram showing a format of a local transfer command.
FIG. 23 is a diagram illustrating a data configuration example of a local transfer command.
FIG. 24 is a diagram showing a format of a host local transfer command.
FIG. 25 is a diagram illustrating a data configuration example of a host local transfer command.
FIG. 26 is a diagram showing a format of a local host transfer command.
FIG. 27 is a diagram illustrating a data configuration example of a local host transfer command.
FIG. 28 is a diagram showing a format of a setting command.
FIG. 29 is a diagram showing a format of a mode setting command.
FIG. 30 is a diagram showing a format of a texture pattern repetition setting command.
FIG. 31 is a diagram showing a format of a clipping start and clipping end setting command.
FIG. 32 is a diagram showing a format of an offset setting command.
FIG. 33 is a diagram showing a format of a special command.
FIG. 34 is a diagram showing a format of an IRQ generation command.
FIG. 35 is a diagram showing a format of a NOP command.
FIG. 36 is a diagram showing a format of a cache flush command.
FIG. 37 is a diagram showing a format of a block write command.
FIG. 38 is a diagram illustrating a data configuration example of a block write command.
FIG. 39 is a diagram showing a pixel format.
FIG. 40 is a diagram showing a texture pattern format.
FIG. 41 is a diagram illustrating a 16-bit color format in which 4 bits / pixel and 8 bits / pixel are converted using a CLUT.
FIG. 42 is a diagram showing a format of 16 bits / pixel.
FIG. 43 is a flowchart showing a flow of processing of image information generation and image information processing applied in the system of this configuration example.
FIG. 44 is a block circuit diagram illustrating a configuration example of a conventional image creating device (home-use game machine).
FIG. 45 is a diagram used to explain an image creation method by a conventional image creation device.
[Explanation of symbols]
51 CPU
52 Peripheral device controller
53 Main memory
54 ROM
60 Graphic System
61 Geometry Transfer Engine (GTE)
62 Graphics Processing Unit
63 frame buffer
64 image decoder (MDEC)
65 Video output means (display device)
70 sound system
71 Sound Processing Unit (SPU)
72 sound buffer
73 speaker
80 Optical disk controller
81 Disk Drive Unit
82 decoder
83 buffers
90 Communication control unit
91 Communication controller
92 Controller
93 Memory card
101 Parallel I / O port
102 Serial I / O port

Claims (14)

First storage means for storing three-dimensional image data composed of a plurality of polygons;
Second storage means for storing characteristic data designated for each polygon;
Conversion means for performing a perspective transformation on the three-dimensional image data to convert it into two-dimensional image information corresponding to a display screen;
By synthesizing the above characteristics data and the two-dimensional image information, the image information generating device comprising a drawing command generation means for generating a portrayal instruction, to become a for each polygon. 2. The image information generating apparatus according to claim 1, wherein said characteristic data is a color information table. 2. The image information generating apparatus according to claim 1, wherein the characteristic data includes texture pattern information and a color information table. 2. The image information generation apparatus according to claim 1, wherein the characteristic data is translucency designation data. The transparency factor, the image information generating apparatus according to claim 4, characterized in that the predetermined multiple several.   The image information generating device according to claim 1, wherein:
  The drawing command generation means, when sequentially generating the drawing command, if the drawing content specified by the drawing command is the same as the drawing content specified by the immediately preceding drawing command, the drawing command Using the offset value from the coordinate value of the polygon drawn by the instruction
An image information generating apparatus characterized by the above-mentioned. Stores three-dimensional image data consisting of a plurality of polygons,
Stores the characteristic data specified for each polygon,
Performing a perspective transformation on the three-dimensional image data to convert it into two-dimensional image information corresponding to a display screen;
By synthesizing the above characteristics data and the two-dimensional image information, the image information generating method characterized by generating a portrayal instructions per polygon. 8. The method according to claim 7, wherein the characteristic data is a color information table. 8. The method according to claim 7, wherein the characteristic data includes texture pattern information and a color information table. 8. The image information generating method according to claim 7 , wherein the characteristic data is translucency specifying data. The transparency factor is image information generation method of claim 10, wherein that the determined multi several.   The image information generating method according to claim 7, wherein:
  When sequentially generating the drawing command, the drawing content specified by the drawing command is the same as the immediately preceding drawing command. Use the offset value from the coordinate value of the polygon drawn by the immediately preceding drawing command as the drawing command in the case where the drawing content specified in the above is the same.
An image information generation method characterized by the following. In the image information generating device according to any one of claims 1 to 6 ,
Drawing means for drawing a two-dimensional image in an image memory based on characteristic data designated by the drawing command generated by the drawing command generating means;
Supply means for reading two-dimensional image data from the image memory in synchronization with a television synchronization signal and supplying the read data to a display means;
An image information generating apparatus comprising: In the image information generating method according to any one of claims 7 to 12 ,
Drawing a two-dimensional image in an image memory based on the characteristic data specified by the generated drawing command,
An image information generating method, wherein two-dimensional image data is read out from the image memory in synchronization with a television synchronization signal and output.

Images