JP3538138B2 - Semiconductor arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor arithmetic device which holds a plurality of vectors as a data group and selects a vector which satisfies a predetermined condition corresponding to an input vector from the data group.

[0002]

2. Description of the Related Art Conventionally, analog-digital fusion processing for a single input data composed of a plurality of elements and a predetermined relationship with the input data, for example, selecting data closest to the input data from a template and outputting the selected data is performed. The present inventors have proposed a semiconductor arithmetic device that executes at a device level.

This semiconductor arithmetic device has a function similar to that of a mathematical model of a neuron.
(ΝMOS), in which a gate electrode of a normal MOS transistor is electrically floating and a number of input signals are coupled to the gate electrode via a capacitor.
The potential of the gate electrode is determined by a weighted linear sum of the input voltages, and ON / OFF is controlled by whether or not this value exceeds a threshold value of the transistor.

[0004]

By the way, not only the amount of real world data is enormous, but also vague and various disturbance factors. Specifically, taking an example of selecting an apple that best meets the desired condition from among a large number of apples, each data is configured as a vector from four elements of color, shape, size, and weight as the desired condition, Consider the case where the vector closest to the input data is selected from the templates. At this time, as a selection criterion of the vector,
If the four elements have the same importance, the simplicity is obtained. However, the importance is actually different. For example, there may be a case where the shape is regarded as the most important and the size is not so particular. Further, there may be a case where it is desired to strictly determine the weight value, or a case where the weight is important but vague conditions such as a value close to a predetermined weight are sufficient.

As described above, in order to select a data group corresponding to an actual input data group including various requirements, in the above-described configuration using νMOS, since this is a voltage operation, template matching is required. However, there is a problem that it is extremely difficult to flexibly change the calculation characteristics of.

Accordingly, the present invention provides a method of inputting input data composed of a plurality of elements as a voltage, converting the input voltage into a current, selecting data having a predetermined relationship with the input, and outputting the selected data as a current. This is a semiconductor arithmetic device that enables to select data by variably adding importance and strictness to each element constituting data, and to respond to the huge and vague requirements in the real world as much as possible. It is an object of the present invention to provide a semiconductor arithmetic device capable of doing so.

[0007]

According to the present invention, there is provided a semiconductor processing device which stores a plurality of vectors as a data group and selects a vector satisfying a predetermined condition from the data group corresponding to an input vector. An arithmetic unit that outputs a first current for at least one voltage input, wherein the first current value represents at least one maximum value or a minimum value for a predetermined input voltage value. A first circuit having at least one circuit to take, a second circuit that controls a potential of an output terminal of the first current in the first circuit to a predetermined value, and outputs a second current; A circuit which receives a second current or a current obtained by summing a plurality of second currents as one input current, and has a function of specifying a maximum value or a minimum value among the plurality of input currents. 3 circuits Ete constructed.

In one aspect of the semiconductor arithmetic device of the present invention, the second circuit or the third circuit is provided between the second circuit and the third circuit with respect to a current obtained by summing a plurality of the second currents. A fourth circuit that generates a third current having a predetermined relationship, wherein the third circuit uses the third current or a current obtained by summing a plurality of the third currents as one input current receive.

In the following description of the embodiments of the invention, for convenience, the third circuit (current) is referred to as a fourth circuit (current), and the fourth circuit (current) is referred to as a third circuit (current). Current).

In one embodiment of the semiconductor arithmetic device according to the present invention, each of the circuits constituting the first circuit is a circuit in which an nMOS transistor and a pMOS transistor are connected in series or in parallel.

In one aspect of the semiconductor arithmetic device of the present invention, each of the circuits constituting the first circuit is a MOS transistor, and is a quantum effect device having a tunnel barrier between a source channel and a drain channel. is there.

In one aspect of the semiconductor arithmetic device of the present invention, the first circuit is a circuit arranged in rows and columns in a matrix, and each row corresponds to each vector constituting the data group. Each column is set so as to correspond to each element of the vector.

In one aspect of the semiconductor arithmetic device of the present invention, the second circuit is added to each of the first circuits.

In one aspect of the semiconductor arithmetic device of the present invention, the fourth circuit is added to each of the first circuits.

In one aspect of the semiconductor arithmetic device of the present invention, the second circuit has a voltage input terminal for controlling a potential of an output terminal of the first current to a predetermined value. Signals applied to the terminals are shared by a common signal line for each column.

In one aspect of the semiconductor arithmetic device of the present invention, the second circuit is provided for each column of the first circuit.

In one aspect of the semiconductor arithmetic device of the present invention, the first circuit is provided with means for varying the sharpness of a voltage-current characteristic function centered on the maximum value or the minimum value. .

In one aspect of the semiconductor arithmetic device of the present invention, the variable means has a linear amplifier circuit at an input terminal of each of the circuits constituting the first circuit, and an input voltage is applied to the linear amplifier circuit. The output is input to the input terminal of each circuit.

In one aspect of the semiconductor arithmetic device of the present invention, the variable means is a variable-capacitance capacitor for returning the output of each of the circuits constituting the first circuit.

In one embodiment of the semiconductor arithmetic device according to the present invention, the third circuit includes a plurality of transistors having the same conductivity type, and can apply a common reference voltage to all of the gate electrodes. The drain terminal of each transistor is a voltage output terminal.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a schematic diagram showing a main configuration of a semiconductor processing device according to a first embodiment. This semiconductor arithmetic device is a device that holds a plurality of vectors composed of a large number of elements as a template, selects a vector that satisfies a predetermined condition corresponding to an input vector from the template, and outputs the selected vector. In the present embodiment, when the input vector X is composed of n elements,
That is, X = (x ₁ , x ₂ ,..., X _n ).
An example in which the number of templates is m, which is composed of dimensional vectors, will be described.

Here, the semiconductor arithmetic device is a current-driven semiconductor circuit in which each element of an input vector is input as a voltage value, and an arithmetic operation for selecting a vector satisfying a predetermined condition is performed using a current. The output is a digital signal that identifies the selected vector. This is a circuit that specifies a template vector that satisfies a predetermined condition, for example, by setting a digital value flag ("0" or "1" bit) at the position of the selected vector.

More specifically, the semiconductor arithmetic device is a circuit for outputting a first current in response to at least one voltage input, wherein the first current value is at least one for a predetermined input voltage value. A first circuit 1 having a plurality of circuits having a maximum value (or a minimum value), and a second circuit for controlling a potential of an output terminal of a first current in the first circuit 1 to a predetermined value and outputting a second current. A second circuit 2, a third circuit 3 that generates a third current having a predetermined relationship with the second current, and a circuit that receives the third current as one input current. A fourth circuit 4 which is a so-called Wiener Take All (WTA) circuit having a function of specifying a maximum value (or a minimum value) from input currents.

As shown in FIG. 2, the first circuit 1 is a voltage-current conversion circuit in which a plurality of (m × n) CMOS inverters 11 are arranged in a matrix of m rows and n columns.
The input voltage x _k (k = 1 to n) is commonly applied to the input terminals of the CMOS inverter 11 for each column. Here, each CMOS inverter 11 has a pMO
The S transistor and the nMOS transistor are connected in series, and are connected such that the nMOS transistor is grounded.

In the first circuit 1, n constituting each row
The CMOS inverters 11 form m templates T _{1 to} T _{m as} described below. That is, FIG.
As shown in FIG.
Generates an output current I having the characteristics shown in FIG. Since the V-I characteristic is non-linear function having a maximum value, x _1, x ₂ for each row, ..., the maximum current value I _max to the CMOS inverter 11 corresponding to x _n the threshold voltage V _T, respectively Set it to the desired value.

Note that, instead of each CMOS inverter 11, as shown in FIG. 4, an inverting amplifier 14 may be provided so that an inverted signal is applied to the gate electrode. The inverting amplifier 14 may be configured using, for example, an operational amplifier, or may use an inverter.

[0028] Setting of the threshold voltage V _T, for example is suitable to the following procedures.

First, a method for temporarily storing a template
As a method, as shown in FIG.
1, a capacitor 13 is arranged in the preceding stage, and a CMOS inverter
The output of the capacitor 11 and the CMOS inverter 11
There is a way to regress between According to this,
The voltage between the inverter 13 and the CMOS inverter 11 is
Low voltage V_TAnd the output of the CMOS inverter 11 is
The voltage input to node 13 'as it is regressed
Value V_TEMPLATEAnd cut the signal regression path. This
This causes the amount of charge stored at both ends of the capacitance to
Adjusted, V_{TEM PLATE}Is the apparent threshold of this whole circuit
It can be.

Next, as a method of semi-permanently storing a template, there is a method of providing a CMOS inverter 11 with a floating gate and providing a nonvolatile memory-like configuration as shown in FIG. According to this, it is possible to arbitrarily set the threshold voltage V _T by the floating gate flow into electrons and holes in or to the floating gate to flow out electrons and holes. As a method of realizing this, for example, a hot electron (hole) injection phenomenon, a tunnel phenomenon, or the like may be used.

The second circuit 2 is an nMOS transistor functioning as a so-called cascode, and the first circuit 1
, One for each row. These nMOS
By controlling the gate voltage V _{GG of the} transistor to a predetermined value, each CMOS inverter 11 in the corresponding row is controlled.
The potential of the output terminal is fixed to a predetermined value, the maximum current value I _max of each CMOS inverter 11 is fixed to a predetermined value.

The third circuit 3 is a so-called current mirror circuit that generates an output current having a value proportional to the input current. With this arrangement, the current from the second circuit 2 can be stably supplied to the fourth circuit. In this example, a current mirror circuit based on a diode bias method is illustrated as shown in FIG.

The fourth circuit 4, as shown in FIG. 7 (c), selecting the one of the largest value of m multiple current I ₁ ~I _m to enter, specifies the selected vector a circuit, each one nMO corresponding to the current I ₁ ~I _m
It has an S transistor 12.

In the fourth circuit 4, the reference voltage V _REF is commonly applied to the gate electrodes of the nMOS transistors 12, and the drain terminals (output terminals 13 _{(1) to} 13 _{(m) ) of the} nMOS transistors 12 are applied. ), the corresponding current I ₁ ~I _m is input. Next, the reference voltage
V _REF is monotonously reduced with time as shown in FIG. In this case, there is no need to be linear, and a monotonous decreasing function as shown in FIGS. 8B and 8C may be used. nMO
Current drive capability of S transistor 12 (output terminal 13 ₍₁₎
13 The ability to be pull out the charges of _(m)) is determined by the reference voltage V _REF, towards the reference voltage V _REF is high is higher current driving capability. Assuming that the driving capabilities of the respective nMOS transistors are I ₁ ′ to I _m ′, while the reference voltage V _REF is high, I ₁ ′> I ₁ , I ₂ ′> I ₂ ,..., _Im ′> I _m Therefore, the currents I _{1 to} I _m input to the nMOS transistor 12 are
Are all pulled out to the ground terminal, and the output terminals 13 _{(1) to} 13
_(m) is kept at 0V.

[0035] Here, the maximum current in the inside of the I ₁ ~I _m I _k
(1 <= k <= m). When the reference voltage V _REF decreases, n
When the current drive capability of the MOS transistor 12 decreases and I _k ′ <I _k , only the output terminal 13 _(k) is inverted from the digital value “0” to “1”. Further, by further lowering the reference voltage V _REF , the output terminal 13 to which the second and third largest currents are input is sequentially inverted from “0” to “1”. It is possible to detect the largest current in the I ₁ ~I _m by providing a circuit 14 for storing whether signals which output terminal is initially inverted to the next stage. It is also possible to further separate the signals of "0" and "1" using an amplifier such as an inverter, and to invert from "0" to "1" or to invert from "1" to "0". It is also possible to choose whether to do so.
The circuit 14 can be implemented by, for example, a combination of a multi-input OR circuit and a register circuit (FIG. 7A) or a time difference comparison circuit using a flip-flop (FIG. 7B).

Here, the operation of the semiconductor arithmetic device will be described.

First, a vector X = n composed of n elements
(X ₁ , x ₂ ,..., X _n ) as input data, and each element x ₁ ,
x ₂ ,..., x _n are input voltages corresponding to the 1st to _nth columns constituting the first circuit 1 and the CMOS inverters 11 of the respective columns.
Is applied.

[0038] In this case, k columns (k = 1 to n) in each of the CMOS inverter 11 constituting the first in response to the V-I characteristic curve which the maximum value the threshold voltage V _T of each of the templates Generate and output current. Then, the output currents of the n CMOS inverters 11 are added to each of the series-connected rows to become respective currents I _k (k = 1 to n), which are output from the first circuit 1.

Each of the currents I _k is converted into a second current through the second circuit 2, further converted into a third current through the third circuit 2, and input to the fourth circuit 4. This fourth
In the circuit 4, by the function of the WTA described above, it is detected current of the largest value among the current I ₁ ~I _m, so that the template is specified.

As described above, according to the semiconductor computing device of the present embodiment, input data composed of a plurality of elements is input as a voltage, the input voltage is converted into a current, and the input data is most evaluated value. Data having a high (similarity) is selected from the templates T _{1 to} T _m , and a signal specifying the template vector is set to “0” or “
It is possible to output with a flag of "1".

-Modifications- Various modifications of the semiconductor arithmetic device according to the first embodiment will be described below.

(Modification 1) In this example, as shown in FIG. 9, instead of each CMOS inverter 11, circuits 21 each having a pMOS transistor and an nMOS transistor connected in parallel are arranged in a matrix. The first circuit 1 is configured.

In this case, the VI characteristics of each circuit 21 are as shown in FIG.
As shown in FIG. _TAnd the minimum current value I_min
Is obtained. Therefore, this CMOS inverter 2
1 constitutes the first circuit 1, the input vector X
= (X₁, X_Two, ..., x_n) As the vector closest to
Style I₁~ I_mThe current with the smallest value is selected from
Therefore, the current I₁~ I_mThe smallest value among
Needs to be configured to select the current.

In order to realize this, in the circuit shown in FIG. 7, a voltage that monotonically increases with time may be applied instead of a voltage that monotonically decreases with time. At this time, the output terminal 13 sequentially inverts from "1" to "0". To realize this, for example, the signal of the output terminal 13 is inverted, and a circuit in which a multi-input OR circuit and a register are combined is connected to a connection circuit (FIG. 11A) or the multi-input
A circuit in which a circuit combining a NAND circuit and a register is connected (FIG. 11B), a flip-flop (FIG. 11C)
And so on.

Incidentally, the second to fourth circuits other than the CMOS inverter constituting the semiconductor arithmetic device of the first embodiment are as follows.
As shown in FIG. 12, it can be configured to detect what nMOS, the current of largest value from among ... current I ₁ ~I _m as well by inverting the pMOS logic flows .

Also in the semiconductor arithmetic device of this example, similarly to the first embodiment, input data composed of a plurality of elements is input as a voltage, the input voltage is converted into a current, and the input data is most similar to the input data. Template T ₁ with high degree of data
~ _Tm , and a signal specifying the template can be output by a digital "0" or "1" flag.

(Modification 2) In this example, the first circuit 1 is configured by arranging quantum effect devices 22 in a matrix instead of each CMOS inverter 11.

In the quantum effect device 22, as shown in FIG. 13, a gate electrode 33 made of a polycrystalline silicon film is pattern-formed on a Si semiconductor substrate 31 via a gate insulating film 32 made of a silicon oxide film. A source 34 and a drain 35 are formed on the surface layer of the semiconductor substrate 31 on both sides of the source substrate 33 by ion implantation.
And the semiconductor substrate 31 and between the drain 35 and the semiconductor substrate 31, respectively.

As shown in FIG. 14, the VI characteristic of the quantum effect device 22 becomes a curve having a maximum value as shown in FIG. 14 due to the resonance characteristic due to the provision of the silicon oxide film 36. In this example, the first circuit 1 is configured similarly to the CMOS inverter 11 using this characteristic.

According to the semiconductor computing device of this embodiment, in addition to the effects of the semiconductor computing device of the first embodiment, the same characteristics as those of the CMOS inverter can be obtained by a single device. As the device is miniaturized, the quantum effect becomes more remarkable and the characteristics become more prominent, which contributes to miniaturization and miniaturization of the device.

(Second Embodiment) Next, a second embodiment of the present invention will be described. FIG. 15 is a schematic diagram showing a main configuration of the first to third circuits in the semiconductor arithmetic device of the present embodiment.

In this embodiment, a predetermined element is weighted among the elements of the input vector X = (x ₁ , x ₂ ,..., X _n ) as the input data. Specifically, the second circuit 2 is provided for each CMOS inverter 11 constituting the first circuit.
_Are applied, and V _{GG1 to} V _GGn are applied so that the gate voltage is common to each column. Here, the desired element (input voltage) x _k can be weighted by adjusting the gate voltage V _GGk of the CMOS inverter 11 in the desired column (k column) to be larger or smaller than the other columns. it can.

With this configuration, for example, if the description in the section of the problem to be solved by the invention is cited, when selecting an apple that best meets desired conditions from a large number of apples, the color, shape, and size are selected. Of the four elements of weight, when the shape is particularly important, if an element x _k corresponding to the shape is weighted as described above, an optimal template having a high degree of importance for the shape will be selected.

[0054] In fact, to prepare a semiconductor computing device of the present embodiment, when it tries to change the gate voltage V _GG of the second circuit 2 connected to the CMOS inverter 11, as shown in FIG. 16, V _GG maximum current value I _max corresponding to the size
Changed to such an extent that it could be judged sufficiently. It should be noted that in this case, 5, by the method described with reference to FIG. 6, it is of course possible to adjust the threshold voltage V _T.

The second circuit 2 has the effect of not only performing weighting but also fixing the output terminal potential of the first circuit 1 to a predetermined potential. In particular, when a quantum effect device is used, when the voltage between the source and the drain changes, the quantum state is broken, and the operation characteristics themselves change. For this reason, adding a cascode transistor and fixing the potential exerts an unprecedented great effect in this semiconductor arithmetic device.

As described above, according to the semiconductor arithmetic device of the present embodiment, input data composed of a plurality of elements is input as a voltage, the input voltage is converted into a current, and data closest to the input data is converted into a template. When selecting from T _{1 to} T _m and outputting as a current with a relatively simple configuration, it is possible to select data by finely and variably adding importance to each element constituting data. It is possible to respond as much as possible to the vast and vague requirements in the real world.

-Modification- Here, a modification of the semiconductor arithmetic device according to the second embodiment will be described. In this example, as shown in FIG.
For each CMOS inverter 11 constituting the first circuit,
Not only the nMOS transistor, which is the second circuit 2,
A third circuit 3, which is a current mirror circuit, is also provided.

With this configuration, in addition to various effects achieved by the semiconductor arithmetic device according to the second embodiment, the output current of each CMOS inverter 11 can be extremely stabilized.

(Third Embodiment) Next, a third embodiment of the present invention will be described. FIG. 18 is a schematic diagram showing a main configuration of the first to third circuits in the semiconductor arithmetic device of the present embodiment.

In the present embodiment, of the elements of the input vector X = (x ₁ , x ₂ ,..., X _n ) as input data, the VI characteristic curve of the CMOS inverter 11 corresponding to a predetermined element is obtained. (Half value) width, that is, the sharpness of the curve is changed.

More specifically, each CM constituting the first circuit
A variable capacitor 41 is provided for each OS inverter 11.
The variable capacitor 41, for example the sharpness of the operational characteristics 2 ⁿ kinds Taking as an example the case of preparing n capacitors the capacitance ratio 1,2,4, ..., constituted by n 2 ^n, respective conductive Two switches 42 are provided on the film so that Vin can be applied to each of these conductive films. In this case, Vin is applied to one switch 42 and the output of the CMOS inverter 11 is returned to the other switch 42. By selecting only one of the switches 42 connected to one conductive film, the voltage Vin
And the ratio of the regression voltage Vfb. Vin: Vfb = 2 ⁿ -1: 0 ~
0: can be variable up to 2 ⁿ -1. For example, Vin = n = 4
If a ratio of Vfb = 12: 3 is configured, a switch may be set so that Vin is applied to the conductive film having an area ratio of 4,8 and the regression voltage Vfb is applied to the conductive films of 1,2. . When two switches 42 connected to a conductive film are not turned on at the same time, when both switches are turned off, the effect of the conductive film can be ignored, so that Vin: Vfb = p: q (p + q <2 ⁿ ,
The ratio between an arbitrary voltage Vin and a return voltage Vfb satisfying (p and q are natural numbers) is obtained.

Actually, when the semiconductor arithmetic device of the present embodiment was fabricated and V _in : V _fb was changed by the variable capacitor 41 and the switch 42 connected to the CMOS inverter 11, as shown in FIG. It was found that the sharpness changed to an extent that it could be judged sufficiently.

As a second method for changing the sharpness of the characteristic curve, as shown in FIG.
A linear amplifier 42 having a variable gain (amplification degree) is provided for each OS inverter 11. The linear amplifier 42 includes, for example, a linear amplifier using an operational amplifier, resistance division of a voltage by a variable resistor, and capacitance division of a voltage by a variable capacitor.

In the circuits shown in FIGS. 18 and 20 (a),
Although only a method for making the sharpness more gentle is described, as shown in FIG. 20B, it is possible to make the sharpness even more by connecting CMOS inverters in series.

As described above, according to the semiconductor processing device of the present embodiment, input data composed of a plurality of elements is input as a voltage, the input voltage is converted into a current, and data closest to the input data is converted into a template. When selecting from T _{1 to} T _m and outputting as a current with a relatively simple configuration, it is possible to select data by finely and strictly adding strictness to each element constituting data. It is possible to respond as much as possible to the vast and vague requirements in the real world.

The present invention is not limited to the first to third embodiments. For example, the configuration of the third embodiment is added to the configuration of the second embodiment, that is, for each CMOS inverter 11 (each element x _k of the input vector X) constituting the first circuit 1, weighting and sharpness are added. Or the configuration of the third embodiment is added to the configuration of the modified example of the second embodiment, that is, each C constituting the first circuit 1 is changed.
For each MOS inverter 11 (each element x _{k of} input vector X)
In each case, it is preferable that the sharpness is changed together with the weighting, and the output of each third circuit 3 is stabilized.

[0067]

According to the semiconductor arithmetic device of the present invention, input data composed of a plurality of elements is input as a voltage, the input voltage is converted into a current, and data having a predetermined relationship with the current is selected. Output as a current.

Further, it is possible to select data by variably adding importance and strictness to each element constituting the data, and it is possible to respond to the huge and vague requirements in the real world as much as possible. Become.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating a main configuration of a semiconductor processing device according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating a first circuit that is a component of the semiconductor arithmetic device according to the first embodiment;

FIG. 3 is a VI characteristic diagram of each CMOS inverter constituting the first circuit.

FIG. 4 is a schematic diagram showing another example of each circuit constituting the first circuit.

FIG. 5 is a schematic diagram showing a configuration example for temporarily storing a template.

FIG. 6 is a schematic diagram showing a configuration example of storing a template semi-permanently.

FIG. 7 is a schematic diagram illustrating a fourth circuit that is a component of the semiconductor arithmetic device according to the first embodiment;

FIG. 8 is a characteristic diagram illustrating a temporal change of a reference voltage in a fourth circuit which is a component of the semiconductor arithmetic device according to the first embodiment;

FIG. 9 is a schematic diagram illustrating each CMOS inverter forming a first circuit of Modification Example 1 of the semiconductor arithmetic device according to the first embodiment;

FIG. 10 shows each CMOS constituting the first circuit of the first modification.
It is a VI characteristic diagram of an inverter.

FIG. 11 is a schematic diagram showing another example of a circuit constituting the first circuit of the first modification.

FIG. 12 is a schematic diagram showing still another example of the circuit configuring the first circuit of the first modification.

FIG. 13 is a cross-sectional view illustrating a main configuration of each quantum effect device included in a first circuit of Modification Example 2 of the semiconductor arithmetic device according to the first embodiment.

FIG. 14 is a VI characteristic diagram of each quantum effect device included in the first circuit of Modification Example 2.

FIG. 15 is a schematic diagram showing a main configuration of first to third circuits in a semiconductor arithmetic device according to a second embodiment of the present invention.

FIG. 16 is a characteristic diagram showing an experimental result obtained by examining a relationship between a gate voltage V _GG and a maximum current value I _max by the manufactured semiconductor arithmetic device of the second embodiment.

FIG. 17 is a schematic diagram showing first to third circuits of a modified example of the semiconductor arithmetic device according to the second embodiment;

FIG. 18 is a schematic diagram showing a main configuration of first to third circuits in a semiconductor processing device according to a third embodiment of the present invention.

FIG. 19 is a characteristic diagram showing an experimental result obtained by examining a relationship between V _in : V _fb and sharpness by the manufactured semiconductor arithmetic device of the third embodiment.

FIG. 20 is a schematic diagram showing another example of the third embodiment of the present invention.

[Explanation of symbols]

1 First circuit 2 Second circuit 3 Third circuit 4 Fourth circuit 11,14,212 CMOS inverter 12nMOS transistor 13 Capacitor 21 circuits 22 Quantum Effect Devices 31 Si semiconductor substrate 32 Gate insulating film 33 Gate electrode 34 sources 35 drain 36 Silicon oxide film 41 Variable capacitor 42 switch

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06G 7/60

Claims (13)

(57) [Claims] 1. A semiconductor processing device which holds a plurality of vectors as a data group and selects a vector satisfying a predetermined condition from the data group corresponding to an input vector, wherein at least one voltage input is A first circuit for outputting a first current to the first circuit, the first circuit having at least one circuit in which the first current value takes at least one local maximum value or a local minimum value for a predetermined input voltage value; A second circuit that controls a potential of an output terminal of the first current in the first circuit to a predetermined value and outputs a second current; and the second current or a plurality of the second currents And a third circuit having a function of specifying a maximum value or a minimum value from among the plurality of input currents. Semiconductor computing device. 2. A third current having a predetermined relationship between the second circuit and the third circuit with respect to the second current or a current obtained by summing a plurality of the second currents. And a third circuit for generating the third current or a plurality of the third currents.
2. The semiconductor arithmetic device according to claim 1, wherein a current obtained by summing the currents is received as one input current. 3. The semiconductor according to claim 1, wherein each of the circuits constituting the first circuit is a circuit in which an nMOS transistor and a pMOS transistor are connected in series or in parallel. Arithmetic unit. 4. The device according to claim 1, wherein each of the circuits constituting the first circuit is a single MOS transistor, and is a quantum effect device having a tunnel barrier between a source channel and a drain channel. Or the semiconductor arithmetic device according to 2. 5. The first circuit is a circuit arranged in rows and columns in a matrix, wherein each row corresponds to each vector constituting the data group, and each column corresponds to each vector of the vector. The semiconductor arithmetic device according to claim 1, wherein the semiconductor arithmetic device is provided so as to correspond to the elements. 6. The semiconductor arithmetic device according to claim 5, wherein said second circuit is added to each of said first circuits. 7. The semiconductor arithmetic device according to claim 1, wherein said fourth circuit is added to each of said first circuits. 8. The second circuit has a voltage input terminal for controlling a potential of an output terminal of the first current to a predetermined value, and a signal applied to the input terminal is provided for each column. 8. The semiconductor arithmetic device according to claim 6, wherein the semiconductor arithmetic device is shared by a common signal line. 9. The semiconductor arithmetic device according to claim 5, wherein said second circuit is provided for each column of said first circuit. 10. The apparatus according to claim 5, wherein said first circuit is provided with means for varying the sharpness of a voltage-current characteristic function centered on said maximum value or said minimum value. 10. The semiconductor arithmetic device according to any one of items 9 to 9. 11. The variable means has a linear amplifier circuit at an input terminal of each of the circuits constituting the first circuit, an input voltage is applied to the linear amplifier circuit, and an output is input to each of the circuits. 11. The semiconductor arithmetic device according to claim 10, wherein the input is made to a terminal. 12. The semiconductor computing device according to claim 10, wherein said variable means is a variable-capacitance capacitor for regressing an output of each of said circuits constituting said first circuit. 13. The third circuit is composed of a plurality of transistors having the same conductivity type, a common reference voltage can be applied to all of the gate electrodes, and a voltage output terminal of each transistor is output. 13. The semiconductor arithmetic device according to claim 1, wherein the semiconductor arithmetic device is a terminal.