JP3537228B2 - Wireless communication base station - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a base station for wireless communication such as mobile communication. In particular, the present invention relates to a radio communication base station including an amplifier that corrects the amplitude and phase of a transmission signal and performs amplification with less distortion.

[0002]

2. Description of the Related Art In recent years, in a radio communication apparatus for mobile communication or the like, a signal of a plurality of carriers is commonly subjected to power amplification in a radio frequency domain due to a tendency of high speed and high multiplexing of signal transmission. As such a power amplifier, a power amplifier having good linearity is desired in order to suppress deterioration of transmission characteristics.

[0003] A power amplifier having good linearity is characterized by a large scale, a large power consumption, and a high price, assuming, for example, a feedforward system. On the other hand, if the distortion of the power amplifier can be compensated for by digital signal processing, the possibility of small size, low cost, and high power efficiency will be opened.

However, A / D and D / A converters are indispensable. Further, A / D and D / A converters having a sufficient operation speed and a required accuracy (number of bits) are still difficult to obtain. For this reason, the upper limit of the output and input frequencies is about several tens of MHz. Frequency conversion is required for use in higher frequency bands.

[0005]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an image rejection type frequency converter for an up-converter and a down-converter when such frequency conversion is required, thereby suppressing unnecessary sidebands. It is an object of the present invention to provide a wireless communication base station provided with an amplifier that facilitates and increases the handling power by 3 dB, particularly a small wireless communication base station suitable for mobile communication.

Further, a 90-degree phase shifter is required for an image rejection type frequency converter, but it is difficult to manufacture a passive circuit if the fractional band is large. Therefore, an object of the present invention is to provide the wireless communication base station which can be easily created by a digital signal circuit.

Further objects of the present invention will become apparent from the embodiments of the present invention described below with reference to the drawings.

[0008]

According to the present invention, a radio communication base station comprises a transmitting / receiving antenna, a high-frequency power amplifier for amplifying a transmission signal radiated from the transmitting / receiving antenna, and an output of the high-frequency power amplifier. A / D converter for converting the digital signal into a digital signal, a digital transmission signal provided on the input side of the high-frequency power amplifier, and the A / D converter
A radio communication base station having a linearization circuit that corrects the amplitude and phase of a transmission signal so as to reduce the difference obtained by comparing with the output of the converter and performs amplification with less distortion. I do.

Further, as a feature, an image rejection type frequency upconverter provided between the linearize circuit and the high frequency power amplifier is provided. The image rejection type frequency upconverter outputs the output of the linearize circuit by 90 °. A first phase shift circuit for shifting the phase, a first D / A conversion circuit for D / A converting the output of the phase shift circuit, and a D / A conversion for directly outputting the output of the linearize circuit.
The outputs of the second D / A conversion circuit for A / A conversion, the first D / A conversion circuit and the second D / A conversion circuit are I and Q, respectively.
The first D /
There are first and second mixing circuits for mixing with an oscillation signal having a higher frequency than the output of the A-conversion circuit and the second D / A conversion circuit.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or similar components will be described with the same symbols or reference numerals.

Before describing the embodiments of the present invention, the position of the present invention and the configuration of distortion correction by a digital signal processing circuit as a premise of the present invention will be described.

FIG. 1 is a diagram for explaining the positioning of the present invention. An example of a wireless communication base station targeted by the present invention,
An optical multiplexed signal connected to the public communication network 0 and transmitted from the public communication network 0 is transmitted to a DSU (Digit)
al Service Unit) 1 is terminated.

[0013] The optical multiplexed signal terminated by the DSU 1 is converted into an electric signal here and input to the MUX / DMUX unit 2. Demultiplexed by MUX / DMUX unit 2, TDM
Antenna 5 via A section 3, modem section 4 and radio frequency section 5
Sent from 3 The modem unit 4 includes a collective modulation unit 40 that collectively modulates a plurality of channels for a signal in a downstream direction (a direction toward the antenna 53) and a D / A converter 41 that converts the output of the collective modulation unit 40 into an analog signal. Have.

The analog output of the D / A converter 41 is amplified by the power amplifier 50 of the radio frequency section 5 and
3 is output. Here, the collective modulation section 40 further has a linearize function of giving a correction value to the signal in advance for the distortion of the power amplifier 50 to cancel the distortion.

The magnitude of the correction value by the linearize function is determined by feeding back part of the output of the power amplifier 50 and referring to the level of the feedback signal. Further, since this linearization function is processed digitally, it has an A / D converter 42 for converting an analog signal which is a part of the output of the power amplifier 50 into a digital signal.

On the contrary, the radio frequency signal in the upward direction received by the antenna 53 is branched by the branching circuit 52 and input to the low noise amplifier 51. The signal amplified here is converted into a digital signal by the A / D converter 44, and the signals of a plurality of channels are demodulated collectively by the demodulation unit 43.

Then, the TDMA unit 3, MUX / DMUX
Through the unit 2 and the optical DSU unit 1, the signal is processed in the opposite direction to the above-mentioned signal in the down direction (the direction toward the antenna 53) and sent to the public communication network 0.

In FIG. 1, CCU 6 is a MUX / DM
UX section 2, TDMA section 3, batch modulation section 40 / demodulation section 4
3 to supply a clock and control the operation timing.

FIG. 2 further explains the premise of the present invention. In the configuration of FIG. 1, a more detailed configuration block mainly including the collective modulation section 40 of the modem section 4 after the MUX / DMUX section 2 is described. The figure is shown. The configuration corresponding to the TDMA unit 3 is omitted.

In FIG. 2, reference numeral 400 denotes a collective modulation unit 40.
Is a transmultiplexer as a group modulator. For a plurality of carriers, a carrier signal oscillator 41
2, the circuit includes an I and Q signal generation circuit 410 and a modulation circuit 411. The transmultiplexer generates a plurality of carriers by digital signal processing (for example, FF).
Analog oscillators and modulators are not required (using T, etc.)
Although the output is a digital signal, the figure schematically shows an analog system.

The output of the transmultiplexer 400 is
The signal is input to a linearize circuit 402 which is a part of the batch modulation section 40.

FIG. 2 shows only the linearizing circuit 402 in the downward direction toward the antenna 53, and FIG.
In FIG. 7, a radio frequency conversion circuit (up converter) 406 and a radio frequency inverse conversion circuit (down converter) 407 are shown.

The linearize circuit 402 has a digital signal processing circuit 403 and a comparator 404. The delay circuit 405 adjusts the processing time of the digital signal processing circuit 403. The comparison circuit 404 includes a delay circuit 405
And the output of the down-converter 407 are converted into a digital signal by the A / D converter 42, and the amplitude and the phase are compared.

The digital signal processing circuit 403 functions to apply a compensation distortion to the input signal in advance so as to compensate for the distortion of the power amplifier 50 based on the comparison result of the comparison circuit 404. The present invention relates to such a digital signal processing circuit 403.
Is premised on the assumption that the operation speed of the A / D converters 401 and 42 and the D / A converter 41 has an upper limit of several tens of MHz.

FIG. 3 is a block diagram showing a first embodiment of the present invention, in which only a linearize circuit 402 is extracted and an additional circuit added to the linearize circuit 402 according to the present invention is provided. are doing.

As described above, in the configuration of FIG. 2, frequency conversion is required so that the output frequencies of the A / D converters 401 and 42 and the D / A converter 41 have an upper limit of several tens of MHz. Therefore, in the present invention, the up-converter 4
An image rejection type is used for the down converter 06 and the down converter 407, so that unnecessary sidebands can be easily suppressed, and the handling power can be increased by 3 dB to suppress distortion.

However, when an image rejection type frequency converter is used, a 90-degree phase shifter is required.
In FIG. 3, the up converter 406 is composed of up converters 416 and 426. Upconverter 41
The output of the digital signal processing circuit 403 is input to 6 through a 90-degree phase shifter 418 and a D / A converter 417.
On the other hand, the D / A converter 42
7, the output of the digital signal processing circuit 403 is input.

Here, it is difficult to configure the 90-degree phase shifter 418 as a passive circuit if the fractional band is large. It is easy if it is composed of digital circuits. Therefore, in the present invention, the 90-degree phase shifter 418 is constituted by a digital processing circuit, and the I and Q signals are converted into D / A converters 417 and 427, respectively.
, An analog signal is obtained, and input to the image rejection type upconverters 416 and 426.

In FIG. 3, the outputs of the image rejection type up converters 416 and 426 are input to the power amplifier 50 after unnecessary waves are removed by a filter 419 in common.

Reference numeral 408 denotes a local signal oscillator having a phase difference of 90 degrees.
16, 426 and the carrier signal input to the down converter 407.

FIG. 4 shows an example of the configuration according to the present invention of a digital signal processing circuit (hereinafter referred to as a linearizer if necessary) 403 constituting the linearize circuit 402.

The linearizer 403 is constructed by the present inventors using a least squares method (LMS) algorithm. Now, in FIG. 4, the distortion function of the power amplifier 50 is considered as f (p). A memory 140 stores an estimated distortion compensation coefficient h (p) for the distortion function f (p) of the power amplifier 50.

Further, 142 to 145 are multipliers, and 146 is an adder. 141 is an input baseband signal x
The (t) absolute value conversion circuit 147 is a circuit for obtaining a conjugate value with respect to the output of the A / D converter 42. Here, the comparator 404 is configured by a subtractor that outputs a difference between both inputs as a subtractor.

According to the configuration shown in FIG.
The following equation 1 is realized. Note that in Equation 1, x
(T) is an input baseband signal, f (p) is a distortion function of a power amplifier, h (p) is an inference compensation coefficient, and μ is a step size parameter. Further, x, y, f, h, u, e
Represents a complex number and * represents a conjugate complex number.

[0035]

(Equation 1)

U (t) is h _n-1 (p) h ^* _n-1 (p) ≒ 1 where the amplitude distortion of the power amplifier 50 is not so large.
Approximate assuming

FIG. 5 is a diagram showing the 90-degree phase shifter 418 in FIG.
FIG. 3 is a block diagram illustrating a configuration example of FIG. In FIG. 5A, 90
The Qch signal is input to the phase shifter 418. on the other hand,
On the Ich signal side, a delay circuit 54 for adjusting the delay time by the 90-degree phase shifter 418 is inserted to match the delay of the I and Q signals.

The 90-degree phase shifter 418 is basically composed of a transversal filter. Reference numeral 55 denotes a transversal filter delay circuit, which is constituted by a shift register. The output of each stage of the shift register 55 is input to a multiplier 561～56N, it is respectively multiplied by weighting coefficients _{a 1, a 2 ·· a n} .

The weighting coefficients a _1, a ₂ ·· a _n is 5
(B) is determined. H (ω) is −f _s / 2
During the _{f s / 2, π / 2~} -π / 2 is a function of phase shift, in the band 58 required, weighting coefficients a _1, as the number 2 of the function h (t) can be, a ₂ · · a _n is chosen.

[0040]

(Equation 2)

FIG. 6 is a configuration example of the image suppression type up-converters 416 and 426. Note that the down converter is similarly configured only by reversing the input direction.

In FIG. 6A, the image suppression type up-converters 416 and 426 include a pair of double balance type modulators 60 and 61 and 90 degree phase shifters 62 and 63. As an example, 100 is added to the 90-degree phase divider 62.
The signal of Mz is input. The 90-degree phase shifter 62 generates signals having a phase difference of 90 degrees from each other, and the signals are input to the double balance type modulators 60 and 61.

In the double balance type modulators 60 and 61, the 1 GHz carrier is output from the 1 GHz carrier signal oscillator 64, multiplied by the output of the 90-degree phase shifter 62, mixed by the 90-degree phase mixer 63, and output. Is done.

FIG. 6B is a diagram showing a frequency spectrum in the above configuration. 100MHz signal is 1
Only the upper band USB mixed with the GHz signal is output from the 90-degree phase mixer 63.

FIG. 7 shows double balance type modulators 60 and 6.
This is an example of the configuration of Example 1, which includes diodes D1 to D4 and transformers T1 and T2 with intermediate taps. The carrier from the carrier signal oscillator 64 is input to the primary side of the transformer T1. Further, an IF signal between the intermediate taps of the modulators 60 and 61, that is,
In the example of FIG. 6, a signal of 100 MHz is input.

From the output OUT of the modulator 61, FIG.
As shown in (B), upper and lower band waves LSB and USB are output. As described above with reference to FIG.
The outputs of 0 and 61 are input to a 90-degree phase mixer 63 and mixed with a 90-degree phase difference from each other. As a result, the lower band LSB shown in FIG. 7B is canceled, and only the upper band is output.

FIG. 8 shows a second embodiment of the present invention. The circuit of the down converter 407 (see FIG. 2) for the downstream signal transmitted from the antenna 53 through the duplexer 52 is the same as that of FIG. According to the principle described above, the image suppression converters 507 and 517 are used.

Therefore, the 90-degree phase shifter 529 to which the output of the A / D converter 528 is guided is configured as a digital processing circuit as shown in FIG.

FIG. 9 shows a third embodiment of the present invention, in which the configurations shown in FIGS. 3 and 8 are combined, and an image suppression type converter 41 is provided for upstream and downstream signals.
6, 426, 507, and 517, and 90-degree phase shifters 418 and 529 using digital processing circuits.

FIG. 9 shows the signals in the up and down directions.
With such a configuration, the digital signal processing circuit 403 can generate the distortion compensation component of the main amplifier 50 as a power amplifier with higher accuracy.

The digital signal processing circuit 40 described above
In the digital linearization method of No. 3, the D / U (ratio of signal band distortion) of the output signal of the D / A converter depends on the bit precision (number of bits) of the D / A converter. When the input signal is an analog signal, A / D conversion is required to digitize the analog signal. However, this A / D conversion noise is mixed and D / D conversion is performed.
Degrades U.

In this case, it is possible to improve the distortion by combining with the feedforward method.
That is, in the feedforward method, a part of an input signal is branched, and a difference from a part of an output of an amplifier is obtained to obtain a distortion component. By adding this distortion component to the output of the amplifier in the reverse direction, the distortion component is canceled.

FIG. 10 is a diagram showing a fourth embodiment of the present invention, which employs the above-mentioned feed-forward system.

That is, the output of the modulator group 400 is branched, and a part of the output is input to the linearizer circuit 402 through the A / D converter 401. The other is input to the subtraction circuit 101 through the delay circuit 102. In the subtraction circuit 101,
The difference between the branched input component and the output of the power amplifier 50 is obtained and amplified by the distortion amplifier 104 (a low distortion amplifier with a low amplification factor). Furthermore, the amplified distortion component removes the distortion component from the output of the power amplifier 50 in the directional coupler 105.

In each of the above embodiments, the use of the digital linearizer 402 greatly reduces the distortion, and at the same time, further reduces the distortion by 10 to 2 due to the slight power consumption of the distortion amplifier.
The distortion suppression of 0 dB becomes possible.

Since each of the embodiments described above is basically a pre-distortion system, if the parameter relating to the linearity of the device to be linearly compensated does not change,
Once the distortion compensation data is created, it is not necessary to update the data by feedback.

Therefore, the distortion compensation parameter needs to be updated only in the case of a slow change such as a change in temperature or diameter. This means that there is no problem with intermittent feedback. As a result, the power consumption of the distortion compensation part can be reduced.

FIG. 11 is a block diagram showing a fifth embodiment of the present invention which performs such feedback intermittently. In comparison with FIG. 2 or FIG. 3, in FIG.
A / D converter 4 between delay circuit 405 and comparison circuit 404
Gate circuits 409 and 411 between
Is provided. Further, the operations of the gate circuits 409 and 411 and the A / D converter 42 are intermittently controlled by the intermittent operation control circuit 7, and the distortion compensation operation is intermittently operated.

FIG. 12 is a diagram for explaining a configuration for intermittently controlling the distortion compensation operation according to the present invention. 12, the intermittent operation control circuit 7 includes a correlator 70, a timing generator 71, and a clock generator 72.

The clock CL from the clock generator 72 is
Clock a as reference₀, A₁, A _TwoOccurs and the phase
Input a of Seki 70_Three, Output a_FourAnd when
The relationship is as shown in FIG.

When the duty of the intermittent operation of the feedback system from the power amplifier 50 is 1/10 (for example,
Pause for 9 seconds and operate for 1 second), at some suitable time t
On at _0, t 0 _{+ 1} off, clock a from the timing generator 71 so as to be turned on again at t 0 _{+ 9 0,} a
_1, the generation of a ₂ is controlled.

That is, at time t ₀ and t _{0 +9} , the A / D converter 4
2. The AND gates 409 and 411 are operated. Therefore, even when a phase shift occurs in the input signal as shown by a ₃ in FIG. 14, it is possible to output the input signal having the phase of a ₃ with the correct timing.

Here, the function of the correlator 70 is as follows.
It detects which portion of the data that has been fed back corresponds to the downlink transmission data. As shown in FIG. 13A, for example, the MSB of the transmission data is
X-direction shift register 701 input through
And MS of data fed back from the amplifier 50
B-input Y-direction shift register 702, X-direction shift register 701 and Y-direction shift register 702
Multipliers 711 to 71 for multiplying the output of each stage of
n and a combiner 703 that combines the outputs of the plurality of multipliers 711 to 71n.

[0064] Thus, from the synthesizer 703, the peak output a ₄ appears at matched point of the transmission data and the feedback data. The peak output a ₄ is input to the timing generator 71, the timing signal a ₁ at this time, a ₂ is output.

As a means for connecting a radio base station and a forward base station that handles radio frequencies, a method of transmitting radio frequencies directly through an analog optical fiber line has been put to practical use. However, in general, distortion occurs in the E / O and O / E conversion units, and high power and multiple wave transmission cannot be performed.

Therefore, the radio frequency power amplifier is connected to an analog optical fiber transmission line (a system including an E / O converter, an optical fiber, an O / E converter, or an E / O converter, an optical fiber, an O / E converter).
/ E conversion unit and a system including the power amplifier 50), and a method of nonlinearly compensating a return signal from the power amplifier 50 by an analog optical fiber transmission line is also employed. This makes it possible to perform nonlinear compensation including distortion of the optical transmission line and distortion of the high-power amplifier.

FIG. 15 is a block diagram showing a sixth embodiment of the present invention, and is a block diagram showing an example of a system configuration in which the radio frequency power amplification stage is replaced with an analog optical fiber transmission line as described above. In the figure, D /
The output of the A converter 41 is converted into an optical signal by the E / O converter 151. Further, the optical signal transmitted through the analog optical fiber 150 is transmitted to the O / E converter 152 at the forward base station.
To an electric signal, and further input to the power amplifier 50.

The signal branched and fed back from the power amplifier 50 is transmitted to the E / O converter 1 at the forward base station.
The optical signal is converted into an optical signal by the
0 to the wireless base station side, and the O / E converter 152
Is converted into an electric signal.

FIG. 16 is a block diagram showing a seventh embodiment of the present invention. In the embodiment of FIG. 15, the return signal from the power amplifier 50 is transmitted through the same analog optical fiber 150 as the main line. However, in order to generate the same distortion, the return signal is immediately A / D converted by the A / D converter 42 and converted into digital data as shown in FIG.
By converting this into an optical signal and transmitting it through a digital optical fiber, the problem of distortion is relieved.

Further, in the method of transmitting an analog signal to an optical fiber, the elements (laser diodes, photodiodes, etc.) constituting the E / O and O / E converters have a large non-linearity, and therefore a large distortion. Power transmission is not possible.
Therefore, as shown in FIG. 17, the digital fiber 153 is used for both the up direction and the down direction.

That is, the digital optical fiber transmission line 153 is connected to the interface of the D / A converter 41, the A / D converter 42 for the return signal from the power amplifier and the interface (for example, a 12-bit bus) of the linearizer 402. .

With this method, the problem of instability and distortion peculiar to the analog circuit can be relieved.

Here, it is possible to perform nonlinear compensation by the method using the above-mentioned optical fiber transmission line. However, this data is usually quite large (for example, 12 × 50 = 600 Mb).
ps), and it is not economical to transmit a few km at present under the present circumstances, though the digital line is cheaper than the analog line.

For this reason, in the ninth embodiment shown in FIG. 18, a plurality of optical fibers are prepared and divided by a distributor 154 into a plurality of low-speed optical fiber transmission lines for transmission. Further, on the forward base station side, the combiner 155 converts the optical signals sent from the plurality of low-speed optical fiber transmission lines into electric signals, and then combines the electric signals with the combiner 155 to convert the signals into the original high-speed specified clock speed signal. .

Further, as another form, as shown in FIG. 19, a configuration in which a high-speed signal is converted into a low-speed signal and processed using a FIFO (first-in / last-out) can be provided. In the configuration of FIG. 19, the FIFO circuit 156 converts the digital data output from the A / D converter 42 obtained by A / D conversion at a high specified clock rate for a certain period of time (for example, 600 Mbps to 1 second sample). This is then transmitted at 1/100 Mbps for 100 seconds).

Since the cost of a digital line of about 6 Mbps is very low, an inexpensive forward base station system can be constructed by this method.

FIG. 20 is a detailed block diagram corresponding to FIG. 19, showing details of the embodiment using such speed conversion. Further, FIG. 21 shows a time chart of each timing corresponding to FIG.

The clock a output from the AND gate 74
_The A / D converter 42 operates at the timing of ₀ , and data is accumulated in the FIFO memory 156 during this period. Then, the stored data is read is performed at the timing of a _20, the reading of the period a ₁₀ at a low speed takes place.

Data read from the FIFO memory 156 is converted into an optical signal by the E / O converter 151 and transmitted through the digital optical fiber 153. The signal is again converted into an electric signal by the O / E converter 152 and
The data is written to the O memory 157. At this time, are read at the timing of a _21, read is completed in a period of a _11.

In FIG. 20, as can be understood from the time chart of FIG. 21, the operations other than those described above are the same as those of FIGS.

When an optical fiber is used as the transmission line, the transmission line must be buried underground. However, if the transmission line can be transmitted through a microwave line such as a quasi-millimeter wave, there is no need to bury the transmission line and the system can be manufactured at low cost. Can be built. FIG. 22 is a block diagram showing an embodiment of such a system.

The transmission lines are connected to microwave lines 160 and 161.
Other than the above, it is the same as the embodiment described above. Further, in the case of transmission via a microwave line, the method of returning a feedback signal from a power amplifier via an analog micro line may be affected by distortion. For this reason, in the embodiment of FIG. 22, the digital microwave line 161 is used in the downstream direction for digital data transmission.

It is to be noted that transmitting high-speed digital data over a wireless line is very expensive and impractical.
Therefore, in FIG. 22, the intermittent operation timing circuit 17 is further provided as described in the fifth embodiment of FIG.
By providing 0 and 171, the transmission speed can be reduced, and practical use becomes possible.

Here, considering a multi-carrier common amplifier, it is not necessary to set the saturation power of the power amplifier up to the power when all carrier vectors match, and the required distortion (D / U) can be reduced. It has been reported that the saturation power can be reduced depending on the amount. For example, [RCS-90
-4: Ultra-low distortion multi-frequency common amplifier for mobile communication-Self-adjusting feedforward amplifier (SAFF-A) Nojima, Narahashi] That is, the level obtained by multi-frequency synthesis is almost equal to the Rayleigh distribution and is equal to or more than a certain level. The frequency of the instantaneous power is very low, which means that the input signal may be limited at a certain level.

Here, as an example, the power amplifier 50 is
, The gate voltage and the gate current are examined. In FIG. 23, the horizontal axis represents the gate voltage (VgS), and the vertical axis represents the gate current (Igs). In the figure, I indicates a Rayleigh distribution which is an input power distribution. The level distribution of the input power is symmetrically distributed deep and shallow with the operating point OP as the center (target axis).

When a voltage deeper than the breakdown voltage 1P is applied, the gate current sharply increases, causing gate breakdown. If the MSB (maximum voltage) 2P of the D / A converter is set immediately before the gate current sharply increases, the power applied to the FET element of the power amplifier 50 is always less than this, and the device is deteriorated. Can prevent that. Taking a point 2P ′ symmetrical to 2P with the operating point OP as the axis of symmetry, 2P ′ is also the breakdown point 1
It goes without saying that it is just before P '.

FIG. 24 shows the result of simulating the relationship between the precision (number of bits) and the distortion (D / U) of the D / A converter. If the output back off (OBO) is small, the head will be cut off at a relatively small level.
Is bad. In such a case, it can be understood that D / U is not improved even if the accuracy of the D / A converter is increased.

Conversely, when OBO is large, D
If the accuracy of the / A converter is improved, D / U will be improved accordingly. This relationship is a fact first quantitatively grasped by the present inventors.

According to the above relationship, the optimum D / A and A / D for the required D / U can be obtained without using an expensive A / D and D / A converter with higher accuracy than necessary. It has been clarified by the present inventors that a D converter exists. Based on this relationship, a more efficient device can be realized by designing the accuracy (number of bits) of the D / A converter.

On the other hand, in the conventional radio base station for mobile communication, one transmitter is installed for each wave to generate many carriers. On the other hand, by using a group modulator, this part can be constituted by several LSIs. Since the output of the group modulator is a digital signal (for example, a 12-bit bus), this signal is D / A converted and converted into an analog signal, and then input to the high power amplifier.

Thus, even when a group modulator is used, a digital linearizer is inserted immediately before a D / A converter rather than an analog linearizer (for example, feed forward), so that a modulation unit and a carrier can be used. Overwhelming downsizing, light weight, and low cost of the synthesizing unit, power amplifying unit, and linear circuit can be achieved.

FIG. 25 is a block diagram showing a twelfth embodiment of the present invention constituted as described above. The output of the group modulator 500 is connected to the digital data bus 501.
, A distortion correction value is added by the digital signal processing circuit 403, and the distortion correction value is input to the power amplifier 50.

The group modulator 500 can be composed of, for example, a transmultiplexer and a digital quadrature modulator.

In general, the power amplifier 50 operates at a level exceeding the OBO amount, so that the instantaneous value of the spectrum deteriorates by about 20 to 30 dB from the average value. The instantaneous value can be measured by setting the spectrum analyzer to a peak hold mode.

Since the spectrum is usually measured by averaging,
Although the instantaneous value does not matter much, if the instantaneous value can be reduced, the average D / U can be further improved.

Since the input level can be determined by the digital processing unit, when the maximum level of the D / A converter is exceeded (D / A
It is assumed that the MSB of the A converter is set to be the saturation power), and the instantaneous value of the spectrum can also have the effect of improving the D / U by smoothly shaping the clipped waveform.

FIG. 26 is a block diagram of a thirteenth embodiment of the present invention for obtaining such effects. 25, a clip level detection circuit 602 and a smoothing circuit 601 are provided between the group modulator 500 and the digital signal processing circuit 403. The delay circuit 600
Is a circuit for adjusting the operation of the smoothing circuit 601 to the processing time of the clip level detection circuit 602.

FIG. 27 shows the delay circuit 6 in FIG.
FIG. 2 is a block diagram illustrating a configuration example of a smoothing circuit 601 and a clip level detection circuit 602. The smoothing circuit 601 basically forms a transversal filter.

FIG. 28 is a view for explaining clip level detection. As shown in FIG. 28, when the input voltage amplitude I exceeds the clip level CL, the level detector 602
Detects this.

On the other hand, the smoothing circuit 601 includes an n-stage shift register 603, a weighting controller 604,
For each stage of the shift register 603, the weighting factor a _n from the weighting controller _{604, a n-1, ··} a 1, a
_0, a _-1, the multiplier 61n ·· 61 multiplying the ··· a _-n
.. 61n, an accumulator 605 and a multiplier 606.

Therefore, by the level detector 602,
When detecting that the input voltage amplitude I exceeds the clip level CL, the weighting controller 604 outputs a predetermined weighting coefficient. Then, the value of each stage of the shift register 603 is multiplied by a predetermined weighting coefficient, and the output is accumulated by the accumulator 6.
Input to 05 and synthesize. As a result, the waveform is smoothed (smoothed) into the waveform shown by the dotted line II in FIG.

Further, the output of the accumulator 605 is
6 and multiplied by a coefficient b. The coefficient b is obtained by setting the center level a _{0 of the} tap to 1 / as shown in FIG.
and n, level a _1, a _-1 ·· a _n before and after the tap shown in FIG. 28 (II), a _-n and levels match.

The embodiment shown in FIG. 27 requires a high-speed digital transversal filter. In contrast,
FIG. 29 shows another configuration of the clip correction.
That is, the sample rate conversion unit 501 and the frequency multiplexing unit 50
2. In the group modulator including the channel filter 503 and the quadrature modulator 504, the level detector 602
, The output of the group modulator is constantly monitored.

When it becomes clear that the amplitude level exceeds the MSB of the D / A converter, the amplitude of each carrier is reduced to an equal or unequal amount. A configuration for reducing the amplitude of each carrier to an equal amount or an unequal amount uses a weight controller 604 similar to that in FIG.
The output is multiplied by the output of the mapping unit 512 by the multipliers 701 to 70n in the sample rate conversion unit 501.

As described above, the amplitude is reduced before the roll-off filter 514. As a result, the band is limited by the baseband roll-off filter for each carrier, so that processing can be performed at a low speed. In addition, since the voltage is clipped ideally, the instantaneous spectrum degradation in the peak hold mode is completely suppressed.

Further, as shown in the configuration example of FIG. 4, the digital signal processing circuit 403 of the linearizer circuit 402
The distortion correction data is stored in the AM memory 140, but the initial value of the distortion correction data is undefined, and the distortion immediately after the start of operation is not compensated.

Therefore, as a fourteenth embodiment of the present invention, as shown in FIG. 30, a nonvolatile memory 710 for storing data is prepared. Then, at the time of factory shipment, a trial operation is performed to obtain final data, and the final data is stored in the nonvolatile memory 710. RAM just before actual operation
This value is installed in the memory 140 such as. As a result, it is possible to converge in a very short time and perform actual operation.

Further, it is conceivable that the distortion data changes due to the time change during operation. In such a case, immediately before the operation is stopped by the control
By saving the data of 140 in the nonvolatile memory 710, a smooth operation at the next operation is compensated.

If the input signal is a burst-like TDMA signal (one carrier wave), a short preamble burst is emitted immediately before the start of the burst, thereby generating linearized data. As the preamble data, as shown in FIG. 31, data can be obtained in a very short time by a monotonically increasing function taking a value from 0 to a maximum value or a staircase wave.

FIG. 31A shows the relationship between the preamble period I and the main burst period II, and FIG. 31B shows an example of a triangular wave function that monotonically increases and decreases as a function of the preamble period I. . FIG. 31C shows an example in which a staircase wave function is used.

By the way, it is more economical to perform the linearize operation for compensating the distortion of the amplifier in the forward base station because it is not necessary to return the return signal to the parent base station on the transmission line. FIG. 32 is a block diagram shown as a fifteenth embodiment of the present invention.

That is, the digital signal processing circuit 403 is provided in the forward base station on the side where the antenna 53 exists.

Further, as shown in FIG. 33 as a sixteenth embodiment of the present invention, an upstream signal is transmitted to a plurality of analog optical fiber transmission lines 15 by a plurality of space diversity.
4 to transmit to the base station. Instead of the analog optical transmission line, it is also possible to install an upstream transmission line using an analog microwave transmission line. This makes it possible to realize an ultra-small radio base station (on a pole).

Further, as shown in FIG. 34, if the accuracy and speed of the A / D converter 441 can be increased, the analog transmission line 154 can be replaced with a digital transmission line 153. As a result, an inexpensive, highly stable, and high quality transmission path can be constructed.

[0115]

As described above according to the embodiments, the present invention relates to an up converter and a down converter.
An image rejection type frequency converter is used to easily suppress unnecessary sidebands. Furthermore, a 90-degree phase shifter is required for an image rejection type frequency converter, and it is difficult to produce a passive circuit if the fractional bandwidth is large. However, the present invention can be easily produced by a digital signal circuit. And

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the positioning of the present invention.

FIG. 2 is a diagram illustrating the premise of the present invention.

FIG. 3 is a block diagram showing a first embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration example of a linearizer.

FIG. 5 is a block diagram illustrating a configuration example of a 90-degree phase shifter using digital signal processing.

FIG. 6 is a diagram illustrating an image suppression type upconverter.

FIG. 7 is a configuration example of a double balance type modulator.

FIG. 8 is a block diagram showing a second embodiment of the present invention.

FIG. 9 is a block diagram showing a third embodiment of the present invention.

FIG. 10 is a block diagram showing a fourth embodiment of the present invention.

FIG. 11 is a block diagram showing a fifth embodiment of the present invention.

FIG. 12 is a diagram illustrating a configuration of an intermittent operation.

FIG. 13 is a diagram illustrating a configuration example of a correlator.

14 is a time chart of each timing in FIG.

FIG. 15 is a block diagram showing a sixth embodiment of the present invention.

FIG. 16 is a block diagram showing a seventh embodiment of the present invention.

FIG. 17 is a block diagram showing an eighth embodiment of the present invention.

FIG. 18 is a block diagram showing a ninth embodiment of the present invention.

FIG. 19 is a block diagram showing a tenth embodiment of the present invention.

FIG. 20 is a detailed block diagram corresponding to FIG. 19;

FIG. 21 is a time chart of each timing in FIG. 20;

FIG. 22 is a block diagram showing an eleventh embodiment of the present invention.

FIG. 23 is a diagram illustrating an input signal power distribution and current characteristics of a semiconductor device.

FIG. 24 is a diagram illustrating the relationship between D / A accuracy and amplifier distortion.

FIG. 25 is a block diagram showing a twelfth embodiment of the present invention.

FIG. 26 is a block diagram showing a thirteenth embodiment of the present invention.

FIG. 27 is a diagram illustrating a configuration example of a clip level detection circuit and a smoothing circuit.

FIG. 28 is a diagram illustrating clip level detection.

FIG. 29 is a diagram illustrating another configuration example of clip correction.

FIG. 30 is a block diagram showing a fourteenth embodiment of the present invention.

FIG. 31 is a diagram illustrating an example of a preamble waveform.

FIG. 32 is a block diagram showing a fifteenth embodiment of the present invention.

FIG. 33 is a block diagram showing a sixteenth embodiment of the present invention.

FIG. 34 is a block diagram showing a seventeenth embodiment of the present invention.

[Explanation of symbols]

0 Public communication network 1 Optical termination equipment 2 MUX / DMUX section 3 TDMA section 4 Modem section 402 linearizer circuit 403 Digital signal processing circuit 404 Comparison circuit 405 delay circuit 41, 417, 427 D / A converter 42, 44 A / D converter 5 Radio frequency part 50 power amplifier 52 splitter 416 upconverter 418 90 degree phase shifter 426 down converter

Continuation of front page (56) References JP-A-6-21990 (JP, A) JP-A-6-318959 (JP, A) (58) Fields studied (Int. Cl. ⁷ , DB name) H04B 1 / 02-1/04 H04B 1/38-1/58 H03D 7/18

Claims (20)

(57) [Claims] 1. A transmitting / receiving antenna, a high-frequency power amplifier for amplifying a transmission signal radiated from the transmitting / receiving antenna, and an A for converting a part of the output of the high-frequency power amplifier into a digital signal.
A / D converter and an input side of the high-frequency power amplifier, and the input digital transmission signal and the output of the A / D converter are compared with each other to reduce a difference obtained by comparing the output of the A / D converter. In a wireless communication base station having a linearize circuit for correcting amplitude and phase and performing amplification with less distortion, an image rejection type provided between the linearize circuit and the high-frequency power amplifier A frequency upconverter, the image rejection type frequency upconverter includes a first phase shift circuit that shifts the output of the linearize circuit by 90 °, and a first phase shift circuit that D / A converts the output of the phase shift circuit. D / A
A conversion circuit; a second D / A conversion circuit for directly D / A converting the output of the linearization circuit; and an output of the first D / A conversion circuit and the second D / A conversion circuit, respectively. , Q quadrature signals, and 90 ° out of phase with each other and with higher frequency oscillation signals than the outputs of the first D / A conversion circuit and the second D / A conversion circuit. A base station for wireless communication, comprising a circuit. 2. A transmitting / receiving antenna, a high-frequency power amplifier for amplifying a transmission signal radiated from the transmitting / receiving antenna, and an A / A converter for converting a part of the output of the high-frequency power amplifier into a digital signal.
A D converter, provided on the input side of the high-frequency power amplifier,
The amplitude and phase of the transmission signal are corrected so that the difference obtained by comparing the input digital transmission signal with the output of the A / D converter becomes zero, and control is performed so as to perform amplification with little distortion. A wireless communication base station having a linearizing circuit, further comprising a branching circuit for branching the output of the high-frequency power amplifier, and an image rejection provided between the linearizing circuit and the branching circuit A frequency downconverter, wherein the image rejection type frequency downconverter mixes the output of the demultiplexer with an oscillating signal having a phase shifted by 90 ° and having a lower frequency than the output of the demultiplexer. A fourth mixing circuit; first and second A / D conversion circuits for converting respective outputs of the third and fourth mixing circuits into digital signals; and an output of the second A / D conversion circuit. 9 A second phase shift circuit for phase shifting, wherein the outputs of the third mixing circuit and the second phase shift circuit are input to the linearization circuit as I and Q quadrature signals, respectively, and the digital transmission signal A base station for wireless communication characterized by being compared with: 3. A transmitting / receiving antenna, a high frequency power amplifier for amplifying a transmission signal radiated from the transmitting / receiving antenna, and an A / A converter for converting a part of the output of the high frequency power amplifier into a digital signal.
A D converter, provided on the input side of the high-frequency power amplifier,
The amplitude and phase of the transmission signal are corrected so as to reduce the difference obtained by comparing the input digital transmission signal with the output of the A / D converter, and control is performed to perform amplification with less distortion. A wireless communication base station having a linearize circuit, comprising: an image rejection type frequency upconverter provided between the linearize circuit and the high frequency power amplifier, wherein the image rejection type frequency upconverter comprises: A first phase shift circuit for shifting the output of the circuit by 90 °, and a first D / A for D / A converting the output of the phase shift circuit
A conversion circuit; a second D / A conversion circuit for directly D / A converting the output of the linearization circuit; and an output of the first D / A conversion circuit and the second D / A conversion circuit, respectively. , Q quadrature signals, and 90 ° out of phase with each other and with higher frequency oscillation signals than the outputs of the first D / A conversion circuit and the second D / A conversion circuit. An image rejection type frequency down-converter provided between the linearizing circuit and the demultiplexing circuit, further comprising a demultiplexing circuit for demultiplexing an output of the high-frequency power amplifier. A rejection-type frequency downconverter comprising: a third and a fourth mixing circuit for mixing the output of the demultiplexer with an oscillation signal having a phase shifted by 90 ° and having a lower frequency than the output of the demultiplexer; Each of the third and fourth mixing circuits A first and a second A / D conversion circuit for converting an output into a digital signal; and a second phase shift circuit for shifting the output of the second A / D conversion circuit by 90 °. A radio communication base station, wherein outputs of the third mixing circuit and the second phase shift circuit are input to the linearization circuit as I and Q quadrature signals, respectively, and are compared with the digital transmission signal. 4. A transmission / reception antenna, a high-frequency power amplifier for amplifying a transmission signal radiated from the transmission / reception antenna, and a part of an input transmission signal and a part of an output of the high-frequency power amplifier provided on an input side of the high-frequency power amplifier. In a wireless communication base station having a linearization circuit that corrects the amplitude and phase of the transmission signal so as to reduce the difference obtained by comparing A wireless circuit comprising: a circuit for obtaining a difference between a signal and an output of the high-frequency power amplifier; and a directional coupler for coupling an output of the circuit for obtaining the difference to an output of the high-frequency power amplifier. Communication base station. 5. The method according to claim 1, wherein M is a maximum output voltage of the first and second D / A converters.
A base station for wireless communication, wherein SB is set to a value immediately before characteristics and life of the high-frequency power amplifier are not compensated. 6. The intermittent operation according to claim 1, 2 or 3, wherein the output of the A / D converter for converting the output of the high-frequency power amplifier to a digital signal is periodically transmitted to the linearize circuit. A base station for wireless communication, comprising a control circuit. 7. The first speed conversion circuit according to claim 1, 2 or 3, wherein the first speed conversion circuit converts the output of the A / D converter for converting the output of the high-frequency power amplifier into a digital signal to a low speed. It has a second speed conversion circuit for further converting the output of the speed conversion circuit to the original speed, and an optical fiber or a microwave line is provided between the first speed conversion circuit and the second speed conversion circuit. A wireless communication base station characterized by being interposed. 8. The system according to claim 7, wherein the first speed conversion circuit and the second speed conversion circuit
A wireless communication base station comprising an IFO (First In First Out) memory. 9. The high-frequency power amplifier according to claim 1, wherein the high-frequency power amplifier is arranged at a forward base close to the transmitting antenna, and the forward base and the linearize circuit are connected by an analog optical transmission line. A base station for wireless communication. 10. The high-frequency power amplifier according to claim 1, wherein the high-frequency power amplifier is disposed at a forward base close to the transmitting antenna, and the forward base and the linearize circuit are connected by a digital optical transmission line. A base station for wireless communication. 11. The A / D converter according to claim 10, wherein the operation of the A / D converter for converting the output of the high-frequency power amplifier into a digital signal is periodically performed intermittently for a short time, and the output of the A / D converter is output. A wireless communication base station configured to return to the linearize circuit by the digital optical transmission line at a low speed. 12. The radio communication base station according to claim 10, wherein said digital optical transmission line is divided into N lines and N digital optical transmission lines are reduced to a speed of 1 / N. . 13. The digital transmission signal according to claim 1, further comprising a group modulator for collectively generating modulated waves of a plurality of channels, wherein a multicarrier signal from the group modulator is input to the input digital transmission signal. A base station for wireless communication. 14. The output of a signal according to claim 13, further comprising a digital filter on an output side of said group modulator, wherein an output level of said group modulator exceeds a maximum output voltage (MSB) of said D / A converter. A base station for wireless communication, characterized in that the occurrence of clipping noise is suppressed. 15. The D / A converter according to claim 13, further comprising monitoring an output of said group modulator.
A level detection circuit for detecting a state in which the amplitude level exceeds a maximum output voltage (MSB) of the converter; and a detection output of the level detection circuit for controlling individual amplitudes of the modulated waves of the plurality of channels to decrease. A base station for wireless communication, comprising a control circuit. 16. The linearization circuit according to claim 1, further comprising: a RAM for storing data for providing predistortion; and a non-volatile memory externally, which is actually operated in advance. A wireless communication base station, wherein data for giving a pre-distortion is stored in the non-volatile memory, and data stored in the non-volatile memory is transferred and stored in the RAM immediately before actual operation. 17. The wireless communication base station according to claim 16, wherein the contents stored in said RAM are transferred and stored in said nonvolatile memory immediately after the power is turned off after actual operation. 18. The forward base station according to claim 1, 2 or 3, wherein a linearizing circuit is disposed on a side of the forward base station having the transmitting antenna, and the digital transmission signal is transmitted by a digital optical fiber transmission line or a microwave transmission line. A base station for wireless communication characterized by transmitting to a station. 19. The wireless communication base station according to claim 18, wherein the upstream signal is transmitted to the base station through an analog optical fiber transmission line or a microwave transmission line through a low noise amplifier. 20. The microwave transmission line according to claim 18, wherein the microwave transmission line has an ultra-high frequency of 4 to 8 GHz,
A base station for wireless communication, wherein the base station is a quasi-millimeter wave of 40 to 40 GHz or a millimeter wave line of 40 to 80 GHz.