JP3534096B2 - Low power semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which power consumption of a clock distribution circuit is reduced, and more particularly to a semiconductor integrated circuit improved so as not to fall into a permanent stop state even if a malfunction occurs.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit for performing logic processing
From the viewpoint of design ease, from the clock signal supply circuit
Common clock signal of the
The operation circuit is operated according to the lock timing, and the operation result
Generally, a synchronous design that takes the result into a flip-flop is used.
It In recent years, the speed of circuit operations has increased and the scale of circuits has increased.
Depending on the direction, distribute high frequency clock signals to large scale circuits
The need is emerging. However, high-speed clock signals
Signal is distributed to a large-scale circuit,
Cost, which reduces power consumption in clock distribution.
Is required. To meet this request, an example
For example, as disclosed in Japanese Patent Laid-Open No. 11-110064.
In addition, do not distribute unnecessary clock signals to unnecessary timing.
A circuit for controlling the operation is proposed. This prior art
Figure of circuit disclosed in the literature5Shown in. This circuit has many
Internal arithmetic circuit 200 with internal functional blocks of
Internal calculation based on the clock signal of input clock 1
Distribute clocks to many internal functional blocks in the circuit
The operation result of the clock distribution circuit 100 and the internal operation block
The control signal 400 for controlling the clock distribution circuit is issued from the result.
It is composed of a control unit 300 for generating the data. Clock minutes
The distribution circuit 100 includes a control signal 400 and a clock therein.
Clock driver for AND circuit that takes AND with signal
Are arranged in a tree structure. The control unit 300
It is necessary to distribute the clock signal from the calculation result of the calculation block.
For the internal calculation blocks that are not necessary, use the corresponding clock driver.
Set the EVER control signal to LOW level and6C
As shown in LKa to CLKd, it is not necessary to supply the clock.
It will stop for a long time. This control unit
From the output of the lock operation result and the operation of the clock distribution circuit
Pre-designed by logic circuit and built in integrated circuit
Has been. By taking such a configuration,7
The clock distribution circuit up to that point shown in FIG.
Operation that constantly supplies a clock (Fig.7(Shown in (B))
In all, it is possible to reduce the power consumption in the integrated circuit.
Has the advantage that

[0003]

However, in the above technique, the semiconductor integrated circuit malfunctions due to noise inside the semiconductor integrated circuit or outside the semiconductor integrated circuit, and all the control signals of the clock driver are set to the LOW level. In that case, the clock is no longer distributed to the internal function block, which causes a problem that the internal function block stops. Further, since there is no means for detecting that the clock is no longer distributed, it is not possible to deal with the abnormal state inside the semiconductor integrated circuit or outside the semiconductor integrated circuit. Therefore, there is a problem that the semiconductor integrated circuit is stopped forever. The main object of the present invention is to reduce power consumption by not distributing unnecessary clocks,
At the same time, another object of the present invention is to provide a semiconductor integrated circuit that does not fall into a permanent stop state even if a malfunction occurs.

[0004]

According to a first aspect of the present invention, there is provided a low power consumption semiconductor integrated circuit which comprises a plurality of first delay time differences adjusted from a first clock signal input from the outside of the semiconductor integrated circuit. Clock distribution means for generating and distributing two clock signals, and a plurality of internal processing means for calculating and outputting a data signal input from the outside of the semiconductor integrated circuit in synchronization with the distributed second clock signal. Among the plurality of internal arithmetic means, the internal arithmetic means that does not require clock supply is provided with a clock distribution control means for outputting a control signal for stopping the second clock signal to the clock distribution means, and an unnecessary clock is provided. Is a low power consumption semiconductor integrated circuit that reduces the power required for clock distribution by not distributing the clock to the internal computing means. Abnormal state detection that outputs an alarm signal when an abnormal state in which all clocks distributed to the plurality of internal arithmetic units continue to stop is detected from the control signal output from the distribution unit and the first clock signal Means, are provided. In the low power consumption semiconductor integrated circuit of the invention according to claim 2 of the present invention, the control signal output from the clock distribution control means according to the invention of claim 1 is calculated by the plurality of internal calculation means. It is characterized in that it is generated based on the output. The low power consumption semiconductor integrated circuit of the invention according to claim 3 of the present invention is the low power consumption semiconductor integrated circuit according to the invention of claim 1 or 2, further comprising the clock distribution control means and the clock. Between the distribution means, from the control signal and the alarm signal, when the abnormal state occurs, to output a control signal for forcibly distributing the clock to the internal calculation means, to the clock distribution means, It is characterized in that the semiconductor integrated circuit is provided with self-sustained recovery means for autonomously returning from the abnormal state to a normal state. Further, in the low power consumption semiconductor integrated circuit of the invention according to claim 4 of the present invention, the abnormal state detection means according to any one of claims 1 to 3 is output from the clock distribution control means. NOR to input control signal
And a flip-flop for receiving the output of the NOR circuit and the first clock signal and outputting the alarm signal. Further, in the low power consumption semiconductor integrated circuit of the invention according to claim 5 of the present invention, the abnormal state detection means according to any one of claims 1 to 3 is output from the clock distribution control means. An NOR circuit for inputting a control signal, a plurality of stages of flip-flops, and an AND of all the outputs of the plurality of stages of flip-flops to output the alarm signal.
The flip-flop of the first stage is provided with a D circuit, the output of the NOR circuit and the first clock signal are input, and the flip-flops of the second and subsequent stages include the output of the flip-flop of the previous stage and the It is characterized in that it receives the first clock signal and the input.

[0005]

BEST MODE FOR CARRYING OUT THE INVENTION In order to clarify the objects, features and advantages of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Referring to FIG. 1, there is shown a low power consumption semiconductor integrated circuit as an embodiment of the present invention. The low power consumption semiconductor integrated circuit includes a clock distribution circuit 10 and internal function blocks 21 to 21.
It has an internal arithmetic circuit 20 including 24, a clock distribution control circuit 30, and an abnormal state detection circuit 40 which is a feature of the present invention. The clock distribution circuit 10 includes clock drivers 11, 12a, 12b, 13a, 1 that perform an AND operation.
3b, 13c and 13d are connected in a tree shape. Of these clock driver inputs, one input is the external input clock 1 (clock driver 1
1) or an output signal from another clock driver (12a to 13d), and a control signal for controlling the clock driver is input to the other input. In the example shown in FIG. 1, the control signal is fixed to the HIGH level (12a) and the output signal of the clock distribution control circuit 30 is input (11, 12b,
13a, 13b, 13c, 13d). The clock signals CLKa to CLKd output from the clock drivers 13a to 13d at the final stage of the clock driver having the tree structure are input to the internal function blocks 21 to 24 included in the internal arithmetic circuit 20. Internal arithmetic circuit 20 performs arithmetic operations in synchronization with CLKa to CLKd. The calculation result of each internal functional block includes signals 6a to 6c input to other functional blocks and signals 3a to 3c input to the clock distribution control circuit 30. In the clock distribution control circuit 30, the clock distribution circuit 10 is based on the signals 3a to 3c input from each internal functional block.
Control signals 4a to 4g for controlling are output. The signals 4a to 4g outputted from the clock distribution control circuit 30 are outputted to the clock distribution circuit 10 and simultaneously to the abnormal state detection circuit 40. The signal output from the clock distribution control circuit 30 is input to both the abnormal state detection circuit 40 and the clock distribution circuit 10 like 4a to 4e, and is input only to the clock distribution circuit 10 like 4f. There are signals and signals such as 4g that are input only to the abnormal state detection circuit 40. Abnormal condition detection circuit 40
From the states of the control signals 4a to 4e and 4g output from the clock distribution control circuit 30, an alarm signal 2 indicating whether the clock supplied to the internal functional block is in an abnormal state is output from the semiconductor integrated circuit. Output to.

An abnormal state detection circuit 40 which is a feature of the present invention
Can be configured by two flip-flops and an AND circuit as shown in FIG. Signals 4a to 4e and 4g output from the clock distribution control circuit 30
Is input to the NOR circuit 41. The output signal of the NOR circuit 41 is input to the flip-flop 42, and the output signal of the flip-flop 42 is input to the flip-flop 43. The output signals of the flip-flop 42 and the flip-flop 43 are input to the AND circuit 44, and the AND circuit 44 outputs the alarm signal 2. The present abnormal state detection circuit is not limited to this configuration, and the number of flip-flops may be one or three or more. 44 for one
AND circuit 44 becomes unnecessary, and when there are three or more,
The alarm signal 2 may be output by ANDing all the outputs of the flip-flops.

The operation of this embodiment will be described below. First, in the clock distribution circuit 10, the output signals of the respective clock drivers are controlled by the control signals 4a to 4f. That is, when each of the control signals 4a to 4f is at the high level, a clock pulse is output from the corresponding clock driver, but when the control signals 4a to 4f are at the low level, the corresponding clock driver outputs the clock pulse. Outputs a LOW level signal. In this way, clock pulses or LOW level signals are output from the signals CLKa to CLKd according to the control signals 4a to 4f. Next, the internal function block 21
24 to 24, arithmetic processing is performed in accordance with signals CLKa to CLKd output from clock distribution circuit 10. At this time, if CLKa to CLKd are clock pulses, arithmetic processing is performed in the corresponding internal functional block, but if CLKa to CLKd is a LOW level signal, arithmetic processing remains stopped in the corresponding internal functional block. Becomes Next, the clock distribution control circuit 30 controls the clock distribution circuit 10 based on the signals 3a to 3c output from the internal function blocks.
Output ~ 4g. In the abnormal state detection circuit 40, the semiconductor integrated circuit malfunctions due to factors such as noise inside the semiconductor integrated circuit or outside the semiconductor integrated circuit, and the clock distribution circuit 1
By keeping the output signals CLKa to CLKd of 0 continuously at the LOW level, all the internal function blocks 21 to 24 are
If a state occurs in which the signal continues to stop, when this state is detected, the alarm signal is set to HIGH level and output. That is, when all the control signals 4a to 4f for controlling the clock distribution circuit 10 continue to be LOW level, all the signals CLKa to CLKd also keep LOW level, and the clock is not distributed to the internal function blocks 21 to 24. At this time, the abnormal state detection circuit 4 shown in FIG.
At 0, when the signals 4a to 4e and 4g are all at the LOW level for two clocks, the flip-flop 4
2 and the output signals of the flip-flop 43 are both HI
It becomes the GH level, and the alarm signal 2 is set to the HIGH level and output.

[0008]

[0009]

As described above, in the semiconductor integrated circuit according to the present invention shown in FIG. 1, the clock distribution control circuit 30 appropriately sets the control signals 4a to 4f based on the output of the internal arithmetic circuit 20. The clock is distributed only to the blocks to be operated in 21 to 24, and the unnecessary clocks are not distributed to the internal functional blocks which are not desired to operate. A semiconductor integrated circuit can be realized, and at the same time, the present invention includes an abnormal state detection circuit, which is a feature of the present invention. In the abnormal state detection circuit 40, the clock signals distributed to the internal function blocks 21 to 24 are provided. CL
It constantly detects whether or not Ka to CLKd are in an abnormal state in which they all stop, and when an abnormal state is detected, an alarm signal is output. Therefore, outside the present low power consumption semiconductor integrated circuit, it is possible to know whether or not an abnormal state has occurred by monitoring the alarm signal. Further, if necessary, some measures such as the reset signal input can be taken from the outside of the low power consumption semiconductor integrated circuit in order to get out of the abnormal state.

In FIG. 2, all the signals 4a ...
Only when 4e and 4g are at the LOW level, the abnormal state is determined, but the abnormal state is not limited to this. For example, in the configuration diagram shown in FIG. 1, 4b, 4d,
Even if 4e and 4f continue to take the LOW level, the clock is not distributed to the internal function blocks 21 to 24 and the function blocks stop. The condition for determining an abnormal state may be changed as necessary. Further, since the abnormal state detection circuit 40 shown in FIG. 2 needs to be always operated, the external input clock 1 is used as the clock signal input to the flip-flop, but another non-stopped clock is used. May be.

As a second embodiment of the present invention, shown in FIG. 3 the arrangement further devised. In FIG. 3 , a forced recovery circuit 50 is added between the clock distribution control circuit 30 and the clock distribution circuit 10. Forced recovery circuit 50 is configured as shown in FIG. That is, the signals 4a, 4c, 4d and 4f output from the clock distribution control circuit 30.
And OR circuits 51 to 54 for performing an OR operation with the alarm signal 2 output from the abnormal state detection circuit 40. Signals 4b and 4e that do not require OR operation
Is output as it is. The signals 5a to 5f output from the forced recovery circuit 50 are transmitted to the clock distribution circuit 10
Entered in.

The operation of the low power consumption semiconductor integrated circuit using this forced recovery circuit will be described. First, regarding the operation of the clock distribution circuit 10, the internal function blocks 21 to 24, the clock distribution control unit 30, and the abnormal state detection circuit 40,
Is exactly the same as the embodiment of Next, in the forced recovery circuit 50, the signal 4a output from the clock distribution control circuit 30 is output.
4f and the alarm signal 2 output from the abnormal state detection circuit 40 are ORed and the result is signal 5a.
Output to 5f. At this time, the internal function blocks 21 to 2
When the clock is normally distributed to 4 and is in a normal state, the alarm signal 2 output from the abnormal state detection circuit 40 becomes LOW level, and 5a to 5f have the same values as 4a to 4f. On the other hand, when all the clock signals CLKa to CLKd distributed to the internal function blocks 21 to 24 are in an abnormal state where they continue to stop, the alarm signal 2 output from the abnormal state detection circuit 40 becomes HIGH level,
Output signals 5a, 5c, 5d, 5f of the OR circuits 51-54
Is forcibly set to the HIGH level. Figure 3 and Figure
In the configuration example shown in FIG. 4 , when the alarm signal 2 becomes HIGH, 5a, 5c, 5d and 5f become HIGH level, and the clock distribution circuit 10 outputs CLKb and CLKb.
A clock pulse is output to c. As described above, in the present embodiment, when the clock signals CLKa to CLKd distributed to the internal function blocks 21 to 24 all fall into an abnormal state where they continue to stop, the signals 5a to 5f output from the forced recovery circuit 50 are changed. By setting a certain signal from among them to the HIGH level, it is possible to forcibly generate clock pulses in CLKa to CLKd. As a result, even if a clock is not distributed to the internal function blocks 21 to 24 due to noise or the like inside or outside the semiconductor integrated circuit, no action is taken from outside the semiconductor integrated circuit. , It is possible to autonomously return to the normal state. In the present embodiment shown in FIG. 4 , when the alarm signal 2 is detected, 5a, 5a
Although c, 5d, and 5e are forcibly set to HIGH, this combination may be changed as necessary.

[0014]

As described above, according to the present invention, the clock distribution control means controls the clock distribution circuit to distribute only necessary clocks and not distribute unnecessary clocks, thereby realizing low power consumption. it can. Further, when all the clocks distributed from the clock distribution circuit to the internal functional blocks continue to stop, the abnormal state detecting means for detecting the abnormal state and outputting an alarm signal is provided, so that the low power consumption semiconductor integrated circuit is provided. The occurrence of an abnormal state can be notified to the outside of the circuit. As a result, some measure can be taken from outside the low power consumption semiconductor integrated circuit. In addition, when the above-mentioned abnormal state occurs, by forcibly distributing the clock to the internal functional blocks by providing the forcible recovery means, it is possible to prevent a permanent stop in the abnormal state.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a low power consumption semiconductor integrated circuit of the present invention.

FIG. 2 is a circuit diagram showing one configuration example of the abnormal state detection circuit shown in the first embodiment of the low power consumption semiconductor integrated circuit of the present invention.

FIG. 3 is a block diagram showing a configuration of a second embodiment of a low power consumption semiconductor integrated circuit of the present invention.

FIG. 4 is a circuit diagram showing a configuration example of a forced recovery circuit shown in a second embodiment of a low power consumption semiconductor integrated circuit of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional low power consumption semiconductor integrated circuit.

FIG. 6 is a diagram illustrating an operation of a conventional low power consumption semiconductor integrated circuit.

FIG. 7 is a diagram showing a conventional clock distribution circuit of a non-low power consumption semiconductor integrated circuit and its operation.

[Explanation of symbols]

1 External Input Clock 2 Alarm Signal 10 Clock Distribution Circuits 11, 12a, 12b, 13a, 13b, 13c, 13
d clock driver 20 internal arithmetic circuits 21, 22, 23, 24 internal function block 30 clock distribution control circuit 40 abnormal state detection circuit 50 forced recovery circuit 100 clock distribution circuit 200 internal arithmetic circuit 300 control unit 400 control signal

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 1/04 301 G06F 1/04 302 G06F 1/10 G06F 1/32

Claims (5)

(57) [Claims] 1. A first input from the outside of a semiconductor integrated circuit
A plurality of second delay time differences adjusted from the second clock signal
Clock distributing means for generating and distributing the clock signal, a plurality of internal calculating means for calculating and outputting a data signal input from the outside of the semiconductor integrated circuit in synchronization with the distributed second clock signal, Of the plurality of internal arithmetic means, the internal arithmetic means that does not require clock supply is provided with a clock distribution control means for outputting a control signal for stopping the second clock signal to the clock distribution means, and an unnecessary clock is supplied. A low-power-consumption semiconductor integrated circuit that reduces power required for clock distribution by not distributing to the internal arithmetic means, further comprising: the control signal and the first clock signal output from the clock distribution means. An alarm signal is output when an abnormal state in which all clocks distributed to the plurality of internal arithmetic means continue to stop is detected. A low power consumption semiconductor integrated circuit, comprising: Wherein said control signal output from the clock distribution control means, said plurality of low-power semiconductor according to 請 Motomeko 1 you characterized in that it is produced on the basis of the operation output of the internal calculation means Integrated circuit. 3. The low power consumption semiconductor integrated circuit further comprises: when the abnormal state occurs between the clock distribution control means and the clock distribution means from the control signal and the alarm signal, The semiconductor integrated circuit is provided with self-sustained recovery means for autonomously recovering from the abnormal state to the normal state by outputting to the clock distribution means a control signal for forcibly distributing the clock to the internal arithmetic means. low-power semiconductor integrated circuit according to 請 Motomeko 1 or 2 shall be the. 4. The abnormal state detection means inputs a NOR circuit to which the control signal output from the clock distribution control means is input, the output of the NOR circuit and the first clock signal, and the alarm signal. low-power semiconductor integrated circuit of the flip-flop, to any of 請 Motomeko 1 you characterized 3, further comprising serial <br/> mounting for outputting. 5. The NOR circuit for inputting the control signal output from the clock distribution control unit, the plurality of stages of flip-flops, and the AND output of all the outputs of the plurality of stages of flip-flops are taken by the abnormal state detection unit. And an AND circuit that outputs the alarm signal, wherein the first-stage flip-flop receives the output of the NOR circuit and the first clock signal as input, and the second- and subsequent-stage flip-flops low-power semiconductor integrated circuit according to any one of 3 請 Motomeko 1 you, characterized in that an input of the output and the first clock signal of the flip-flop.