JP3533956B2 - Pseudo random number generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo-random number generator for generating a pseudo-random number used in a cryptographic communication device or the like, and more particularly, it guarantees the equal frequency of outputs 1 and 0 and provides good random number characteristics. The present invention relates to a filter generator as a pseudo-random number generator that can be obtained.

[0002]

2. Description of the Related Art Conventionally, in communication systems such as telephone, wireless, and data communication, transmission information is encrypted in order to prevent the transmission information from being known to a third party. Among these encryption methods, the stream encryption method is particularly used for high-speed communication. The stream encryption method is an encryption of a data stream by performing an exclusive OR operation on a pseudo random number output from a pseudo random number generator with the data stream in 1-bit units. That is, in a general stream encryption device, as shown in FIG. 4, an exclusive OR operation circuit 5 is connected between an input terminal 1 and an output terminal 3 of a data stream, and the exclusive OR operation circuit 5 is The output of the pseudo-random number generator 7 is connected to the other input. An input terminal 9 and a clock input terminal 11 are connected to the pseudo random number generator 7, and an initial value and a clock signal are input. FIG. 5 is a non-linear filter generator (Nonlinear Filter Generator) which is an example of a conventional pseudo-random number generator.
(tor) is a block diagram. As shown in FIG.
This nonlinear filter generator has an input terminal 13
And a non-linear conversion function circuit 19 is connected to the linear feedback shift register 17 connected to the clock input terminal 15, and the non-linear conversion function circuit 19 has an output terminal 21.
Are connected. The non-linear filter generator uses a pseudo random number sequence as the output sequence of the non-linear conversion function circuit 19 which receives the respective register values of the linear feedback shift register 17 which operates in synchronization with the clock from the clock input terminal 15.

FIG. 6 shows the configuration of a standard type linear feedback shift register which is one of the linear feedback shift registers. In this standard linear feedback register, as shown in FIG. 6, a plurality (L in this case) of registers 23 and a plurality (L-1 in this case) of exclusive OR operation circuits 25 are connected in series, and A feedback tap 27 is connected between the output of the register 23 and one input of each exclusive OR operation circuit 25. When the number of stages of the linear feedback shift register is ^L , it is known that the maximum period of the output sequence is 2 ^L −1 when focusing on one register, and this sequence is called an m sequence. For example, to generate an m-sequence in the linear feedback shift register shown in FIG. 6, the following is done. In FIG. 6, c ₁ , c ₂ , ..., C _L-1
Is called a feedback tap, and indicates a connection when the tap is 1, and a disconnection when the tap is 0. At this time, the characteristic polynomial of the output sequence of the linear feedback shift register is expressed as follows.

[0004]

[Equation 1] If the above equation is made to be a primitive irreducible polynomial, the linear feedback shift register will generate m sequences. The state of the linear feedback shift register shown in FIG. 6 at time t is

[0005]

[Equation 2] (Where T represents transposition), the state of the linear feedback shift register after one clock input is

[0006]

[Equation 3] If you say,

[0007]

[Equation 4] Is expressed as That is,

[0008]

[Equation 5] Is. Here, T _s is a state transition matrix. Therefore,
The state of the linear feedback shift register after i clocks is, using the power T _s ⁱ of the state transition matrix,

[0009]

[Equation 6] It is expressed as. In addition to the above-mentioned linear feedback shift register, there are a modular type and a hybrid type. These are Laung-Terng Wang, Edward J. Macc
Luskey's paper, "Hybrid Designs Generating Maximum
-Length Sequences, "IEEE Trans.on Computer-Aided D
esign, Vol.7, No.1, January, 1988 etc.

[0010]

However, the conventional non-linear filter generator (Nonlinear Filter G
In the enerator), since the register values of the linear feedback shift register are not independent from each other, the equal frequency of outputs 1 and 0 is not guaranteed and the random number characteristic is poor. If a combination generator (CombinationGenerator) is used as the pseudo-random number generator, 0,
The equal frequency of 1 can be guaranteed. FIG. 7 is a schematic configuration diagram of the combination generator. Figure 7
As shown in, when the combination generator is configured such that each linear feedback shift register 31 is connected to the non-linear conversion function circuit 29, and the greatest common divisor of the period of each linear feedback shift register 31 is one. Moreover, the output sequence of each linear feedback shift register 31 can be regarded as independent.
Further, if the equal frequency of 1 and 0 in the output of each linear feedback shift register 31 is guaranteed, the input to the non-linear conversion function circuit 29 can be regarded as a completely random sequence. No matter how biased the appearance frequencies of 1 and 0 are, a random sequence and a sequence obtained by performing an exclusive OR operation for each bit are random sequences. Therefore, in the above combination generator,
The non-linear conversion function circuit 29 in which 0 has an equal frequency may be configured to perform an exclusive OR operation on at least one input and the non-linear conversion values of the remaining inputs. That is, the nonlinear transfer function is

[0011]

[Equation 7] It will be good to do. Where x _i , f, g ∈
It is {0,1}. However, when trying to increase the encryption strength when using the above combination generator, many feedback registers must be prepared,
There is a drawback in that the hardware configuration is larger than that of the above non-linear filter generator. The present invention has been made in view of the above circumstances, and provides a filter generator as a pseudo-random number generator capable of ensuring an equal frequency of outputs 1 and 0 and obtaining good random number characteristics. With the goal.

[0012]

In order to achieve the above object, the present invention is a pseudo-random number generator for generating pseudo-random numbers used in a cryptographic communication device or the like, wherein the m-sequence operates in synchronization with a clock. , A non-linear conversion function means for non-linearly converting each register value of the linear feedback shift register to obtain a 1-bit output, and an initial value setting means for setting an initial value in the linear feedback shift register. When at least one linear feature other than the final stage of the register value of the one linear feedback shift register even small <br/> no other than the final stage of the linear feedback shift register
It is characterized by comprising an exclusive OR operation means for performing an exclusive OR operation on the non-linear conversion values of the register values of the remaining linear feedback shift registers except the feedback shift register and outputting it as a pseudo random number. Another feature of the present invention is a pseudo-random number generator for generating pseudo-random numbers used in a cryptographic communication device or the like, and a linear feedback shift register for generating an m-sequence that operates in synchronization with a clock, and the linear feedback shift register. Linear conversion means for linearly converting and outputting each register value of the shift register, nonlinear conversion means for nonlinearly converting the linear conversion value and outputting 1 bit, and initial value setting for setting an initial value in the linear feedback shift register The non-linear conversion means performs an exclusive OR operation of at least 1-bit output of the linear conversion means with the non-linear conversion value of the remaining linear conversion means, and outputs the pseudo-random number. The linear conversion means can be expressed by the power of the state transition matrix of the linear feedback shift register.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on the illustrated embodiments. FIG. 1 is a configuration diagram showing an embodiment of a non-linear filter generator as a pseudo-random number generator according to the present invention. As shown in FIG. 1, this non-linear filter generator includes an L-stage linear feedback shift register 33 for generating an m sequence, a nonlinear conversion function circuit 35 connected to the linear feedback shift register 33, and the nonlinear conversion function circuit. 35, exclusive OR circuit 3 connected between the output terminal 37 and the output terminal 37
9 and the output of at least one stage 33a of the L-stage linear feedback shift register 33 is connected to the other input of the exclusive OR arithmetic circuit 39. An input terminal 41 for inputting an initial value is connected to the L-stage linear feedback shift register 33. Next, the operation of the non-linear filter generator will be described.

Register values from registers other than the predetermined one-stage register 33a of the L-stage linear feedback shift register 33, which is set to an initial value from the input terminal 41 and performs a shift operation, are input to the non-linear conversion function circuit 35. Input and non-linear conversion. Then, with respect to the non-linear conversion value from the non-linear conversion function circuit 35, the exclusive OR calculation circuit 39 performs an exclusive OR operation on the register value from the predetermined one-stage register 33a, and outputs the pseudo random number sequence as the pseudo random number sequence. Output from the terminal 37. Next, the equal frequency of 1s and 0s in the output of the non-linear filter generator having the above configuration will be described. Let each register value of the L-stage linear feedback shift register 33 be s
Let ₁ , s ₂ , ..., s _L, and generate m sequences. However, s _i ε {0, 1}. Then, since this linear feedback shift register 33 has a period of 2 ^L −1, (s ₁ , s ₂ , ...,
s _L ) ≠ (0,0, ..., 0) All states are taken once. And the nonlinear function is

[0015]

[Equation 8] Can be expressed as Here, x _i = s _a , (1 ≦ i ≦ n), where 1 ≦ a ₁ <a ₂ <... <a _n ≦ L. Also,
f, gε {0,1}. In one cycle of the linear feedback shift register 33, the input to the nonlinear function (x _1, ..., x _n) are (0, ..., 0) and various non every 2 ^Ln times, (0, ..., 0 ) Is 2 ^Ln -1 times. If the various occurrence probabilities at (x ₁ , ..., X _n ) are the same, the appearance probabilities of 1 and 0 at the output of the non-linear filter generator are equal. this is,
If the various occurrence probabilities at (x ₁ , ..., X _n ) are the same, the input (x ₁ , ..., X _m-1 , x _{m + 1} , x _n to g is input to g.
Is a certain value, x _m takes 1 and 0 with equal frequency. However, in reality, (x ₁ , ..., x _n )
In (1), (0, ..., 0) is once less than in other values. Therefore, the value of f (0, ..., 0) is reduced by one time. From the above, if z ₀ = f (0, ..., 0), the output becomes z ₀ in 2 cycles of the linear feedback shift register, and the output becomes 2 ^Ln −1 times.

[Equation 9] Is 2 ^Ln times. If L is sufficiently large, 1 of the output of the above non-linear filter generator,
It can be considered that the appearance probabilities of 0 are equal. Next, a specific example of the non-linear filter generator shown in FIG. 1 will be described. FIG. 2 is a configuration diagram of a specific example of the non-linear filter generator shown in FIG. As shown in FIG. 2, in this non-linear filter generator, the linear feedback shift register 43 has four stages of D-type flip-flops 45 to 51, the output of the fourth-stage D-type flip-flop 51, and the first-stage D-type flip-flop 51. A first exclusive OR circuit 53 for performing an exclusive OR operation with the output of the flip-flop 45 and outputting the result to the first-stage D-type flip-flop 45, and each of the D-type flip-flops. An input terminal 55 for setting an initial value and a clock terminal 57 for inputting a clock signal are connected to 45 to 51. Then, the non-linear conversion function circuit 59 of this non-linear filter generator logics the value set in the D-type flip-flop 45 in the first stage and the value set in the D-type flip-flop 51 in the fourth stage. It has a logical product arithmetic circuit 61 for performing a product arithmetic operation, and the exclusive OR operation of the output of the logical product arithmetic circuit 61 and the output of the D-type flip-flop 47 of the second stage is the second exclusive operation. It is applied by the logical OR operation circuit 63 and output from the output terminal 65.

Next, the operation of the above non-linear filter generator will be described. First, the D-type flip-flop 45 in the linear feedback shift register 43
Up to 51 are set to initial values through the input terminal 55. If there is a clock input from the clock terminal 57,
The values stored in the D-type flip-flops 45 to 49 are set in the D-type flip-flops 47 to 51, respectively, and the first-stage D-type flip-flop 45 is set in the first-stage D-type flip-flop 45. Is set to the exclusive OR value of the value stored in the fourth stage D-type flip-flop 51. The non-linear conversion function circuit 59 (logical product operation circuit 61) is set in the D-type flip-flop 45 of the first stage and the D-type flip-flop 51 of the fourth stage among the outputs of the registers of the linear feedback shift register 43. The logical product value of the existing values is output, and the value obtained by performing the exclusive OR operation of the logical product value and the value set in the D flip-flop 47 of the second stage is output from the output terminal 65. Therefore, if 1 is set to all the D-type flip-flops 45 to 51 as an initial value, the output sequence appearing at the output terminal 65 is 0, 1, 1, 1, 0, 0, 1, 0, 1 , 1, 0,
It can be seen that 0,0,1,1 is repeated, and the appearance probabilities of 1,0 can be considered equal.

Next, a modification of the specific example shown in FIG. 2 will be described with reference to FIG. The nonlinear filter generator shown in FIG. 3 is equivalent to that shown in FIG. That is, as shown in FIG. 3, in this nonlinear filter generator, the linear feedback shift register 67 has four stages of D-type flip-flops 69 to 7.
An exclusive OR operation of the outputs of the fifth and fourth D-type flip-flops 75 and the output of the first-stage D-type flip-flop 69 is performed, and the result is output to the first-stage D-type flip-flop 69. And an exclusive OR circuit 77 of 1,
An input terminal 79 for setting an initial value and a clock terminal 81 for inputting a clock signal are connected to each of the D-type flip-flops 69 to 75. Then, the non-linear conversion function circuit 83 of the non-linear filter generator excludes the value set in the D-type flip-flop 69 in the first stage and the value set in the D-type flip-flop 75 in the fourth stage. Second exclusive OR circuit 85 for performing logical OR operation, and the third-stage D-type flip-flop 7
3 has a logical product operation circuit 87 for performing a logical product operation of the value set to 3 and the output of the second exclusive OR operation circuit 85, and the output of the logical product operation circuit 87. And an output of the D-type flip-flop 69 of the first stage is subjected to an exclusive OR operation by the third exclusive OR operation circuit 89 and output from the output terminal 91. Therefore, if 1 is set to all of the D-type flip-flops 69 to 75 as an initial value, the output sequence appearing at the output terminal 91 is 1,1,1,0,0,1,0,1,1. , 0,
The sequence is 0, 0, 1, 1, 0, which is the same sequence because the sequence appearing at the output terminal 65 of the nonlinear filter generator shown in FIG. 2 is a sequence delayed by one clock.

It will be shown below that the non-linear filter generator shown in FIG. 3 is made by equivalent conversion of the non-linear filter generator shown in FIG. In FIG. 2, the register value of the first D-type flip-flop 45 at time t is represented by s (t). Then, the D-type flip-flop 47 of the second stage is s (t-
1) and the D-type flip-flops 49 in the third stage and the D-type flip-flops 51 in the fourth stage are s (t-
2), s (t-3). Therefore, the output terminal 65
The output at time t that appears in

[0019]

[Equation 10] Becomes Here, the linear feedback shift register 4
From the structure of 3,

[0020]

[Equation 11] The following relationship holds. Similarly, in FIG. 3, the register value of the first-stage D-type flip-flop 69 at time t is

[0021]

[Equation 12] The output at the time t appearing at the output terminal 91 is

[0022]

[Equation 13] From the structure of the linear feedback shift register 67,

[0023]

[Equation 14] Holds. Since the output appearing at the output terminal 91 is delayed by one clock with respect to the output appearing at the output terminal 65, s (t)

[0024]

[Equation 15] In between

[0025]

[Equation 16] There is a relationship. If this is substituted into the above equation (6),

[0026]

[Equation 17] To get Also, with the relationship of the above formula (7)

[0027]

[Equation 18] By combining and substituting in equation (8),
You can get the formula. Therefore, it can be seen that the non-linear filter generator shown in FIG. 3 is made by equivalent conversion of the non-linear filter generator shown in FIG. FIG. 8 is a generalized expression of the present invention including the above-described modified embodiment. In the figure,
The same components as those in FIG. 1 are denoted by the same reference numerals. 8 is different from FIG. 1 in that the linear conversion circuit 100 represented by the power T _s ⁱ of the state transition matrix T _s of the linear feedback shift register 33 is provided between the linear feedback shift register 33 and the nonlinear conversion circuit 35. It is in the place where I placed it. As described above, the output of the linear conversion circuit 100 represented by the power T _s ⁱ of the state transition matrix T _s of the linear feedback shift register 33 in FIG. Since they are shifted, it can be considered that the appearance probabilities of 1,0 in the output of the non-linear filter generator shown in FIG. 8 are also the same as in the non-linear filter generator shown in FIG. For example, when the configuration of FIG. 3 is expressed based on FIG. 8, it becomes as shown in FIG. In the figure, 101
Is a linear conversion circuit. The state transition matrix T _s of the linear feedback shift register 67 at this time is

[0028]

[Formula 19] And the linear conversion circuit 101 is a power of T _s . In this example, T _s ¹ = T _s . The state of the linear feedback shift register 67 is

[0029]

[Equation 20] And the output of the linear conversion circuit 101 is

[0030]

[Equation 21] If you say,

[0031]

[Equation 22] That is,

[0032]

[Equation 23] Since it can be expressed as,

[0033]

[Equation 24] To get Therefore, in the case of FIG. 3, the linear conversion circuit is expressed as shown in FIG.

[0034]

As described above, the present invention inputs each register value of the linear feedback shift register which operates in synchronization with the clock input to the non-linear conversion function circuit,
In a configuration in which a pseudo random number is output for each clock, at least one register value of the linear feedback shift register is subjected to exclusive OR operation with the non-linear conversion values of the remaining several registers. In the case where each register value of the shift register is input to the linear conversion circuit and the output linear conversion value is input to the non-linear conversion circuit, at least one bit output of the linear conversion output is converted into some remaining linear outputs. Since the non-linear conversion value of the conversion output is subjected to the exclusive OR operation, it is possible to provide a pseudo-random number generator having good random number characteristics in which 1 and 0 appear at equal frequency.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a non-linear filter generator as a pseudo-random number generator according to the present invention.

FIG. 2 is a configuration diagram of a specific example of the non-linear filter generator shown in FIG.

FIG. 3 is a configuration diagram of a modified example of the nonlinear filter generator shown in FIG.

FIG. 4 is a configuration diagram of a general stream encryption device.

FIG. 5 is a configuration diagram of a non-linear filter generator that is an example of a conventional pseudo-random number generator.

FIG. 6 is a configuration diagram of a general standard linear feedback shift register.

FIG. 7 is a configuration diagram of a combination generator that is an example of a conventional pseudo-random number generator.

FIG. 8 is an explanatory diagram according to the present invention.

FIG. 9 is an explanatory diagram according to the present invention.

[Explanation of symbols]

1 ... Plaintext input terminal, 3 ... Ciphertext output terminal, 5, 39, 53, 63, 77, 85, 89 ...
Exclusive OR operation circuit, 7 ... Pseudo random number generator, 9, 1
3, 41, 55, 79 ... Initial value setting terminals, 11, 1
5, 57, 81 ... Clock input terminals, 17, 33, 4
3, 67 ... Linear feedback shift register, 19,
29, 35, 59, 83 ... Non-linear conversion function circuit 21,
37, 65, 91 ... Pseudo-random number output terminals, 23, 45-5
1, 69 to 75 ... D-FlipFlop element, 25 ... Exclusive OR operation element, 31 ... Linear feedback shift register, 61, 87 ... AND operation circuit,

Continuation of the front page (56) References JP-A-63-294115 (JP, A) Koichi Sugimoto et al., A method for constructing a secure Filter Generator, Proceedings of the 1998 IEICE General Conference, Nihon, Denshi The Institute of Information and Communication Engineers, 1998, Basics / Boundaries, A-7-12, p. 241 LAUNG-TERNG WANG, Hybrid Designs Generating Maximum-Length Sequences, IEEE ETRANSACTIONS ON COMPUTER-AIDED DES IGN, May 1988, IEE. 7, No. 1, P. 91- 99 (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 7/58

Claims (2)

(57) [Claims] 1. A pseudo-random number generator for generating a pseudo-random number used in a cryptographic communication device or the like, comprising: a linear feedback shift register for generating an m sequence that operates in synchronization with a clock; and the linear feedback shift register. Non-linear conversion function means for non-linearly converting each register value to obtain a 1-bit output, initial value setting means for setting an initial value in the linear feedback shift register, and a small number of elements other than the last stage in the linear feedback shift register. register values of at least one linear feedback shift register to at least one linear feed other than the last stage
Pseudo-random number generator characterized by comprising exclusive-OR operation means for performing exclusive-OR operation and outputting as pseudo-random numbers with the non-linear conversion value of the register value of the remaining linear feedback shift register excluding the back shift register apparatus. " 2. A pseudo-random number generator for generating a pseudo-random number used in a cryptographic communication device or the like, comprising: a linear feedback shift register for generating an m sequence that operates in synchronization with a clock; and the linear feedback shift register. Linear conversion means for linearly converting and outputting each register value,
It comprises a non-linear conversion means for non-linearly converting the linear conversion value and outputting 1 bit, and an initial value setting means for setting an initial value in the linear feedback shift register, the non-linear conversion means being equivalent to the linear conversion means. An output of at least 1 bit is subjected to exclusive OR operation with the non-linear conversion value of the remaining linear conversion means and output as a pseudo random number, and the linear conversion means should be the state transition matrix of the linear feedback shift register. A pseudo-random number generator characterized in that it can be expressed.