JP3532292B2 - Digital signal receiving circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal receiving circuit for performing waveform shaping by slicing a digital signal input from a digital signal communication line through a coupling capacitor with a set threshold value.

[0002]

2. Description of the Related Art Conventionally, for example, an input is made from a communication line.
Waveform shaping of a digital signal is performed as shown in FIG.
It is done in the slice circuit of the part. In the figure, a receiving unit 101
For example, NRZ (non
return to zero) digital signal via line 103
Has been entered. Then, with the output terminal of the transmitter 102
When the DC potential of the input terminal of the receiver 101 is different,
DC is provided by providing a coupling capacitor C in the input section of the receiving section 101.
The component is cut off, and the input digital signal S_DIs
Through the coupling capacitor C, a sludge having an inverting amplification function is provided.
It is input to the chair circuit 104. Turning on the slice circuit 104
Bias voltage value V on the force side via resistor R _DCDC voltage of
Is supplied to the slice circuit 104 and is input to the slice circuit 104.
Lyser input signal S_SIIs the bias voltage value V_DCTo the same value as
Set threshold voltage value V_THWaveform is sliced by
Done. Slicer output signal S of slice circuit 104_So
Is output from the receiving unit 101, and the signal processing unit 105 and P
Input to LL (Phase Lock Loop) circuit 106
It In the PLL circuit 106, a rectangular wave slicer output signal
S_SoClock signal C synchronized with the edge of_KGenerate
Clock signal C_KIs input to the signal processing unit 105, and
In the signal processing unit 105, the clock signal C_KBased on
Is output signal S_SoExtract the necessary data from the
No. processing is executed.

As shown in FIG. 9A, noise is mixed in the digital signal S _D input to the receiving unit 101 as it passes through the line 103, resulting in a signal having a deteriorated S / N ratio. When the signal is continuously output, the slicer input signal S that has passed through the coupling capacitor C
_A bias voltage value V _DC is an intermediate value between the high level and the low level of _SI . Therefore, as shown in FIG. 9B, by slicing the slicer input signal S _SI with the bias voltage value V _DC , the waveform is shaped and noise is removed from the slice circuit 104 as shown in FIG. 9C. The rectangular wave slicer output signal S _So is extracted.

[0004]

However, in the above-mentioned conventional example, as shown in FIG. 10, when the digital signal S _D is in the non-input state and remains in the low level for a long time, the slicer input signal S _SI goes low. The level potential is
Based on the discharge characteristic of the time constant CR determined by the coupling capacitor C and the resistor R, the bias voltage value V _DC is gradually approached.
After the elapse of the time constant CR, the low-level potential of the slicer input signal S _SI becomes substantially equal to the bias voltage value V _{DC, that} is, the threshold voltage value V _TH . At this time, the slice circuit 104 is sensitive to the noise mixed in the line 103, and the slicer circuit 104 outputs the slicer output signal S _So in which the noise is amplified. Therefore, the signal processing unit 10 in the subsequent stage
No. 5 operates based on a noise component, which causes a malfunction.

As described above, in the above-mentioned conventional example, if slicing is performed while a low-level no-signal state continues, it is sensitive to noise. Therefore, for example, the threshold of the slicer input signal S _{SI in} FIG. 10 is set to a high value like the threshold voltage value V _TH 'shown by the broken line so as not to be sensitive to noise, thereby lowering the sensitivity of the waveform shaping action of the slicer circuit 104. When the riser and the fall of the slicer input signal S _SI waveform are not steep, the high-level and low-level pulse widths of the slicer output signal S _So after waveform shaping may change, and the duty ratio may change. Therefore, the original signal waveform shaping capability of the slice circuit 104 is reduced.
Therefore, even when generating a clock signal C _K in synchronization with the slicer output signal S _So. the PLL circuit 106, the duty ratio of the slicer output signal S _So. changes, the PLL circuit 10
When the tracking performance of 6 is inferior, the slicer output signal S _So and the clock signal C _{K have out-} of-phase edges, and the signal processing unit 105 causes the slicer output signal S _{So to have} a high level and a low level based on the clock signal C _K. When detecting
It may malfunction.

Therefore, the present invention solves the above-mentioned problems, does not respond to noise even when the no signal state of the input signal continues, and performs waveform shaping without lowering the signal waveform shaping ability when there is a signal. It is an object of the present invention to provide a digital signal receiving circuit capable of performing the above.

[0007]

In order to achieve the above object, a digital signal receiving circuit according to a first aspect of the present invention comprises a waveform shaping means for shaping the waveform of a digital signal input via a coupling capacitor, and a resistance component. In the digital signal receiving circuit of the digital communication line system having the coupling capacitor and the bias setting means for setting the bias value of the connection portion of the waveform shaping means, the no signal state of the output signal of the waveform shaping means is predetermined. No-signal-state detecting means for outputting a no-signal-state signal when it is detected that the signal has continued for a time, and the no-signal-state signal is not input.
If not, the threshold of the waveform shaping means and the bias setting are set.
Set the bias value of the constant means substantially the same value, the when the no-signal state signal is input, by changing at least one value of the bias value of the threshold and the bias setting means before Symbol waveform shaping means, The waveform shaping sensitivity is set to the signalless state.
Sensitivity that is lower than the sensitivity when no signal is input
A degree control means, characterized by comprising a.

[0008] Then, the digital signal receiving circuit according to claim 2, wherein the waveform shaping means includes a field effect transistor for waveform shaping to change the threshold according to the supplied current value, the sensitivity control means It has a constant current circuit for threshold setting and threshold adjustment parallel to one another for supplying a constant current to said field effect transistor in accordance with the control, the sensitivity control means, no signal state of the no-signal condition detecting means When a signal is input, at least the connection of the constant current circuit for adjusting the threshold is changed to change the constant current value supplied to the field effect transistor to change the threshold.

In the digital signal receiving circuit according to a third aspect of the present invention, the waveform shaping means changes the threshold value according to the supplied current value, and a waveform shaping field effect transistor is provided in parallel with the field effect transistor. constructed and the electrolytic effect transistor a channel size between different channel sizes used for waveform shaping of the field effect transistor, a constant current supplying a constant current to one of the field effect transistor in accordance with the control of the sensitivity control means and a circuit, said sensitivity control means, said when no-signal state signal of the non-signal state detecting means is inputted, the target supply the constant current of the constant current circuit, one field effect transistor Is switched to another field effect transistor to change the threshold value.

Furthermore, the digital signal receiving circuit according to claim 4, supply the bias setting means, a resistance unit to generate a bias voltage, a constant current to the resistor portion in response to the control of the sensitivity control means mutually parallel and a constant current circuit for use and bias adjustment bias setting, the sensitivity to
Control means, said when no-signal state signal of the non-signal state detecting means is input, and change the constant current value supplied to the resistance portion by changing the connection of the constant current circuit for at least bias adjustment bias It is characterized in that the voltage value is changed.

[0011] Then, the digital signal receiving circuit according to claim 5, wherein the bias setting means, a resistance portion for parallel bias setting and bias adjustment each other, the control of the sensitivity system <br/> control means depending and a constant current circuit for supplying a constant current to the resistor portion, the sensitivity control means, said when no-signal state signal of the non-signal state detecting means is input, for at least bias adjustment It is characterized in that the resistance value generated in the resistance part is changed by changing the connection of the resistance part to change the bias voltage value.

In the digital signal receiving circuit according to a sixth aspect of the present invention, the signalless state detecting means receives the output signal of the waveform shaping means and a predetermined clock signal, and the clock signal is output when the output signal is not signaled. Is configured by a counter circuit that determines whether or not the number of clocks has been counted by a predetermined value set in advance and detects continuation of a no-signal state for a predetermined time.

Further, in the digital signal receiving circuit according to a seventh aspect of the present invention, the clock signal is an output clock signal of a PLL circuit that generates a clock signal synchronized with the output signal of the waveform shaping means.

[0014]

With the above arrangement, according to the digital signal receiving circuit of the first aspect, the signalless state detecting means detects whether or not the signalless state of the output signal of the waveform shaping means has continued for a predetermined time. and, when detecting this, sensitivity control means, set such that the threshold and the bias value becomes a different value, so as not sensitive to, for example, noise waveform shaping means, the waveform shaping action of the waveform shaping means Sensitivity , no signal
The sensitivity is lower than when no signal is input . Since the threshold value and the bias value are set to substantially the same value before the no-signal state is detected, waveform shaping can be performed with good sensitivity even for a small signal input signal.

According to the digital signal receiving circuit of the second aspect, the waveform shaping means is provided with the respective constant current circuits for threshold setting and threshold adjusting. Then, for example, when there is a signal, the constant current of one of the constant current circuits is supplied to the field effect transistor for waveform shaping, and when there is no signal, both constant currents are supplied simultaneously to increase the supply current.
Alternatively, conversely, both constant currents are supplied to the field effect transistor when a signal is present, and only one constant current is supplied when there is no signal to reduce the supply current, or one constant current circuit The threshold value is raised or lowered by performing control such as switching to a constant current circuit to increase or decrease the supply current.
As a result, there is a difference between the threshold value and the bias voltage value.
The sensitivity of the waveform shaping operation of the waveform shaping means is reduced.

According to another aspect of the digital signal receiving circuit of the present invention, the waveform shaping means has field effect transistors having different channel sizes, and supplies a constant current when the continuation of the no signal state is detected. The field effect transistor to be switched. Since the supplied current is constant and the channel size is different, the threshold value can be raised or lowered. As a result, there is a difference between the threshold value and the bias voltage value, and the sensitivity of the waveform shaping operation of the waveform shaping means is reduced.

Further, according to the digital signal receiving circuit of the fourth aspect, the bias setting means is provided with respective constant current circuits for bias setting and bias adjustment. Then, for example, when a signal is present, the constant current of one of the constant current circuits is supplied to the resistor portion, and when there is no signal, both constant currents are simultaneously supplied to increase the supply current, or conversely, when there is a signal. Both constant currents are supplied to the resistance part, and only one constant current is supplied to reduce the supply current when there is no signal, or the supply current is switched from one constant current circuit to another constant current circuit. The bias voltage value is increased or decreased by performing control such as increasing or decreasing. As a result, there is a difference between the threshold value and the bias voltage value, and the sensitivity of the waveform shaping operation of the waveform shaping means is reduced.

According to the digital signal receiving circuit of the fifth aspect, the bias setting means is provided with a bias setting resistance portion and a bias adjustment resistance portion. When the continuation of the non-signal state is detected, the resistance unit that supplies the constant current is switched. Since the resistance value changes even if the supplied current is constant, the bias voltage can be increased or decreased. As a result, there is a difference between the threshold value and the bias voltage value, and the sensitivity of the waveform shaping operation of the waveform shaping means is reduced.

Further, according to the digital signal receiving circuit of the sixth aspect, when the number of clocks of the clock signal is counted by the counter circuit and the number of clocks is counted by a preset predetermined value, for example, a count-up type When the count value of the counter reaches a predetermined set value and when the preset value of the countdown type counter becomes zero, the counter circuit detects that the no-signal state has continued for a predetermined time.

Further, according to the digital signal receiving circuit of the seventh aspect, the PLL circuit generates the clock signal synchronized with the output signal of the waveform shaping means, and inputs this clock signal to the counter circuit to obtain no signal. It is detected whether the state has continued for a predetermined time.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. A circuit diagram of a first embodiment of a digital signal receiving circuit according to the present invention is shown in FIG. Digital signal receiving circuit 1
Is a slice circuit 2 as a waveform shaping means for shaping a waveform by inputting a digital signal SD inputted through a communication line through a coupling capacitor C, and a bias setting for setting a bias voltage of an input portion of the slice circuit 2. Bias setting circuit 3 as means, slicer output signal SSo of slice circuit 2 and clock signal S of PLL circuit 6 described later.
CK is input, the counter circuit 4 as a no-signal condition detecting means slicer output signal SSo detects whether a no-signal state, sensitivity system changes the threshold value of the slice circuit 2 in accordance with the detection result your RS flip-flop 5 as means
Have and.

Then, output from the digital signal receiving circuit 1.
Forced slicer output signal S_SoIs the PLL circuit 6 and
Is supplied to the signal processing circuit 7 and output from the PLL circuit 6.
Output clock signal S_CKIs a counter circuit 4 and signal processing
It is supplied to the circuit 7. In the PLL circuit 6, the slicer output
Signal S_SoClock signal S that can be synchronized with_CKLive
In the signal processing circuit 7, the clock signal S_CKBased on
Slicer output signal S _SoRetrieve the desired playback signal from
ing.

The slice circuit 2 includes a constant current circuit 2a for outputting a constant current having a current value I _C1 and a constant current circuit 2b configured in parallel with the constant current circuit 2a for outputting a constant current having a current value I _C2.
And a constant current of the constant current circuit 2b is supplied to switch between conduction and non-conduction in accordance with a predetermined switching signal to control the supply of the constant current of the current value I _C2 to the MOS transistor M ₁ , for example, a semiconductor switch. Normally open switch circuit 2
c and the drain current of the current value I _C1 supplied from the constant current circuit 2a flows, and an N-channel M having an inverting amplification action
Has a OS transistor M _1, a gate terminal of the MOS transistor M ₁ is connected to the coupling capacitor C, a source terminal is grounded. The slicer input signal S _SI is input to the gate terminal, and the slicer output signal S _So is output from the drain terminal.

Here, the switch circuit 2c receives a low-level switching signal (suilyzer sensitivity switching signal S _SC ).
Opened state, high level Suilyzer sensitivity switching signal S
Closed by _SC . When the current value I _C2 is added to the current value I _C1 , a logic threshold voltage value that does not cause noise to the MOS transistor M ₁ when the digital signal S _D remains in the non-signal state is obtained, and no signal is present. It is set to a predetermined value so as to obtain a logical threshold voltage value that enables slicing when the state changes to the signaled state.

Then, the MOS transistor M₁Output power
Pressure from low level to high level or high level to low
Logical threshold voltage of the input voltage that becomes the threshold to be inverted to the level
Value V _THIs usually a MOS transistor M₁Formed in
Depending on the width and length of the channel between the drain and source
MOS transistor M specified by₁Size and
Drain current flowing through the channel. That
The constant current circuits 2a and 2b are, for example, their own gates.
A field effect transistor in which the terminal and the source terminal are connected,
A resistor for adjusting the drain current of this field effect transistor
Composed of and.

The bias setting circuit 3 includes a constant current circuit 2a.
Constant current circuit 3 that outputs a constant current with the same current value I _C1 as
a and a drain current having a current value I _C1 from the constant current circuit 3a, and its own gate terminal and drain terminal are connected to each other to form an N-channel MOS transistor M
₂ and a resistor R for supplying a bias, one end of which is connected to the gate terminal of the MOS transistor M ₂ and the other end of which is connected to a connecting portion between the coupling capacitor C and the gate terminal of the MOS transistor M ₁ . . The size of the MOS transistor M ₂ identified by the channel width and length of the MOS transistor M ₂ is set to be identical to the MOS transistor M _1.

Here, the resistance value of the resistor R is set to a value sufficiently smaller than the input resistance value of the MOS transistor M ₁ of the slice circuit 2. As a result, the bias voltage value V _DC generated at both ends of the MOS transistor M ₂ by the constant current of the current value I _C1 is supplied to the gate terminal of the MOS transistor M ₁ via the resistor R with almost the same value.

Then, the MOS transistors M ₁ and M ₂
Of the MOS transistors M ₁ and M ₂ have the same logical threshold voltage value V _TH . Furthermore, MO
Since the gate terminal and the drain terminal of the S transistor M ₂ are connected, the bias voltage value V generated at the drain terminal is
_DC becomes equal to the logical threshold voltage value V _TH . Therefore, in the normal state of the signal present, the logical threshold voltage value V _TH of the MOS transistor M ₁ of the slice circuit 2 and the supplied bias voltage value V _DC are substantially equal to each other, so that the input voltage is at a minute level. Even if there is, a slice circuit that can slice the input signal with the logical threshold voltage value V _TH with good sensitivity is configured.

The counter circuit 4 includes a slicer output signal S _So of the slice circuit 2 and a clock signal S _{CK of the} PLL circuit 6.
And a counter 4a counts up type the reset signal S _R to be described later is inputted, a delay circuit 4b for delaying the slicer output signal S _So., minute pulse width based on the output signal of the delay circuit 4b and the slicer output signal S _So. And an exclusive OR circuit 4c for generating the reset signal S _R.

Here, the counter 4a starts counting based on the clock signal S _CK supplied to the clock terminal CK when the slicer output signal S _So of high level is input to the enable terminal E, The carry terminal C outputs a high-level count-up signal S _CP when the count value equal to a predetermined set value, such as 100, input in advance from a predetermined terminal (not shown) of the counter 4a. Then, when a high-level reset signal S _R is input to the reset terminal R of the counter 4a, the count value is initialized to zero. The predetermined value set in advance at this time depends on the format of the communication system and is higher than the count value counted by the counter 4a during the half cycle of the lowest frequency of the frequency components of the input digital signal S _D. It is set to a large value and is set to a value smaller than the count value counted by the counter 4a during the period determined by the time constant CR of the coupling capacitor C and the resistor R.

The RS flip-flop 5 has a
Count-up signal S of unta 4a _CPGoes into the set terminal
Force and reset signal S_RIs input to the reset terminal
It The output from the Q terminal of the RS flip-flop 5
Elisa sensitivity switching signal S_SCIs supplied to the switch circuit 2c
To be done. Next, the operation of this embodiment will be described with reference to the waveform diagram of FIG.
Explain.

As shown in FIG. 2, the input digital signal S _D is a signal of logic levels “0” and “1” including a DC component, and is in a low level state of “0” when there is no signal.
When the digital signal S _D is continuously input, the DC level is an intermediate value between the high level and the low level of the slicer input signal S _SI that passes through the coupling capacitor C and is input to the slice circuit 2. Therefore, when there is a signal, as shown in FIG. 2, the amplitude of the slicer input signal S _SI is substantially equal above and below the bias voltage value V _DC . Since the bias voltage value V _DC and the logical threshold voltage value V _{TH of the} slicing circuit 2 are substantially the same, the slicer input signal S _SI is sliced at the center of the amplitude, and the waveform of the signal is shaped with good sensitivity. Then, the slicer circuit 2 outputs a rectangular wave slicer output signal S _So.

In the delay circuit 4b and the exclusive OR circuit 4c, a reset signal S _R having a narrow pulse width at the high level is generated every time the slicer output signal S _So is inverted, as shown in FIG. The high-level reset signal S _R resets the counter 4a to zero, and also resets the RS flip-flop 5 to output the low-level slicer sensitivity switching signal S _SC . Then, the switch circuit 2c is held in the open state by the low-level slicer sensitivity switching signal S _SC , and only the drain current of the current value I _C1 flows through the MOS transistor M ₁ of the slice circuit 2.

When the input digital signal S _D continues to have the logical value "0", the low-level potential of the slicer input signal S _SI is based on the discharge characteristic of the time constant CR determined by the coupling capacitor C and the resistor R. The bias voltage value V _DC . At this time, the slicer output signal S _So continues to be in the high level state, and the clock signal S _CK is supplied to the counter 4a by the free running of the PLL circuit 6 even when there is no signal, so the count value of the counter 4a becomes large. Then, the count value reaches a preset value of 100 before the time of the time constant CR elapses, and at this time, the counter 4
The high-level count-up signal S _CP is output from a, and the swimmer sensitivity switching signal S _SC of the RS flip-flop 5 is held at the high level.

As a result, the switch circuit 2c is closed, a current of current value I _C1 + I _C2 flows through the MOS transistor M _1, and the increase of the drain current raises the logical threshold voltage value V _TH by ΔV _TH . Therefore, the slicer input signal S
_{Even if} the low-level potential of _SI gradually approaches the bias voltage value V _DC , the logic threshold voltage value V _TH is increased by ΔV _TH, so that the noise level is prevented from exceeding the logic threshold voltage value V _TH , and the slicer is prevented. Inverted and amplified noise does not appear in the output signal S _So.

After that, when the digital signal S _D is input, the slicer input signal S _SI changes to the logical threshold voltage value V
Since it exceeds _TH , the slicer output signal S _So shifts to the low level. As a result, the reset signal S _R changes to the counter 4
The count value is input to a and initialized to zero, and RS
The swimmer sensitivity switching signal S _SC of the flip-flop 5 is held at a low level. Then, the switch circuit 2c is opened, only the drain current of the current value I _C1 flows through the MOS transistor M _1, and the bias voltage value V _DC of the slice circuit 2 and the logical threshold voltage value V _TH become substantially the same value. ,
Waveform shaping with high sensitivity is performed.

As described above, in the first embodiment, the bias voltage value V _DC of the slice circuit 2 and the logical threshold voltage value V _TH are set to substantially the same value when a normal signal is present,
Even if the input signal is a small signal, the waveform can be shaped with high sensitivity. When the non-signal state continues for a predetermined time, the switch circuit 2c is closed to supply a constant current, and the drain current of the MOS transistor M ₁ is increased to increase the logical threshold voltage value V _TH. The slice circuit 2 is not sensitive to noise when the signal state continues. Therefore, when a signal is present, waveform shaping can be performed without lowering the signal waveform shaping capability, and even if a no-signal state continues, noise is not sensitive and signal processing can be reliably executed.

Since the counter circuit 4 is used to determine the continuation state of the no-signal state, it is suitable for integration into an integrated circuit. In addition, a predetermined value for outputting the count-up signal S _CP from the counter 4a is set as the count value in correspondence with the number of times that one logical value appears consecutively defined in the data format of the digital signal S _D. Therefore, when the logical value “0” or “1” of the digital signal S _D is regulated to continue up to 10 times when there is a signal, the count value to be set is set to a value of 11 or more, It is possible to easily and surely set the count value for determining the signal state.

Further, since the clock signal S _CK of the counter 4a is obtained from the PLL circuit 6, the free-running clock signal S _CK can be obtained even when there is no signal, and a new clock generation circuit is not required. Since it is good, the circuit configuration can be simplified. Next, FIG. 3 shows an example of another circuit configuration of the slice circuit for raising the logical threshold voltage value V _TH as in the first embodiment. As shown in the figure, the slice circuit 2A includes a constant current circuit 2 that outputs a constant current having a current value I _C1.
a, a switch circuit 2d that is a normally closed semiconductor switch, a switch circuit 2e that is a normally open semiconductor switch, and MOS transistors M ₁ and M ₃ that perform inverting amplification. The current output from the constant current circuit 2a is branched, one of the branched currents is input to the drain terminal of the MOS transistor M ₁ via the switch circuit 2d, and the other is MO via the switch circuit 2e.
It is configured to be input to the drain terminal of the S transistor M ₃ . And each gate terminal is connected to each other,
Each source terminal is grounded.

[0040] to the switch circuit 2d and 2e, the above embodiment and the high level at the time of continuation of the no-signal state becomes a low level when the signal present similarly Suiraisa sensitivity switching signal S _SC is supplied from the RS flip-flop 5. The switch circuits 2d and 2e are in a closed state and an open state, respectively, when the slyizer sensitivity switching signal S _SC is at a low level,
On the other hand, when the level is high, the open state and the closed state are set. The channel size of the MOS transistors M ₁ and M ₃ is larger than that of the MOS transistor M ₃ . Therefore, the logic threshold voltage value V _TH becomes higher in the MOS transistor M ₃ .

In this embodiment, when the signal is present, the MOS transistor M ₁ is in the operating state, and the bias voltage value V _DC and the logical threshold voltage value V _TH are almost the same, so that the waveform shaping with high sensitivity can be performed. When the no-signal state continues for a predetermined time, the operation is switched to the MOS transistor M ₃ and the logical threshold voltage value V _TH rises.
The sensitivity of waveform shaping is reduced, and signal processing can be executed without being sensitive to noise. In this embodiment, since the drain current is not increased when there is no signal, the increase in power consumption can be suppressed.

In addition to the above-mentioned respective embodiments, a configuration for increasing the logical threshold voltage value V _TH may be as follows. In the embodiment of FIG. 1, the switch circuit 2c is closed to supply the constant current of the current value I _C2 additionally when there is no signal. However, for example, as shown in FIG. 4, the current value is the current of the constant current circuit 2a. Constant current circuit 2 that outputs a current value I _C2 'greater than the value I _C1
b ′ is provided, and when there is a signal, the current value I _C1 is supplied from the constant current circuit 2a via the switch circuit 2f to the MOS transistor M.
₁ to supply the current value I _C2 'from the constant current circuit 2b' to the MOS transistor M ₁ by switching the switch circuit 2f by the slyizer sensitivity switching signal S _SC in the no-signal state, and the logical threshold voltage value V _TH may be increased by ΔV _TH .

Further, in each of the above embodiments, the logic threshold voltage value V _TH is raised so as to be insensitive to noise in the non-signal state, but the logic threshold voltage value V is reversed.
_{Even if TH} is lowered below the bias voltage value V _DC , the waveform shaping sensitivity can be lowered, and the slicer output signal S _So is fixed at a low level, so that it is possible to make it insensitive to noise. For example, in FIG. 1, the switch circuit 2
When c is a normally closed switch, the switch circuit 2c is opened to release the parallel circuit when there is no signal and the current supplied to the MOS transistor M ₁ is reduced to lower the logical threshold voltage value V _TH . Further, as in the case of FIG. 4, the changeover switch may be used to reduce the supply current in the no signal state.

Next, a second embodiment according to the present invention will be described based on the circuit diagram of FIG. The same components as those in the first embodiment are designated by the same reference numerals. In the second embodiment, when the no-signal state continues for a predetermined time, the logic threshold voltage value V _TH is kept constant and the bias setting circuit 3A is kept.
The bias voltage value V _{DC of} is reduced by a predetermined value so as not to be sensitive to noise.

In the second embodiment, the slice circuit 2 and the bypass circuit are
Instead of the ass setting circuit 3, the slice circuit 2A and the bypass circuit
An ass setting circuit 3A is provided. The slice circuit 2A is
Current value I_C1Constant current circuit 2a for outputting the constant current of
S transistor M₁Composed of and. And bahia
Current setting value I_C3Constant current that outputs the constant current of
Current circuit 3b and current value I_C3The constant current of the drain current
Is always supplied and acts as a resistance portion as in the first embodiment.
The MOS transistor to which the resistor R for bias supply is connected.
Dista M₂And the current value I_C2Constant current output to output the constant current of
The constant current of the constant current circuit 3c is supplied to the path 3c,
Suilyzer sensitivity switching signal supplied from lip flop 5.
Issue S_SCDepending on the, the MOS transistor can be switched between conductive and non-conductive.
Register M ₂Current value I_C2Control the constant current supply of
For example, a normally closed switch circuit composed of semiconductor switches
And the path 3d. The switch circuit 3d has a signal
Sometimes low level Suilyzer sensitivity switching signal S_SCSupplied by
Is closed, and when there is no signal, high level
Leu Sui Lisa Sensitivity Switching Signal S_SCIs supplied and open
Become. And the current value I_C2＋ I_C3Is the current value I_C1When
It is set to be the same. Except these points
The second embodiment has the same configuration as the first embodiment of FIG.
There is.

Next, the operation of the second embodiment will be described with reference to the waveform diagram of FIG.
It will be described with reference to FIG. When there is a signal, the bias setting circuit 3
A MOS transistor M₂Current value I _C2＋ I_C3The de
A rain current flows, and as in the first embodiment, the MOS transistor is
Dista M₁Bias voltage value V_DCAnd the logical threshold voltage value V_TH
Are set to be almost the same, and sensitive waveform shaping is performed.
It Then, the input digital signal S_DIs a logical value "0"
The state continues and the count value of the counter 4a is preset.
When the value of 100 is reached, RS flip-flop 5 outputs
Level Soil Slicer Sensitivity Switching Signal S_SCIs output,
The switch circuit 3d is opened.

As a result, the MOS transistor M₂To
Is the current value I_C3Drain current of the
Bias voltage value V_DCIs ΔV_DCdescend.
Therefore, the slicer input signal S_SIThe low-level potential of
Logical threshold voltage value V_THBias voltage V_DC
ΔV_DCAs the noise level decreases, so does the noise level.
Therefore, the noise level is the logical threshold voltage value V_THTo exceed
Is avoided and the slicer output signal S_SoNo noise appears in
Yes. Then, after this, the digital signal S_DIs entered
And the slicer output signal S_SoGoes to low level, cow
Input 4a is reset to zero and RS flip-flop 5
Suilyzer sensitivity switching signal S_SCIs held low
It As a result, the MOS transistor M₂In the current
Value I_C2＋ I _C3Drain current flows again, and the slice circuit
Bias voltage value V of 2_DCAnd the logical threshold voltage value V_THIs almost the same
The value becomes 1, and waveform shaping with high sensitivity is executed.

As described above, in the second embodiment, the bias voltage value V _DC of the slice circuit 2 is normally applied when a signal is present.
And the logical threshold voltage value V _TH are set to substantially the same value, so that the waveform shaping with high sensitivity can be performed. And
When the non-signal state continues for a predetermined time, the switch circuit 3d is opened, the drain current of the MOS transistor M ₂ is reduced, and the bias voltage value V _DC is reduced. Therefore, when the non-signal state continues, the slice circuit 2 Is not sensitive to noise. Therefore, when a signal is present, waveform shaping can be performed without deteriorating the signal waveform shaping capability, and even if a no-signal state continues, noise is not sensitive and signal processing can be reliably executed.

Besides having the same effect as the first embodiment, in the second embodiment, the drain current of the MOS transistor M ₂ is reduced when the no-signal state continues for a predetermined time. Further power saving can be achieved. Further, since the bias voltage value V _DC is lowered, the charging time when returning to the signal state is shortened, and the median of the upper and lower amplitudes of the slicer input signal S _SI is promptly the same as the bias voltage value V _DC. It becomes a value, and the time until the duty ratio of the slicer output signal S _So becomes stable can be shortened.

Next, FIG. 7 shows an example of another circuit configuration of the slice circuit for lowering the bias voltage value V _DC as in the second embodiment. As shown in the figure, the slice circuit 2A
Is configured the same as the slice circuit of the second embodiment of FIG. 5, the bias setting circuit 3B includes a constant current circuit 3a for outputting a constant current of a current value I _C1, a constant current is the drain current of the current value I _C1 The MOS transistor M ₂ to which the bias resistor R is connected and the conduction and non-conduction in accordance with the swimmer sensitivity switching signal S _SC of the RS flip-flop 5 are always supplied as. A normally open switch circuit 3e composed of, for example, a semiconductor switch that can be switched, and a constant current output from the constant current circuit 3a are input via the switch circuit 3e, and their gate terminals and drain terminals are connected to each other to provide a predetermined value. MOS that constitutes the resistance part
And a transistor M ₄ .

In this embodiment, the MOS transistor M ₁
By setting the channel size and the drain current value of M ₂ and M ₂ to be the same, the logical threshold voltage value V _TH and the bias voltage value V _DC become substantially the same value. Then, when the no-signal state continues for a predetermined time, the high-level swimmer sensitivity switching signal S _SC is output from the RS flip-flop 5, and the switch circuit 3e is closed, the MOS transistor M
₂ and M ₄ have a parallel resistance configuration, and the bias voltage value V
_DC drops. As a result, like the second embodiment,
When a signal is present, waveform shaping can be performed without lowering the signal waveform shaping ability, and signal processing can be performed without being sensitive to noise even when a no-signal state continues.
Further, since the current does not increase, it is possible to suppress the increase in power consumption.

In the second embodiment shown in FIG. 5,
A parallel circuit is configured to change the constant current supplied to the MOS transistor M ₂ for setting the bias voltage.
Similar to the current switching described in (1), the constant current circuit may be switched by the changeover switch to reduce the constant current value and reduce the bias voltage value in the no signal state. In addition, the second of FIG.
Also in the embodiment, the resistance value of the resistance portion may be decreased by the changeover switch.

In the second embodiment shown in FIGS. 5 and 7, the bias voltage value V _DC is lowered so as to be insensitive to noise, but conversely, even if the bias voltage value V _DC is raised. , The slicer output signal S _So is fixed at a low level, so that it can be made insensitive to noise.
For example, in FIG. 5, a switch circuit 3d that is normally open when a signal is present is used, and the switch circuit 3d is closed when there is no signal to form a parallel circuit, increasing the current flowing through the MOS transistor M ₂ and increasing the bias voltage. Let Further, the constant current is switched by the changeover switch to increase the constant current value when there is no signal. Then, in FIG. 7, the switch circuit 3e is a normally closed switch to release the parallel circuit in the no-signal state to increase the resistance value of the resistor portion and increase the bias voltage.

In each of the first and second embodiments, the counter circuit 4 detects whether or not the no-signal state has continued for a predetermined time, but the present invention is not limited to this. , Using an integrator circuit, charging with the slicer output signal S _So and discharging with the reset signal S _R , the comparing circuit determines whether or not the charging voltage has reached a predetermined value, and the no-signal state continues for a predetermined time. It may be configured to detect whether or not it is done.

In each of the first and second embodiments, the clock signal S _CK of the counter 4a is _supplied to the PLL circuit 6.
I got more, but provided an oscillation circuit of a predetermined oscillation frequency,
The counter 4a may be operated using this oscillation clock. In this case, since the clock frequency can be set arbitrarily, the count value until the count up can be reduced, and the configuration of the counter can be reduced.

[0056]

As described above, in the invention according to claim 1, the signalless state detecting means for detecting whether or not the signalless state continues for a predetermined time and the substantially same value depending on the detection result. and changing at least one value of the set threshold value and the bias value and a sensitivity control means for controlling the sensitivity of the waveform shaping on. Therefore, when the no-signal state continues for a predetermined time, the sensitivity of waveform shaping is lowered and the waveform shaping means is insensitive to noise having a low signal level, for example. Since the threshold value and the bias value are set to the same value in the signal presence state, waveform shaping can be performed without lowering the signal waveform shaping capability, and signal processing can be reliably performed.

In the invention according to claim 2,
The waveform shaping means is provided with a field effect transistor and a constant current circuit for threshold setting and threshold adjustment, and when the continuation of the no signal state is detected, the threshold value is changed by changing the current supplied to the field effect transistor. is doing. For this reason, the threshold value can be changed with a simple configuration by increasing or decreasing the drain current, and thereby, it becomes possible to easily achieve a reduction in the sensitivity of waveform shaping in the no-signal state.

Further, in the invention according to claim 3, the field effect transistors having different channel sizes are switched and waveform shaping is performed in response to the detection of the continuation of the non-signal state. Therefore, the threshold can be changed with a simple configuration,
It is possible to easily reduce the sensitivity of waveform shaping.
Further, since the drain current to be supplied may be constant, it is possible to suppress an increase in power consumption.

Further, in the invention according to claim 4,
The bias setting means is provided with a resistance section and a constant current circuit for bias setting and bias adjustment, and when continuation of a no-signal state is detected, the current supplied to the resistance section is changed to change the bias voltage value. Have changed. Therefore, it is possible to change the bias voltage value with a simple configuration by increasing or decreasing the supply current, and thereby it is possible to easily achieve a reduction in the sensitivity of waveform shaping in the no-signal state.
In particular, when the supply current is reduced, the bias voltage is reduced, so ideal reduction in sensitivity can be performed, and reduction in power consumption can be achieved.

In the invention according to claim 5,
The bias setting means is provided with a bias setting and bias adjusting resistance section and a constant current circuit, and when continuation of a no-signal state is detected, the resistance section is changed to change the resistance value to change the bias voltage value. Have changed. Therefore, it is possible to change the bias voltage value with a simple configuration by increasing or decreasing the resistance value, and thus it is possible to easily achieve a reduction in the sensitivity of waveform shaping in the no-signal state. Further, since the supply current to the resistance portion is not increased, the increase in power consumption can be suppressed.

In the invention according to claim 6, the counter circuit detects whether or not the no-signal state has continued for a predetermined time. Therefore, it is suitable for an integrated circuit, and the circuit board can be downsized. Then, since the counter circuit determines whether or not there is no signal, it is possible to easily and surely confirm the signalless state in accordance with the continuous standard of "0" or "1" of the data format of the input digital signal. It is possible to set the count value for the determination, and it is possible to reliably detect the continuation of the no-signal state for a predetermined time.

Further, in the invention according to claim 7,
Since the clock signal used in the counter circuit is obtained from the PLL circuit, it is possible to obtain the free-running clock signal S _CK even when there is no signal, and it is not necessary to newly prepare a clock generation circuit. It can be simplified.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment according to the present invention.

FIG. 2 is a waveform diagram showing the operation of the first embodiment.

FIG. 3 is a main part circuit diagram showing another example of the first embodiment.

FIG. 4 is a main part circuit diagram showing another example of the first embodiment.

FIG. 5 is a circuit diagram showing a configuration of a second exemplary embodiment according to the present invention.

FIG. 6 is a waveform diagram showing the operation of the second embodiment.

FIG. 7 is a main part circuit diagram showing another example of the second embodiment.

FIG. 8 is a circuit diagram showing a configuration of a conventional example.

FIG. 9 is a waveform diagram showing an operation of a conventional example.

FIG. 10 is a waveform diagram when a no-signal state continues in a conventional example.

[Explanation of symbols]

1 digital signal receiving circuit 2,2A slice circuit (waveform shaping means) 3, 3A, 3B bias setting circuit (bias setting means) 4 counter circuit (no-signal state detecting means) 5 RS flip-flop (sensitivity control means) 6 PLL circuit M _{1 to} M ₄ MOS transistor S _SC Soilizer sensitivity switching signal V _DC bias voltage value V _TH logic threshold voltage value

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-7-58712 (JP, A) JP-A-62-42649 (JP, A) JP-A-4-358443 (JP, A) JP-A-7- 131489 (JP, A) JP-A-8-46494 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 5/08 H04B 1/10 H04L 25/03

Claims (7)

(57) [Claims] 1. A waveform shaping means for shaping a waveform of a digital signal inputted through a coupling capacitor, and a bias setting means for setting a bias value of a connection portion of the coupling capacitor and the waveform shaping means having a resistance component. In a digital signal receiving circuit of a digital communication line system having: a no-signal state detecting means for outputting a no-signal state signal when it is detected that the no-signal state of the output signal of the waveform shaping means continues for a predetermined time. And when the no signal status signal is not input,
Threshold of shape shaping means and bias of the bias setting means
Set the value to substantially the same value, the when the no-signal state signal is input, by changing at least one value of the bias value of the threshold and the bias setting means before Symbol waveform shaping means,
When the signalless state signal is input , the sensitivity of the waveform shaping
Digital signal receiving circuit, characterized in that it and a sensitivity control means for reducing than sensitivity when not. Wherein said waveform shaping means includes a field effect transistor for waveform shaping to change the threshold according to the supplied current value, the constant current to the field effect transistor in accordance with the control of the sensitivity control means the has a constant current circuit for threshold setting and threshold adjustment parallel to one another and supplies the sensitivity control means, when the no-signal state signal of the no-signal condition detecting means is input, at least the threshold value 2. The digital signal receiving circuit according to claim 1, wherein the connection of the adjusting constant current circuit is changed to change the constant current value supplied to the field effect transistor to change the threshold value. 3. The waveform shaping means includes a field effect transistor for waveform shaping, the threshold value of which is changed according to a supplied current value, and a channel size of the field effect transistor, which is configured in parallel with the field effect transistor. a field effect transistor used in a in waveform shaping at different channel sizes, and a constant current circuit for supplying a constant current to one of the field effect transistor in accordance with the control of the sensitivity control means, the sensitivity control Means, when the no-signal state signal of the no-signal state detection means is input, switches the target for supplying the constant current of the constant current circuit from one field effect transistor to another field effect transistor, and sets a threshold value. The digital signal receiving circuit according to claim 1, wherein the digital signal receiving circuit is changed. Wherein said bias setting means, the resistance unit to generate a bias voltage and the sensitivity control means for controlling parallel bias setting and bias adjustment together supplying a constant current to the resistor unit in accordance with the of and a constant current circuit, the <br/> sensitivity control means, when the no-signal state signal of the no-signal condition detecting means is inputted, the connection of the constant current circuit for at least bias adjustment The digital signal receiving circuit according to claim 1, wherein the constant current value supplied to the resistance portion is changed to change the bias voltage value. 5. The bias setting means includes a resistance portion for bias setting and a bias adjustment which are parallel to each other, and
And a constant current circuit for supplying a constant current to the resistor portion in accordance with a control of time control means, the sensitivity control means, when no-signal state signal of the no-signal condition detecting means is inputted To
2. The digital signal receiving circuit according to claim 1, wherein the bias voltage value is changed by changing the resistance value generated in the resistance portion by changing the connection of at least the bias adjusting resistor portion. 6. The signalless state detecting means receives the output signal of the waveform shaping means and a predetermined clock signal,
And a counter circuit that detects whether or not the number of clocks of the clock signal has been counted by a predetermined value set in advance when the output signal is non-signal, and detects whether the no-signal state continues for a predetermined time. The digital signal receiving circuit according to any one of claims 1 to 5. 7. The clock signal is an output clock signal of a PLL circuit that generates a clock signal in synchronization with the output signal of the waveform shaping means.
The digital signal receiving circuit according to 1.