JP3531406B2 - Video signal processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device, and more particularly to a programmable arithmetic circuit (digital signal processor: DSP hereinafter).
It is related to a television receiver using.

[0002]

2. Description of the Related Art In recent years, various developments have been made on signal processing technology by DSP, and one of them is, for example, a television receiver using a DSP described in Japanese Patent Laid-Open No. 56-37272. A configuration example of a television receiver using this DSP is shown in FIG. 7, and this television receiver will be described below.

FIG. 7 is a block diagram showing an outline of a television receiver using a DSP. In FIG. 7, the signal received by the antenna 200 is guided to the tuner 201, where the selected channel is determined, and the intermediate frequency signal derived from the tuner 201 is amplified by the intermediate frequency amplifier 202 and supplied to the detector 203. To be done. Detector 203
The video signal output from is selected by the selection circuit 204 and supplied to the synchronous reproduction deflection control circuit 206 and the analog-digital (A / D) converter 207. Selection circuit 2
04 can also selectively introduce an external video signal from the terminal 205.

The digitized video signal is supplied to the video signal processing device 210. This video signal processing device 2
Reference numeral 10 is composed of a plurality of DSPs. The video signal processed by the video signal processing device 210 is supplied to the digital-analog (D / A) converter 208, converted into an analog signal, and supplied to the color CRT 209. A loader circuit 501 is connected to the video signal processing device 210. The loader circuit 501 transfers the program data from the program memory 211 to the video signal processing device 21.
Used to write 0 to each DSP.

Here, the program data is automatically written according to the system of the input signal, and the system determination is performed by using the system determination circuit 500 for the NTSC system, the PAL system, or the video signal output from the selection circuit 204. SECAM
It is determined which method is used.

The system determination circuit 500 provides the program memory 211 with a bank select signal in which a program corresponding to the system is stored, and also provides a trigger pulse to the loader circuit 501. This allows
The program in the program memory 211 is a plurality of DSs.
Sequentially transferred to P. As a result, the video signal processing device 2
The signal processing mode inside 10 is set.

[0007]

Conventionally, in the case of realizing a television receiver capable of processing a plurality of video signals, a dedicated video signal processing circuit conforming to each system is required, and more functions are required. A large number of circuits are required to realize the above, and there is a cost problem, and a DSP capable of realizing a plurality of video signals with one circuit is required.

However, in the signal processing circuit using the DSP as shown in FIG. 7, a plurality of video signals can be processed and configured by one video processing circuit, but data mistransfer or CPU
There is a problem that a erroneous operation of video signal processing such as a hang-up of the video signal or an erroneous output of an image is caused due to a disturbance of synchronization, and a stable video processing system is required.

[0009]

In order to solve this problem, the present invention provides stable operation even when a program transfer error occurs in the DSP when a plurality of video signals are processed by a single video processing circuit using the DSP. It is configured to output a video signal.

Further, the DSP is adapted to be able to adaptively display the operating state of the system such as a program transfer error on the screen.

This makes it possible for the user to recognize the operating state of the processor, and at the same time, a stable system can be obtained at the time of erroneous program transfer or CPU hang-up.

[0012]

[0013]

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION The video signal processing apparatus of the present invention includes a memory in which a plurality of microprograms defining a plurality of video decoding processing algorithms are stored in advance, and a video signal is supplied to perform video decoding processing according to the microprograms. A programmable arithmetic circuit for performing, a CPU for controlling transfer of a microprogram stored in the memory to the programmable arithmetic circuit, a video data storage means for storing video data, a video signal output and deflection when the CPU hangs up. A video synchronization control circuit for controlling the synchronization signal output, a first selection circuit capable of selecting the output of the programmable arithmetic circuit or the output of the video data storage means by a first control signal of the video synchronization control circuit, and an input A sync playback circuit that performs sync detection and sync playback for video signals, and A deflection synchronization circuit that receives the synchronization signal output of the synchronization reproduction circuit as input and performs synchronization signal processing of the deflection system, a setting synchronization signal generation circuit that generates a preset synchronization signal, an output of the deflection synchronization circuit and the setting A screen display is provided by providing a second selection circuit capable of selecting the output of the synchronization signal generation circuit by the second control signal of the video synchronization control circuit, and replacing the video signal output and the deflection synchronization even when the CPU hangs up. It has the effect that it can be carried out stably.

Further, in the video signal processing device of the present invention, a memory in which a plurality of microprograms defining a plurality of video decoding processing algorithms are stored in advance, and a plurality of microprograms for controlling screen display are stored in advance. No. 2 memory, a third memory in which screen display contents are stored in advance, a programmable arithmetic circuit that is supplied with a video signal and performs a video decoding process according to the microprogram, and a microprogram stored in the memory is the programmable operation. A CPU that controls the transfer to the circuit,
Video data storage means for storing video data, CP
A video display synchronous output control circuit that controls the programmable arithmetic circuit and the deflection synchronous signal output at the time of U hang-up, a synchronous reproduction circuit that performs synchronous detection for the input video signal, and performs synchronous reproduction, and synchronization of the synchronous reproduction circuit. A deflection synchronizing circuit that receives a signal output as input and performs a synchronizing signal processing of a deflection system, a setting synchronizing signal generating circuit that generates a preset synchronizing signal, an output of the deflection synchronizing circuit, and an output of the setting synchronizing signal generating circuit. Is provided with a selection circuit capable of selecting and by the control signal of the video synchronization control circuit, and even when the CPU hangs up, by replacing the video signal output and the deflection synchronization, it is possible to perform stable screen display. I have.

(Embodiment 1) A first embodiment of a video signal processing apparatus according to the present invention will be described below with reference to FIGS.
Will be explained. FIG. 1 is a block diagram showing the configuration of a video signal processing device according to an embodiment of the present invention. FIG. 2 is a flow chart for explaining the operation of the video signal processing device of FIG.

In FIG. 1, 1 is a video signal input terminal, 2
Is an A / D converter for converting a video signal input from the video signal input terminal 1 into a digital signal, 3 is a programmable arithmetic circuit capable of processing the video signal input from the video signal input terminal 1 according to a broadcasting system, Reference numeral 4 is a D / A converter for converting the digital video signal output from the programmable arithmetic circuit 3 into an analog video signal, and 5 and 6 are memories in which a plurality of microprograms defining a plurality of video decoding processing algorithms are stored in advance. And 5 is a read only memory (hereinafter referred to as ROM), 6 is a random access memory (hereinafter referred to as RAM), and 7 is a transfer control of the microprogram stored in the memories 5 and 6 to the programmable arithmetic circuit 3. CPU, 8 is a video data storage means for storing video information data, and 9 is a CPU
A selection circuit that can select an output according to the control signal 7 is a signal transfer bus, and 11 is an output terminal of the selection circuit 9.

The programmable arithmetic circuit 3 has a ROM 5, a RAM 6, and a C via an input / output port (not shown).
They are connected to the PU 7 via the bus 10. The programmable arithmetic circuit 3 is an arithmetic circuit whose processing contents can be changed. The procedure of the arithmetic operation is input from the ROM 5 as a micro program and loaded into the programmable arithmetic circuit 3 according to a load instruction from the CPU 7.

The CPU 7 judges whether the register is erroneously transferred or the data is erroneously recognized by the programmable arithmetic circuit 3, and when the data is erroneously transferred, it outputs a control signal to the selection circuit 9. This control signal controls the output of the signal output from the video data storage means 8 so that erroneous video data is not output.

The operation of the video signal processing circuit of FIG. 1 configured as above will be described with reference to FIG.

When the power is turned on, the video signal input from the video signal input terminal 1 is not processed while the program is transferred from the ROM 5 to the programmable arithmetic circuit 3. Therefore, the CPU 7 sends the selection signal "1" to the selection circuit 9. Output. (Step 1) In response to this selection signal, the selection circuit 9 outputs the signal output from the output terminal 11 to the video data storage means 8.
To be the video data from.

Next, the video signal input to the video signal input terminal 1 is input to the programmable arithmetic circuit 3 via the A / D converter 2. The CPU 7 determines the system of the video signal input to the programmable arithmetic circuit 3, and issues a command to the ROM 5 to output a program corresponding to the video signal from the ROM 5 to the programmable arithmetic circuit 3 (step
p2).

The output signal from the ROM 5 is sent via the bus 10 to the programmable arithmetic circuit 3, the RAM 6 and the CPU.
It is input to each of 7. The CPU 7 compares the input signal from the ROM 5 with the data (register) loaded in the programmable arithmetic circuit 3 (step 3). If the compared results match, it is determined that the program has been normally transmitted from the ROM 5 to the programmable arithmetic circuit 3, and a selection signal having a selection value "0" is sent to the selection circuit 9 (step 4). The signal output from the programmable arithmetic circuit 3 and converted into an analog signal by the D / A converter 4 is switched to be output from the output terminal 11.

On the other hand, as a result of comparison, if the data loaded into the programmable arithmetic circuit 3 and the signal sent to the CPU 7 do not match, it is judged that a program transfer has failed,
An instruction is given again to transfer the ROM information to the programmable arithmetic circuit 3. The CPU controls to compare the register values until they match.

The CPU 7 performs register comparison once in n times (setting cycle n: integer) even after the coincidence and the selected value becomes "0", and immediately makes a change if a transfer error occurs. Instead of applying a hysteresis, it has hysteresis, and it is determined whether or not it is a temporary transfer error, and then whether or not the data in the ROM 5 is retransferred.

As described above, in the video signal processing device of the present invention, when the program data is transferred to the programmable arithmetic circuit, if the register erroneous transfer of the CPU 7 or the data erroneous recognition of the programmable arithmetic circuit 3 occurs, the video data storage means. By outputting the image recorded in 8 instead, the control is performed so that the disturbed image signal is not output accidentally, and a stable output operation is realized.

(Second Embodiment) Next, a second embodiment of the video signal processing apparatus of the present invention will be described with reference to FIGS. 3 and 4. The same components as those of the first embodiment described with reference to FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

FIG. 3 is a block diagram showing a configuration example of the video signal processing device of the present invention, and FIG. 4 is a diagram showing a display portion state of an image display device having the video signal processing device.

In FIG. 3, reference numeral 21 is a display means for displaying externally so that the user can recognize when data is erroneously transferred to the programmable arithmetic circuit 3 by the control signal of the video display output control circuit, and 22 is Display means 2
1 output terminal.

The operation of the video signal processing circuit configured as described above will be described below with reference to FIG.

As described in the first embodiment, the CPU 7 judges the register erroneous transfer of the CPU 7 and the data erroneous recognition of the programmable arithmetic circuit 3, and when the data is erroneously transferred, the selection value "1" is set in the selection circuit 9. The control signal (first control signal) is output to the selection circuit 9. This control signal is output controlled so as to output the video from the video data storage means 8 so as not to output erroneous video data. Also,
At the same time, another control signal (second control signal) is output to the display means 21. The display means 21 is controlled by the second control signal, and displays the contents so that the user can recognize when the register erroneous transfer occurs. The display means 21 may be a display of the display portion of the image display device, an LED, or the like.

Here, an example of the display is shown using FIG.
explain. In FIG. 4, a screen display example (see FIG.
(A)) and an LED display example (FIG. 4 (b)) on the right part. The screen display is an on-screen display (hereinafter referred to as OSD) display, and displays "data is being transferred" on a part of the screen or sends a still image so that the user can recognize it. During this period, the CPU 7 performs RO to reload the program of the part that was erroneously transferred.
M5 and programmable arithmetic circuit 3 are controlled. Further, regarding the LED display, it is possible to use a method of discriminating on the basis of the type of color, and the user can recognize the transfer information according to the color.

As described above, according to the present invention, by sending the information for writing the status of the program transfer on or near the screen, the viewer can be informed of the status and the anxiety of breakdown or the like will not be given and the user can feel at ease. To realize a video signal processing device capable of providing a display device that can be viewed.

(Third Embodiment) Next, a third embodiment of the video signal processing apparatus of the present invention will be described with reference to FIG. The same components as those of the first and second embodiments described above are designated by the same reference numerals, and the description thereof will be omitted.

FIG. 5 is a block diagram showing an embodiment of the video signal processing device. In FIG. 5, 31 is a CPU
7. A video synchronization control circuit for controlling video signal output control and deflection synchronization when the hang-up of 7, a synchronous reproduction circuit 32 for synchronous detection / reproduction with respect to an input video signal, 33 a deflection output from the synchronous reproduction circuit 32. A deflection synchronization circuit that receives a synchronization signal and forms a deflection loop, 34 is a set synchronization signal generation circuit that generates a preset synchronization signal, and 35 is a deflection synchronization circuit 33 that is controlled by the second control signal of the video synchronization control circuit 31. Second output circuit that can select the output of the output signal of the setting synchronizing signal generating circuit 34 or the output signal of the setting synchronizing signal generating circuit 34. Reference numerals 36 and 37 denote amplitude amplifying circuits for amplifying the amplitudes of the video signal and the deflection synchronizing signal.
Is a display capable of displaying a signal subjected to video signal processing.

The operation of the video signal processing circuit configured as described above will be described below with reference to FIG.

The video synchronization control circuit 31 constantly monitors whether or not the CPU 7 is hung up, and controls the first selection circuit 9 and newly selects the deflection synchronization circuit 33 as described in the first embodiment. The second selection circuit 35 is controlled. When the CPU 7 hangs up, the video synchronization control circuit 31 transfers the video data storage means 8 to the first selection circuit 9.
The selection value “1” (first control signal) is output so as to select the video data output from the second selection circuit 3
A second control signal for selecting the deflection synchronization signal output from the setting synchronization signal generation circuit 34 is output to the signal line 5.

As a result, even when the CPU 7 hangs up and system control becomes impossible, the output video signal is displayed on the display 38 which is the image display means by the video output from the video data storage means 8. As the deflection synchronizing signal, the preset synchronizing signal output from the setting synchronizing signal generating circuit 34 is output to the display 38, so that the screen is prevented from being disturbed and a stable screen display can be performed.

The video signal processing device according to the above-described embodiment can provide a stable image to the viewer even when the CPU is hung up and the system control is disabled.

(Fourth Embodiment) Next, a fourth embodiment of the video signal processing apparatus of the present invention will be described with reference to FIG. The same components as those of the first, second, and third embodiments described above are designated by the same reference numerals, and the description thereof will be omitted.

FIG. 6 is a block diagram showing an embodiment of the video signal processing device. In FIG. 6, 51 is a second memory (hereinafter referred to as a second ROM) in which a plurality of microprograms for controlling screen display are stored in advance, and 52 is a third memory (in which the screen display content is stored in advance). Hereinafter, a third ROM), 53 is a video display synchronization control circuit for controlling the video signal output and the deflection synchronization signal output when the CPU 7 hangs up.

The operation of the video signal processing device configured as described above will be described with reference to FIG.

In the video display synchronization control circuit 53, the first control signal is sent to the programmable arithmetic circuit 3 as the first control signal,
The second control signal is sent to the selection circuit 35. In the programmable arithmetic circuit 3, the first from the video display synchronization control circuit 53
When the CPU 7 is hung up by the control signal of, the microprogram recorded in the second ROM 51 is downloaded, and the screen display stored in the third ROM 52 expressing that the CPU 7 is hung up is displayed. The content is decoded and displayed on the display 28. In addition, the selection circuit 35 is generated by the second control signal.
Then, the synchronizing signal preset in the setting synchronizing signal generating circuit 34 is selected.

In the present embodiment, the second ROM 51,
The third ROM 52 is connected to the video display synchronization control circuit 5 respectively.
3, the configuration is shown in which the programmable arithmetic circuit 3 is connected, but like the first ROM 5, it is connected to the bus 10 and outputs programs and data to the programmable arithmetic circuit 3 through the bus 10. Good.

As described above, even if the CPU 7 hangs up and system control becomes impossible, the output video signal and the deflection synchronization signal are stabilized to prevent the screen from being disturbed, and stable screen display can be performed.

[0046]

[0047]

[0048]

As described above, according to the present invention , even when the CPU hangs up, it is possible to perform stable screen display by replacing the video signal output and the deflection synchronization.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a video signal processing device according to a first embodiment of the present invention.

FIG. 2 is an algorithm flowchart of the operation of the video signal processing device.

FIG. 3 is a circuit block diagram of a video signal processing device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing an example of a second embodiment of the present invention.

FIG. 5 is a circuit block diagram of a video signal processing device according to a third embodiment of the present invention.

FIG. 6 is a circuit block diagram of a video signal processing device according to a fourth embodiment of the present invention.

FIG. 7 is a circuit block diagram of a conventional video signal processing device.

[Explanation of symbols]

1 Video signal input terminal 2,207 A / D converter 3 programmable arithmetic circuit 4,208 D / A converter 5, 51, 52 Memory (ROM) 6 memory (RAM) 7 CPU 8 Video data storage means 9 means of selection 10 signal bus 11 Video signal output terminal 21 display means 22 Display means output terminal 31 Video synchronization control circuit 32 Synchronous playback circuit 33 Deflection synchronization circuit 34 Setting synchronization signal generator 35 Second selection circuit 36, 37 amplifier 38 display 53 Video display synchronization control circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-241584 (JP, A) JP-A-5-91434 (JP, A) JP-A-5-83651 (JP, A) JP-A-6- 113217 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 5/46

Claims (2)

(57) [Claims] 1. A memory in which a plurality of microprograms defining a plurality of video decoding algorithms are stored in advance, a programmable arithmetic circuit to which a video signal is supplied and which performs a video decoding process according to the microprograms, and a memory which is stored in the memory. CP for controlling transfer of a microprogram to the programmable arithmetic circuit
U, video data storage means for storing video data, a video synchronization control circuit for controlling the output of the video signal or the output of the deflection synchronization signal when the CPU hangs up, the output of the programmable arithmetic circuit or the A first selection circuit for selecting whether to output from the video data storage means by a first control signal of the video synchronization control circuit; a synchronous reproduction circuit for performing synchronous detection for an input video signal and performing synchronous reproduction; A deflection synchronization circuit that receives the synchronization signal output of the synchronization reproduction circuit as input and performs a synchronization signal processing of the deflection system, a setting synchronization signal generation circuit that generates a preset synchronization signal, an output of the deflection synchronization circuit and the setting synchronization. A video signal processing device comprising: a second selection circuit for selecting the output of the signal generation circuit and a second control signal of the video synchronization control circuit. 2. A memory in which a plurality of microprograms defining a plurality of video decoding algorithms are stored in advance, and a second memory in which a microprogram that controls screen display when the CPU hangs is stored in advance. A third memory in which screen display contents are stored in advance, a programmable arithmetic circuit which is supplied with a video signal and performs a video decoding process according to the microprogram, and a control for transferring the microprogram stored in the memory to the programmable arithmetic circuit A video data storage means for storing video data, a video display synchronization output control circuit for controlling the programmable arithmetic circuit and deflection synchronization signal output when the CPU hangs up, and an input video signal. Synchronous reproduction circuit that performs synchronous detection by performing synchronous detection A deflection synchronization circuit that receives the synchronization signal output of the synchronization reproduction circuit as input and performs synchronization signal processing of a deflection system; a set synchronization signal generation circuit that generates a preset synchronization signal; and an output of the deflection synchronization circuit. A video signal processing device, comprising: a selection circuit that selects the output of the setting synchronization signal generation circuit and a control signal of the video synchronization control circuit.