JP3526541B2 - Semiconductor integrated circuit device and data input / output unit thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its data input / output unit, and more particularly to a semiconductor integrated circuit device having a level shift circuit.

[0002]

2. Description of the Related Art In recent years, with the digitization of video information equipment, digital transmission is being used for data transmission and reception between equipment. Even at home, DVC (Digital
l Video Camera and PC (Person)
al Computer) connection, etc. IEEE1394
Standards have been adopted and standardized as standards for home networks. IEEE139 of 200Mbps transmission
4.1995 has already been standardized, and also 400 Mbp
s IEEE 1394. a will be standardized in the near future. The standard is IEEE P1394.1995 D.
raft 8.4 and IEEE P1394a D
Each of them is described in "raft 3.1", and each company develops an LSI that complies with this standard. At present, IEEE 1394 is a standard for realizing extremely high-speed data transmission of 400 Mbps in MAX. However, due to this high-speed data transmission, jitter is required.
The restrictions on r) and skew are very strict. In order to satisfy this limitation, measures have been taken to reduce jitter and skew individually for each circuit.

[0003]

[Problems to be Solved by the Invention] L of the 0.25 μm generation
In SI, the voltage level of the signal input / output from the data input / output circuit to the outside of the LSI is different from the voltage level of the signal in the logic section inside the LSI. Therefore, it is necessary to provide a level shift circuit. However,
As shown in FIGS. 14 and 15, the level shift circuit has a very large jitter component due to the circuit configuration. That is, two voltage levels (VDDH, VD
Since (DL) changes without any correlation, the rising edge and the falling edge of the input signal are largely deviated when the voltage is converted. For example, with respect to the TYP condition, a phenomenon occurs in which the rising edge is greatly delayed and the falling edge is forward. At this time, in the case of a transmission method in which a rising portion and a falling portion of a signal are used as data, such as IEEE 1394, there arises a problem that the data width is reduced to a width that cannot withstand data transmission. To do.

The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor integrated circuit device capable of reducing a jitter component.

[0005]

According to one aspect of the present invention, a semiconductor integrated circuit device includes a logic circuit portion, a first level shift circuit, and a flip-flop circuit.

The logic circuit portion receives a first power supply voltage of a first voltage level and a first ground voltage and generates an output signal having an amplitude of the first voltage level. The first level shift circuit controls the amplitude of the output signal from the logic circuit section to the second level.
Convert to the amplitude of the voltage level of. The flip-flop circuit receives the second power supply voltage of the second voltage level and the second ground voltage, latches the output signal from the level shift circuit in response to a predetermined clock signal, and outputs the latched output. The signal is output in response to a predetermined clock signal.

If the flip-flop circuit is not provided, the output signal including the jitter generated up to the first level shift circuit is output as it is to the outside. However, in the semiconductor integrated circuit device described above, the jitter component included in the output from the first level shift circuit is reduced by the flip-flop circuit. As a result, a large data window can be secured and high speed operation can be realized.

Preferably, the semiconductor integrated circuit device further includes a clock signal generation circuit and a second level shift circuit. The clock signal generation circuit receives a first power supply voltage and a first ground voltage and generates a first clock signal having an amplitude of a first voltage level. The second level shift circuit converts the amplitude of the first clock signal from the clock signal generation circuit into the amplitude of the second voltage level and supplies it to the flip-flop circuit. The flip-flop circuit responds to either the rising or falling edge of the clock signal from the second level shift circuit.

Preferably, the logic circuit section operates in response to the first clock signal from the clock signal generating circuit. The first signal from the clock signal generating circuit
The clock signal has a frequency twice as high as the frequency of the output signal from the logic circuit section.

The increase amount of the jitter component by the second level shift circuit is different between the rising portion and the falling portion of the clock signal from the second level shift circuit. But,
In the semiconductor integrated circuit device, the flip-flop circuit responds to either the rising or falling edge of the clock signal from the second level shift circuit. Therefore, looking at only the responding edge, all the edges are displaced in the same direction due to the influence of the fluctuation of the power supply voltage in the second level shift circuit. As a result, the jitter component due to the second level shift circuit can be removed.

Preferably, the flip-flop circuit is configured such that the first flip-flop circuit is in the first mode in the test mode in which the clock signal is stopped.
The output signal from the level shift circuit of is output to the outside.

In the above semiconductor integrated circuit device, it is not necessary to supply the clock signal to the flip-flop circuit again in the test mode.

Preferably, the flip-flop circuit includes a first latch circuit, a timing adjusting circuit, and a second latch circuit.
Latch circuit and a third latch circuit.

The first latch circuit latches the output signal from the first level shift circuit in response to the clock signal from the second level shift circuit. The timing adjustment circuit receives the output signal from the first latch circuit and the inverted signal of the output signal from the first latch circuit, and responds to the clock signal from the second level shift circuit with the output signal and the inverted signal. Output. The second latch circuit latches the output signal from the timing adjustment circuit in response to the inverted signal of the clock signal from the second level shift circuit. The third latch circuit latches the inverted signal from the timing adjustment circuit in response to the inverted signal of the clock signal from the second level shift circuit.

In the above semiconductor integrated circuit device, the first
The output signal from the latch circuit and the inverted signal of the output signal from the first latch circuit are respectively supplied to the second latch circuit and the third latch circuit at the same timing.

Preferably, the flip-flop circuit further includes an inverter, a delay compensation circuit, and an output switching circuit.

The inverter inverts the output signal from the first level shift circuit. The delay compensation circuit delays the output signal from the first level shift circuit by a predetermined time. The output switching circuit outputs the output signal from the second latch circuit and the output signal from the third latch circuit to the outside in the normal mode, while the delay compensation circuit in the test mode in which the first clock signal is stopped. The output signal from the inverter and the output signal from the inverter are output to the outside.

In the semiconductor integrated circuit device, it is not necessary to supply the clock signal to the first to third latch circuits again in the test mode. Since the delay compensation circuit is provided, the output switching circuit outputs the output signal from the delay compensation circuit and the output signal from the inverter at the same timing in the test mode.

Preferably, both the second latch circuit and the third latch circuit include an inverter and a clocked inverter.

The inverter inverts the signal from the timing adjustment circuit. The clocked inverter responds to the inverted signal of the clock signal from the second level shift circuit and inverts the output from the inverter and supplies the inverted output to the input of the inverter.

In the above semiconductor integrated circuit device, the second
The latch circuit and the third latch circuit output the output signal and the inverted signal from the timing adjustment circuit at the same timing. As a result, it is possible to suppress the occurrence of jitter in the flip-flop circuit. As a result, even if a flip-flop circuit is provided in the data input / output path, the jitter hardly increases.

Further, when there is a timing shift between the complementary signals by the output signals from the second latch circuit and the third latch circuit, when the driver circuit for receiving this complementary signal is provided, Jitter (data indefinite period) occurs in the output. In the semiconductor integrated circuit device, signals are output from the second latch circuit and the third latch circuit at the same timing. Therefore, it is possible to prevent the occurrence of jitter as described above.

Preferably, the flip-flop circuit further includes a reset circuit. The reset circuit receives the active reset signal, activates the clock signal from the second level shift circuit, and deactivates the inverted signal of the clock signal from the second level shift circuit. The first latch circuit receives the active reset signal and outputs a signal of the first logic level.

Normally, when resetting the flip-flop circuit, an active reset signal is supplied to both the first-stage latch circuit and the second-stage latch circuit. If, in the flip-flop circuit, an active reset signal is supplied to all of the first to third latch circuits, the circuit configuration from the input to the output of the second latch circuit and the third latch circuit. Must be different from the circuit configuration from input to output. This causes a timing shift between the complementary signals of the output signal from the second latch circuit and the output signal from the third latch circuit. Therefore, in the semiconductor integrated circuit device,
The reset of the flip-flop circuit is realized by inactivating the inverted signal supplied to the clocked inverter without supplying the active reset signal to the second and third latch circuits. As a result, the circuit configuration from the input to the output of the second latch circuit and the circuit configuration from the input to the output of the third latch circuit can be made the same. As a result, the output signal from the second latch circuit and the third signal
It is possible to prevent a timing shift from occurring between the complementary signal to the output signal from the latch circuit of the above.

Preferably, the first level shift circuit includes a first inverter, a first P-channel MOS transistor, a first N-channel MOS transistor,
It includes a second P-channel MOS transistor and a second N-channel MOS transistor.

The first inverter is connected between a first power supply node receiving the first power supply voltage and a first ground node receiving the first ground voltage. First P channel MO
The S transistor is connected between a second power supply node receiving the second power supply voltage and the first ground node. The first N-channel MOS transistor is the first P-channel M
It is connected between the drain of the OS transistor and the first ground node, and receives the output of the first inverter at its gate. The second P-channel MOS transistor has a source connected to the second power supply node, a drain connected to the gate of the first P-channel MOS transistor, and a first P-channel MOS transistor.
Channel MOS transistor and first N-channel MOS
The gate receives the voltage of the interconnection node with the transistor. The second N-channel MOS transistor has a second P
It is connected between the drain of the channel MOS transistor and the first ground node, and receives the input of the first inverter at its gate.

Normally, when there are two power supply voltages in the semiconductor integrated circuit device, two ground voltages are also provided separately. The circuit receiving the first power supply voltage is supplied with the first ground voltage, and the circuit receiving the second power supply voltage is supplied with the second ground voltage. If the first and second N-channel MOS transistors are connected to the second ground node in the first level shift circuit, the state becomes very unstable, and malfunctions and increase in jitter during level conversion occur. Will cause. This is because even if the first ground voltage and the second ground voltage have the same level when viewed in terms of direct current, they will have completely different levels when viewed in terms of alternating current, depending on the connected circuit blocks. . For example, the circuit block connected to the first ground node is a digital circuit block, and the circuit block connected to the second ground node is an analog circuit or an input / output circuit.

However, in the above semiconductor integrated circuit device, the first inverter and the first and second N-channel MOS transistors are commonly connected to the first ground node. Thereby, the amount of jitter generated in the first level shift circuit can be reduced. In addition, it is possible to suppress malfunctions during level conversion.

According to another aspect of the present invention, the data input / output unit of the semiconductor integrated circuit device includes a first amplifier circuit, a second amplifier circuit, and a clamp circuit.

The first amplifier circuit amplifies the amplitude of an input signal from the outside. The second amplifier circuit amplifies the amplitude of the output signal from the first amplifier circuit. The clamp circuit is the first
Is provided between the first amplification circuit and the second amplification circuit and clamps the amplitude level of the output signal from the first amplification circuit to a predetermined level. The input signal has an amplitude of 300 mV
The central potential is the potential between the power supply voltage level and the ground voltage level, and the level changes in time series.

Since the data input / output unit of the semiconductor integrated circuit has a multi-stage configuration of the first and second amplifiers, even if the input signal from the outside is a signal having a very small amplitude level (300 mV or less). It can be amplified at high speed.

Further, if the clamp circuit is not provided, the amplitude of the output signal of the first amplifier circuit largely fluctuates when the same data is continuously input from the outside. Therefore, when the inverted data of the data is subsequently input, the speed at which the first amplifier circuit amplifies the inverted data becomes slow, and the data width of the inverted data becomes narrow. A jitter component is generated due to the difference in the data width. However, since the data input / output unit of the semiconductor integrated circuit is provided with the clamp circuit, the amplitude level of the signal from the first amplifier circuit is clamped to a predetermined level.
As a result, it is possible to suppress the generation of the jitter component due to the difference in the data width. As a result, high-speed amplification operation can be realized.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated.

FIG. 1 is a block diagram showing the overall structure of a semiconductor integrated circuit device (IEEE 1394 physical layer) according to an embodiment of the present invention.

The semiconductor integrated circuit device shown in FIG. 1 has two power supply voltages VDDL and VDDH. The power supply voltage VDDL is 2.5 V, and the power supply voltage VDDH is 3.3
V. The semiconductor integrated circuit device also includes a logic circuit section 10, a data output section 20, and a data input section 30.
And differential signal lines 41 and 42. The logic circuit unit 10, the data output unit 20, the data input unit 30, and the differential signal lines 41 and 42 are arranged on the same chip 1.

The logic circuit section 10 has a power supply voltage VDDL.
And the ground voltage VSSL, the circuit operates in response to the clock signal CLK1 from the PLL circuit 21, outputs the output signal d1 to the data output unit 20, and receives the input signal d2 from the data input unit 30. Output signal d1 and input signal d2
Has an amplitude level of 2.5V.

The data output section 20 includes a PLL circuit 21 and
The DS encoder 22 and the level shift circuit 23-25
, The flip-flops 26 and 27, and the driver circuit 2
8 and 29 are included.

PLL circuit 21 receives power supply voltage VDDL and ground voltage VSSL to generate clock signal CLK1. The clock signal CLK1 is 2.5V (VDDL)
Has an amplitude level of and a frequency of 400 MHz.

The DS encoder 22 has a power supply voltage VDDL.
And the ground voltage VSSL, the output signal d1 from the logic circuit unit 10 is encoded into a data signal Data1 and a strobe signal Stb1. The DS encoder 22 is
D standardized in the physical layer of IEEE 1394
It is a circuit that realizes data transmission by the S method (encoding method). Data signal Data1 and strobe signal S
tb1 has an amplitude level of 2.5V (VDDL).

The level shift circuit 23 sets the amplitude level of the data signal Data1 from the DS encoder 22 to 3.
Convert to an amplitude level of 3V (VDDH). The level shift circuit 24 converts the amplitude level of the strobe signal Stb1 from the DS encoder 22 into an amplitude level of 3.3V (VDDH). The level shift circuit 25 is a PLL
The amplitude level of the clock signal CLK1 from the circuit 21 is
Convert to an amplitude level of 3.3V (VDDH).

The flip-flop 26 has a power supply voltage VDD.
Receiving H and the ground voltage VSSH, the level shift circuit 2
Data signal Dat from the level shift circuit 23 in response to the rising edge of the clock signal CLK1a
It latches a1a and outputs it as a complementary signal. The flip-flop 27 has a power supply voltage VDDH and a ground voltage VS.
Upon receiving SH, the strobe signal Stb1a from the level shift circuit 24 is latched in response to the rising edge of the clock signal CLK1a from the level shift circuit 25,
Output as a complementary signal.

Driver circuit 28 receives power supply voltage VDDH and ground voltage VSSH and outputs a complementary output data signal from flip-flop 26 to differential signal line 42. Driver circuit 29 receives power supply voltage VDDH and ground voltage VSSH and outputs a complementary output strobe signal from flip-flop 27 to differential signal line 41.

The data input section 30 includes a receiver circuit 31,
32, level shift circuits 33 and 34, a DS decoder 35, and a flip-flop 36.

The receiver circuit 31 receives the power supply voltage VDDH and the ground voltage VSSH, amplifies the complementary input data signals from the terminals TPA and NTPA, and outputs the data signal Da.
Output as ta2. The receiver circuit 32 receives the power supply voltage VDDH and the ground voltage VSSH, and receives the terminals TPB,
Amplify the complementary input strobe signal from NTPB,
The strobe signal Stb2 is output.

The level shift circuit 33 includes the receiver circuit 3
The amplitude level of the data signal Data2 from 1 is 2.5
The amplitude level is converted to V (VDDL). The level shift circuit 34 receives the strobe signal S from the receiver circuit 32.
The amplitude level of tb2 is converted into the amplitude level of 2.5V (VDDL).

The DS decoder 35 receives the power supply voltage VDDL and the ground voltage VSSL, and receives the level shift circuit 33,
The data signal Data2a and the strobe signal Stb2a from 34 are combined into the input signal d2a. Also,
The DS decoder 35 generates the clock signal CLK2 by taking the exclusive OR of the data signal Data2a and the strobe signal Stb2a. Clock signal CL
K2 has a frequency of 200 MHz. This frequency corresponds to the data signal Data2a and the strobe signal St.
It is equal to the frequency of b2a. The DS decoder 35 is IEEE
It is a circuit that realizes data transmission by the DS system (encoding system) standardized in the physical layer of E1394.

The flip-flop 36 has a power supply voltage VDD.
In response to the clock signal CLK2 from the DS decoder 35, the DS decoder 3 receives the L signal and the ground voltage VSSL.
The input signal d2a from 5 is latched and output as the input signal d2.

The differential signal line 41 transmits the complementary output strobe signals from the driver circuit 29 to the terminals TPA and NTPA, and the complementary input data signals from the terminals TPA and NTPA to the receiver circuit 31. Differential signal line 42
Transmits complementary output data signals from the driver circuit 28 to the terminals TPB and NTPB, and transmits input strobe signals from the terminals TPB and NTPB to the receiver circuit 32.

The terminals TPA and NTPA are connected to the first twisted pair signal line (not shown). Terminal TPB, N
TPB is connected to a second twisted pair signal line (not shown). The first twisted pair signal line and the second twisted pair signal line form one cable Cable.

Next, the operation of the semiconductor integrated circuit device configured as described above will be divided into (1) a case where a data signal is output to the outside and (2) a case where a data signal is input from the outside. explain.

(1) When outputting a data signal to the outside The output signal d1 from the logic circuit 10 is encoded by the DS encoder 22 into a data signal Data1 and a strobe signal Stb1. The amplitude levels of the data signal Data1 and the strobe signal Stb1 are converted by the level shift circuits 23 and 24, respectively, and are supplied to the flip-flops 26 and 27 as the data signal Data1a and the strobe signal Stb1a, respectively.

The data signal Data1 and the strobe signal Stb1 are latched by the flip-flops 26 and 27, respectively, in response to the rising edge of the clock signal CLK1a, and the jitter components generated up to the level shift circuits 23 and 24 are removed. Circuit 28,
29 is output. Then, the driver circuits 28 and 29
Output to the differential signal lines 42, 41 from the terminal T
It is output from the PB, NTPB, TPA, and NTPA to the outside.

Here, the level shift circuit 25 has the same circuit configuration as the level shift circuits 23 and 24. But,
Even through the level shift circuit 25, the clock signal CLK
There is no increase in the jitter component for the period of 1a. The reason for this will be described below with reference to FIG. Data signal Data
1a and strobe signal Stb1a are effective at both the rising edge and the falling edge. Therefore, the increase in the jitter received from the level shift circuits 23 and 24 is different between the rising direction and the falling direction. On the other hand, the flip-flops 26 and 27 are
Only the rising edge of the clock signal CLK1a is valid and the data signal Data1a and the strobe signal Stb are valid.
Latch 1a. Therefore, the clock signal CLK1a
The edge shifts that are regarded as valid are always in the same direction. Therefore, in the clock signal CLK1a, there is no increase in the jitter component due to the level shift circuit 25, and the PLL circuit 2
Only the jitter component at 1 remains.

The data signals D from the level shift circuits 23 and 24 are provided without providing the flip-flops 26 and 27.
When ata1 and strobe signal Stb1 are directly output to the outside, the jitter components generated up to level shift circuits 23 and 24 cannot be removed. The maximum jitter component generated by the level shift circuits 23 and 24 is 500 ps or more. In this case, it is not possible to meet the IEEE 1394 transmission side standard of 400 ps.

Further, here, the flip-flops 26,
27 validates only the rising edge of the clock signal CLK1a and latches the data signal Data1a and the strobe signal Stb1a, but the clock signal CLK1a
Data signal Dat with only the falling edge of
The a1a and strobe signal Stb1a may be latched.

(2) In the case of inputting a data signal from the outside The data signal input to the terminals TPA and NTPA from the outside is supplied to the receiver circuit 31. External terminal TP
The strobe signal input to B and NTPB is supplied to the receiver circuit 32. Data signal Data2 and strobe signal Stb2 from receiver circuits 31 and 32
Has an amplitude level of 3.3 V (VDDH) to 2.5 V (VDD) by the level shift circuits 33 and 34, respectively.
L) and is supplied to the DS decoder 35 as the data signal Data2a and the strobe signal Stb2a. Data signal Data2a and strobe signal S
The tb2a is combined with the input signal d2a by the DS decoder 35 and supplied to the flip-flop 36. The output from the flip-flop 36 is input to the logic circuit unit 10 as the input signal d2.

In the data input section 30, the receiver circuit 3
At 1 and 32, the jitter component is reduced.

FIG. 3 shows the receiver circuits 31, 3 shown in FIG.
It is a block diagram which shows the schematic structure of 2. Receiver circuit 3
Reference numerals 1 and 32 include amplifier circuits 301, 303 and 304, and a clamp circuit 302.

The amplifier circuit 301 amplifies the input signal IN. The clamp circuit 302 clamps the amplitude of the output signal from the amplifier circuit 301 to a predetermined level. Amplifier circuit 3
03 amplifies the output signal of the amplifier circuit 301. The amplifier circuit 304 amplifies the output signal of the amplifier circuit 303.

Since the receiver circuits 31 and 32 employ the multi-stage configuration (301, 303, 304), the signal IN having a very small amplitude level (300 mV or less) can be amplified at high speed. In addition, the first stage amplifier circuit 30
Since 1 amplifies a signal IN having a slight input level, a clamp circuit 22 is provided to prevent the output amplitude from unnecessarily widening. If the clamp circuit 302 is not provided, as shown in FIG. 4, when the same data is continuously input (a), the amplitude of the output of the first-stage amplifier circuit 301 largely fluctuates. For this reason, the speed of amplifying the inverted data input thereafter becomes slower, and the data width L3 becomes much narrower than the normal data width L1. Then, due to the jitter component due to the difference in the input data, the receiver circuit cannot input 400 MHz data at all. When the clamp circuit 302 is provided, the jitter is 300 ps at the maximum, and it is possible to satisfy the specifications for data input even in total.

Next, the flip-flop 2 shown in FIG.
6, 27 and the level shift circuits 23-25, 33, 34 will be described in more detail.

FIG. 5 is a circuit diagram of the flip-flop 2 shown in FIG.
It is a block diagram which shows the structure of 6,27. The flip-flops 26 and 27 include the latch circuits LC1 to LC3, the reset circuit 50, the timing adjustment circuit 60, the delay compensation circuit 70, the output switching circuit 80, and the inverters 91 and 9.
3-95 and a clocked inverter 92. All receive power supply voltage VDDH and ground voltage VSSH.

The reset circuit 50 includes inverters 51 and 5
3 and a NAND circuit 52. The inverter 51 is
The clock signal C from the level shift circuit 25 shown in FIG.
Invert LK1a. The NAND circuit 52 outputs the NAND of the output of the inverter 51 and the reset signal / RSET. The output of the NAND circuit 52 is the clock signal CLK.
Becomes The inverter 53 inverts the output from the NAND circuit 52. The output from the inverter 53 becomes the clock signal CLKB. The clock signal CLKB is an inverted signal of the clock signal CLK.

The inverter 91 inverts the input signal D. The input signal D is the data signal Data1a in the flip-flop 26 and the strobe signal Stb1a in the flip-flop 27. Clocked inverter 9
2 is an inverter 9 in response to the clock signal CLKB.
Invert the output of 1.

The latch circuit LC1 is the NAND circuit 111.
And a clocked NAND circuit 112. NAND
The circuit 111 outputs the NAND of the output of the clocked inverter 92 and the reset signal / RSET. One input of the clocked NAND circuit 112 has a power supply voltage VDDH
And the other input receives the output of the NAND circuit 111. The output of the clocked NAND circuit 112 is NAND
It is connected to one of the two inputs of the circuit 111, which receives the output of the clocked inverter 92. Therefore, the clocked NAND circuit 112 receives the clock signal C
The output of the NAND circuit 111 is inverted in response to LK.

The inverter 93 inverts the output of the NAND circuit 111.

The timing adjusting circuit 60 includes clocked inverters 61 and 62. Clocked inverter 61
In response to the clock signal CLK, the NAND circuit 11
Invert the output from 1. Clocked inverter 62
Inverts the output of the inverter 93 in response to the clock signal CLK.

The latch circuit LC2 includes an inverter 121.
And a clocked NAND circuit 122. The inverter 121 inverts the output of the clocked inverter 61. One input of the clocked NAND circuit 122 receives the power supply voltage VDDH and the other input receives the output of the inverter 121. The output of the clocked NAND circuit 122 is connected to the input of the inverter 121. Therefore, the clocked NAND circuit 122 receives the clock signal C.
The output of the inverter 121 is inverted in response to LKB.

The latch circuit LC3 includes an inverter 131.
And a clocked NAND circuit 132. The inverter 131 inverts the output of the clocked inverter 62. One input of the clocked NAND circuit 132 receives the power supply voltage VDDH, and the other input receives the output of the inverter 131. The output of the clocked NAND circuit 132 is connected to the input of the inverter 131. Therefore, the clocked NAND circuit 132 outputs the clock signal C
The output of the inverter 131 is inverted in response to LKB.

Inverter 94 inverts the output of inverter 121. The inverter 95 inverts the output of the inverter 131.

Delay compensation circuit 70 includes P channel MOS transistor 71 and N channel MOS transistor 72.
Including and P-channel MOS transistor 71 and N
Channel MOS transistor 72 is connected in parallel between nodes N1 and N2. The ground voltage VSSH is supplied to the gate of the P-channel MOS transistor 71. The power supply voltage VDDH is supplied to the gate of the N-channel MOS transistor 72. At node N1,
The input signal D is supplied.

The output switching circuit 80 includes a NAND circuit 81-
Includes 86 and an inverter 87. NAND circuit 81
Is the NA of the voltage of the node N2 and the test signal DTEST.
Output ND. The inverter 87 outputs the test signal DTE
Invert ST. The NAND circuit 82 has an inverter 87.
And the output of the inverter 94 are output as a NAND. The NAND circuit 83 outputs the output of the NAND circuit 81 and N
The NAND with the output of the AND circuit 82 is output. NAN
The output of the D circuit 83 becomes the output Q of the flip-flops 26 and 27. The NAND circuit 84 outputs a NAND of the inverted signal / D of the input signal D and the test signal DTEST.
The NAND circuit 85 outputs a NAND of the output of the inverter 87 and the output of the inverter 95. NAND circuit 8
6 outputs a NAND of the output of the NAND circuit 84 and the output of the NAND circuit 85. The output of the NAND circuit 86 becomes the output / Q of the flip-flops 26 and 27.

Characteristic points of the flip-flops 26 and 27 configured as described above will be described below.

(A) The number of stages of the circuit from the output of the clocked inverter 61 to the output Q of the flip-flop in the timing adjustment circuit 60, and from the output of the clocked inverter 62 to the output / Q of the flip-flop in the timing adjustment circuit 60. Aligned with the number of circuit stages.

As a result, the flip-flops 26, 27
The timings of the complementary outputs Q and / Q from are aligned. Therefore, it is possible to eliminate the jitter (data indefinite period) that occurs in the outputs of the driver circuits 28 and 29 shown in FIG. 1 due to the timing difference between the outputs Q and / Q.

(B) L level reset signal / RSET
In response to this, a reset circuit 50 for setting the clock signal CLK to the H level and the clock signal CLKB to the L level is provided.

The flip-flops 26 and 27 are in a reset state when the reset signal / RSET goes low, and the output Q goes low and the output / Q goes high. In a normal flip-flop circuit, the reset signal / RSE
T is a second stage latch circuit (latch circuits LC2, LC3
Equivalent to) is also entered. However, in that case, the circuit configuration up to the outputs Q and / Q is different between the output Q side and the output / Q side. As a result, a timing shift occurs between the outputs Q and / Q. Therefore, in the flip-flop circuits 26 and 27, the second-stage latch circuits LC2 and LC3
The resetting of the flip-flop is realized by setting the clock signal CLKB to the L level without inputting the reset signal / RSET to. As a result, the output Q,
/ Q can be the same circuit configuration, output Q,
It is possible to prevent a timing shift between / Q.

(C) When testing the circuit of the data output section 20 shown in FIG. 1 (when the test signal DTEST is at H level)
In addition, the output switching circuit 80 outputs the input signal D from the phase compensation circuit 70 as the output Q and outputs the output / D from the inverter 91 as the output / Q.

The flip-flops 26 and 27 are on the data path in the data output section 20 shown in FIG. Therefore, when the normal flip-flops are provided instead of the flip-flops 26 and 27, the clock signal CLK1a must be supplied when the circuit is tested. However, since the flip-flops 26 and 27 are provided with the output switching circuit 80, the circuit of the data output section 20 can be tested without supplying the clock signal CLK1a during the test. That is, the test signal DTE
When ST goes to the H level, the path of the data (input signals D, / D) is changed and the inside of the flip-flop (LC1-LC
3, 60) so that the circuit does not pass through.

(D) A delay compensation circuit 70 is provided.

The delay compensation circuit 70 delays the input signal D supplied to the node N1 for a predetermined time and outputs it from the node N2. As a result, the timing of the signal D input to the NAND circuit 81 can be matched with the timing of the signal / D input to the NAND circuit 84. That is, the delay compensation circuit 70 is provided to adjust the delays in order to align the paths of the complementary data D and / D even during the test.

FIG. 6 shows the level shift circuit 3 shown in FIG.
It is a circuit diagram which shows the structure of 3,34. The level shift circuit shown in FIG. 6 has a P-channel MOS transistor PT1-
PT4 and N-channel MOS transistors NT1-NT
4 and.

P-channel MOS transistor PT1 and N-channel MOS transistor NT1 have power supply voltage V
It is connected in series between a second power supply node receiving DDH (3.3V) and a second ground node receiving ground voltage VSSH. The input signal IN is supplied to the gates of the P-channel MOS transistor PT1 and the N-channel MOS transistor NT1. The input signal IN is the data signal Data2 in the level shift circuit 33 and the strobe signal Stb2 in the level shift circuit 34.

P-channel MOS transistor PT2 and N-channel MOS transistor NT2 have power supply voltage V
It is connected in series between a first power supply node receiving DDL (2.5V) and a second ground node receiving ground voltage VSSH. The P-channel MOS transistor PT2 and the N-channel MOS transistor NT2 have gates P
Channel MOS transistor PT1 and N channel M
The voltage of the interconnection node of the OS transistor NT1 is supplied.

P-channel MOS transistor PT3 and N-channel MOS transistor NT3 have power supply voltage V
It is connected in series between a first power supply node receiving DDL (2.5V) and a second ground node receiving ground voltage VSSH. The P-channel MOS transistor PT3 and the N-channel MOS transistor NT3 have gates P
Channel MOS transistor PT2 and N channel M
The voltage of the interconnection node of the OS transistor NT2 is supplied.

P-channel MOS transistor PT4 and N-channel MOS transistor NT4 have power supply voltage V
It is connected in series between a first power supply node receiving DDL (2.5V) and a second ground node receiving ground voltage VSSH. The P-channel MOS transistor PT4 and the N-channel MOS transistor NT4 have gates P
Channel MOS transistor PT3 and N channel M
The voltage of the interconnection node of the OS transistor NT3 is supplied. P-channel MOS transistors PT4 and N
The voltage of the interconnection node of the channel MOS transistor NT4 becomes the output signal OUT of the level shift circuit. The output signal OUT is the data signal Data2a in the level shift circuit 33, and the strobe signal Stb2a in the level shift circuit 34.

Normally, there are two power supply voltages (VDDL, VD
DH), the ground voltage is also divided into two systems (V
SSL, VSSH) are provided. The circuit receiving the first power supply voltage VDDL has a first ground voltage (VSS
L) is supplied, and the second ground voltage (VSSH) is supplied to the circuit which receives the second power supply voltage (VDDH). Temporarily, in the level shift circuit shown in FIG. 6, the N-channel MOS transistors NT2-NT4 are connected to the ground voltage VS.
If it is connected to the first ground node that receives SL, it will be in an extremely unstable state, which will cause a malfunction at the time of level conversion and an increase in jitter. This is the ground voltage V
This is because even if the levels of SSL and VSS seen in terms of direct current are the same, they will be completely different in terms of alternating current depending on the connected circuit blocks. For example, the first
In this case, the circuit block connected to the ground node is a digital circuit block and the circuit block connected to the second ground node is an analog circuit or an input / output circuit.

However, in this level shift circuit, the N-channel MOS transistors NT1-NT4 are connected to the ground node on the circuit block side (H side) which receives the power supply voltage of 3.3 V (VDDH) before level conversion. There is. As a result, the amount of jitter generated in the level shift circuit can be reduced. In addition, it is possible to suppress malfunctions during level conversion.

Further, as shown in FIG. 7, a common ground voltage is used to provide a margin M for the input L level.
Can be increased. In FIG. 7, 2
Halve the threshold value Vt of the stage circuit (PT2, NT2)
(VDDL-VSSL). Further, the H side refers to a circuit block side that receives a power supply voltage of 3.3V (VDDH), and the L side refers to 2.5V (VDDL).
It refers to the circuit block side that receives the power supply voltage.

FIG. 8 shows the level shift circuit 2 shown in FIG.
It is a circuit diagram which shows the structure of 3-25. The level shift circuit shown in FIG. 8 has a P-channel MOS transistor PT11.
-PT16 and N-channel MOS transistor NT11
-NT16.

P-channel MOS transistor PT11 and N-channel MOS transistor NT11 are connected in series between a first power supply node receiving power supply voltage VDDL (2.5V) and a first ground node receiving ground voltage VSSL. It P-channel MOS transistor PT11
The input signal IN is supplied to the gate of the N-channel MOS transistor NT11. The input signal IN is the data signal Data1 in the level shift circuit 23, the strobe signal Stb1 in the level shift circuit 24, and the clock signal CLK1 in the level shift circuit 25.

P-channel MOS transistor PT12 and N-channel MOS transistor NT12 are connected in series between the first power supply node and the first ground node. The gates of the P-channel MOS transistor PT12 and the N-channel MOS transistor NT12 have P-channel MOS transistor PT11 and N-channel M, respectively.
The voltage of the interconnection node of the OS transistor NT11 is supplied.

P-channel MOS transistor PT13 and N-channel MOS transistor NT13 are connected in series between a second power supply node receiving power supply voltage VDDH (3.3V) and a first ground node. The voltage of the interconnection node of P channel MOS transistor PT14 and N channel MOS transistor NT14 is supplied to the gate of P channel MOS transistor PT13. The voltage of the interconnection node of P channel MOS transistor PT12 and N channel MOS transistor NT12 is supplied to the gate of N channel MOS transistor NT13.

P-channel MOS transistor PT14 and N-channel MOS transistor NT14 are connected in series between the second power supply node and the first ground node. The voltage of the interconnection node of P channel MOS transistor PT13 and N channel MOS transistor NT13 is supplied to the gate of P channel MOS transistor PT14. N-channel MOS transistor NT
The gate of 14 has a P-channel MOS transistor PT
11 and the voltage of the interconnection node of N-channel MOS transistor NT11 are supplied.

P-channel MOS transistor PT15 and N-channel MOS transistor NT15 are connected in series between the second power supply node and the first ground node. The P-channel MOS transistor PT15 and the N-channel MOS transistor NT15 have their gates at the gates of the P-channel MOS transistor PT14 and the N-channel M, respectively.
The voltage of the interconnection node of the OS transistor NT14 is supplied.

P-channel MOS transistor PT16 and N-channel MOS transistor NT16 are connected in series between the second power supply node and the first ground node. The P-channel MOS transistor PT15 and the N-channel MOS transistor NT16 have gates at the gates thereof.
The voltage of the interconnection node of the OS transistor NT15 is supplied. The voltage at the interconnection node of P-channel MOS transistor PT16 and N-channel MOS transistor NT16 becomes output signal OUT of the level shift circuit. The output signal OUT is the data signal Data1a in the level shift circuit 23, the strobe signal Stb1a in the level shift circuit 24, and the clock signal CLK1a in the level shift circuit 25.

In this level shift circuit, N channel M
The OS transistors NT11 to NT16 are connected to the ground node on the circuit block side (L side) that receives the power supply voltage of 2.5 V (VDDL) before level conversion. As a result, the amount of jitter generated in the level shift circuit can be reduced. In addition, it is possible to suppress malfunctions during level conversion.

Further, as shown in FIG. 9, the common ground voltage is used to provide a margin M for the input H level.
Can be increased. In FIG. 9, 2
Set the threshold value Vt of the stage circuit (PT12, NT12) to 1
/ 2 (VDDL-VSSL). Also, H
The side is the side of the circuit block that receives the power supply voltage of 3.3V (VDDH), and the L side is the side of 2.5V (VDD
L) means the circuit block side receiving the power supply voltage.

Next, the simulation result of the jitter component in the semiconductor integrated circuit device shown in FIG. 1 will be described.

FIG. 10 shows operation at 400 MHz (cycle 25
00ps) timing budget. In the figure, Draft represents the standard value, and MEI represents the simulation result of the circuit shown in FIG. Also, TX
Is a data output unit 20, RX is a data input unit 30, Cab
le is the jitter value of the cable section. Time T for one cycle
The data window (data window) is obtained by subtracting the jitter values of TX, RX, and Cable from (2500 ps), and its conceptual diagram is shown in FIG. In the MEI in FIG. 10, the standard value is used as it is for the jitter of the cable portion because it is not inside the chip.
140ps margin for TX and 23 for RX
There is a margin of 0 ps, and as a result, a Data Window of 810 ps, which is almost twice the standard, can be secured. As described above, since a wide data window can be secured, it is possible to secure a large operation margin, and it is possible to design a circuit that is extremely strong against process variations and characteristic variations due to power source voltage variations. In addition, since the operation margin is large, L of high-speed operation
The SI design can be easily performed, and there is an effect that the design period is shortened.

FIG. 12 shows the jitter value of each part shown in FIG. (A) shows the jitter in the data output section 20, and (b) shows the jitter in the data input section 30. Level conversion circuits 33, 3 of the data input unit 30
No. 4, unlike the data output unit 20, the worst case is 200p.
The jitter is s (jitter5). Since the flip-flops 26 and 27 are newly provided in the data output section 20, the jitter increases by that amount, but (b)
As shown in, the jitter jitter in the flip-flop circuit
Since ter2 is small, there is no problem. This is due to the jitter reduction effect of the flip-flops 26 and 27 as described above.

FIG. 13 is a chip layout schematic diagram of an IEEE 1394 physical layer chip.

The data input / output units 20, 30 shown in FIG.
Are included in the PORT units (PORT1, PORT2), and the logic circuit unit 10 includes the logic unit (LOGI).
Included in C). Data from the logic section is sent to the cable side terminals (TPA0, 1, NTPA0, 1, TPB0,
1, NTPB0, 1) to the cable, and the data from the cable is input to the logic section. The level conversion circuits 23-25, 33, 34 and the flip-flop circuits 26, 27 are arranged in a portion of the PORT section that is closer to the logic section.

[0104]

According to the semiconductor integrated circuit device of the present invention,
Since the flip-flop circuit is provided, the jitter component included in the output from the first level shift circuit can be reduced. As a result, a large data window can be secured and a large operation margin can be secured. Therefore, it is possible to design a circuit that is extremely strong with respect to process variations and characteristic variations due to power source voltage variations. Moreover, high-speed operation LSI design can be easily performed, and the design period can be shortened.

Further, the flip-flop circuit responds to either the rising edge or the falling edge of the clock signal from the second level shift circuit, and the first clock signal from the clock signal generating circuit responds to the logic circuit. Since it has a frequency twice as high as the frequency of the output signal from the unit, it is possible to remove the jitter component due to the second level shift circuit.

In the test mode in which the clock signal is stopped, the flip-flop circuit outputs the output signal from the first level shift circuit to the outside. Therefore, it is necessary to supply the clock signal to the flip-flop circuit again in the test mode. There is no.

Further, since the flip-flop circuit includes the timing adjustment circuit, the output signal from the first latch circuit and the inverted signal of the output signal from the first latch circuit are
The signals are supplied to the second latch circuit and the third latch circuit at the same timing.

Since the flip-flop circuit is provided with the delay compensating circuit, the output signal from the delay compensating circuit and the output signal from the inverter are output from the output switching circuit at the same timing in the test mode.

Since both the second latch circuit and the third latch circuit include the inverter and the clocked inverter, it is possible to suppress the occurrence of jitter in the flip-flop circuit. As a result, even if a flip-flop circuit is provided in the data input / output path, the jitter hardly increases.

Further, the active reset signal is not supplied to the second and third latch circuits, and the inverted signal supplied to the clocked inverter is inactivated, so that the output signal from the second latch circuit is It is possible to prevent a timing shift from occurring between the complementary signal to the output signal from the third latch circuit.

In the first level shift circuit, the first level shift circuit
Since the inverter and the first and second N-channel MOS transistors are commonly connected to the first ground node, the amount of jitter generated in the first level shift circuit can be reduced.

Since the data input / output unit of the semiconductor integrated circuit device according to the present invention has the multi-stage structure of the first and second amplifiers, the input signal from the outside is a signal having a very small amplitude level (300 mV or less). Even if there is, it can be amplified at high speed.

Further, since the clamp circuit is provided, it is possible to suppress the generation of the jitter component due to the difference in the data width. As a result, high-speed amplification operation can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a semiconductor integrated circuit device (IEEE1394 physical layer) according to an embodiment of the present invention.

FIG. 2 shows a data signal Data1a and a strobe signal St.
It is a figure for demonstrating the increase of the jitter in b1a and the clock signal CLK1a.

FIG. 3 is a block diagram showing a schematic configuration of a receiver circuit shown in FIG.

FIG. 4 is a diagram showing a difference in output of an amplifier circuit depending on the presence or absence of a clamp circuit.

5 is a block diagram showing a configuration of a flip-flop shown in FIG.

6 is a circuit diagram showing a configuration of a level shift circuit shown in FIG.

FIG. 7 is a diagram showing a margin with respect to an input L level.

8 is a circuit diagram showing a configuration of a level shift circuit shown in FIG.

FIG. 9 is a diagram showing a margin with respect to an input H level.

FIG. 10 is a diagram showing a timing budget when operating at 400 MHz.

FIG. 11 is a conceptual diagram of Data Window (data window).

FIG. 12 is a diagram showing the jitter value of each part shown in FIG. 1, where (a) shows the jitter value in the data output part,
(B) represents the jitter in the data input section.

FIG. 13 is a chip layout schematic diagram of an IEEE 1394 physical layer chip.

FIG. 14 is a circuit diagram showing a configuration of a conventional level shift circuit.

FIG. 15 is a circuit diagram showing a configuration of a conventional level shift circuit.

[Explanation of symbols]

10 Logic circuit section 21 PLL circuit 23-25, 33, 34 Level shift circuit 26,27 flip-flop circuit 30,31 Receiver circuit 50 reset circuit 60 Timing adjustment circuit 70 Delay compensation circuit 80 output switching circuit LC1-LC3 latch circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H03K 5/02 H03K 19/00 101D (72) Inventor Takashi Hirata 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. ( 72) Inventor Yoshihide Komatsu 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Hiroyuki Yamauchi, 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References 58-157224 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 7/02 H03K 19/0185 H04L 25/02 H04L 25/03 H03K 3/037 H03K 5/02

Claims (8)

(57) [Claims] 1. A first power supply voltage at a first voltage level,
A logic circuit section that receives a first ground voltage and generates an output signal having an amplitude of the first voltage level; and a logic circuit section that converts the amplitude of the output signal from the logic circuit section into an amplitude of a second voltage level. 1 level shift circuit, receiving the first power supply voltage and the first ground voltage,
A first clock signal having an amplitude of a first voltage level
And a first clock signal from the clock signal generating circuit
The amplitude is converted into the amplitude of the second voltage level and output.
A second level shift circuit, a second power supply voltage of the second voltage level, and a second ground
Voltage and output from the second level shift circuit.
Whether the clock signal is rising or falling
The first level shift circuit in response to one of the edges
Latch the output signal from the
The clock signal output from the second level shift circuit
And a flip-flop circuit which outputs in response to the signal. 2. The logic circuit unit according to claim 1 , wherein the logic circuit unit operates in response to a first clock signal from the clock signal generation circuit, and the first clock signal from the clock signal generation circuit is the A semiconductor integrated circuit device having a frequency twice that of an output signal from the logic circuit section. 3. The semiconductor integrated circuit according to claim 1 , wherein the flip-flop circuit outputs the output signal from the first level shift circuit to the outside in a test mode in which the clock signal is stopped. apparatus. 4. The method of claim 1 or claim 2, wherein the flip-flop circuit is responsive to a clock signal from the second level shift circuit, for latching the output signal from said first level shift circuit A first latch circuit, an output signal from the first latch circuit and an inverted signal of the output signal from the first latch circuit, and the output signal and the inverted signal from the second level shift circuit. A timing adjustment circuit that outputs in response to a clock signal; a second latch circuit that latches the output signal from the timing adjustment circuit in response to an inverted signal of the clock signal from the second level shift circuit; A third latch for latching the inverted signal from the timing adjustment circuit in response to the inverted signal of the clock signal from the second level shift circuit. The semiconductor integrated circuit device which comprises a circuit. 5. The flip-flop circuit according to claim 4 , further comprising an inverter that inverts an output signal from the first level shift circuit, and delays an output signal from the first level shift circuit by a predetermined time. And a delay compensation circuit for outputting the output signal from the second latch circuit and the output signal from the third latch circuit to the outside in the normal mode, and in the test mode in which the first clock signal is stopped. A semiconductor integrated circuit device comprising: an output switching circuit that outputs the output signal from the delay compensation circuit and the output signal from the inverter to the outside. 6. The inverter according to claim 4 , wherein the second latch circuit and the third latch circuit both invert the signal from the timing adjustment circuit, and the clock signal from the second level shift circuit. A clocked inverter for inverting the output from the inverter and supplying the inverted output to the input of the inverter in response to the inversion signal of 1. 7. The flip-flop circuit according to claim 6 , further receiving an active reset signal, activating the clock signal from the second level shift circuit, and further activating the clock signal from the second level shift circuit. A semiconductor integrated circuit device comprising: a reset circuit for inactivating an inverted signal of a clock signal, wherein the first latch circuit receives an active reset signal and outputs a signal of a first logic level. 8. The first level shift circuit according to claim 1 , wherein the first level shift circuit is provided between a first power supply node receiving the first power supply voltage and a first ground node receiving the first ground voltage. A connected first inverter, a first P-channel M connected between a second power supply node receiving the second power supply voltage and the first ground node.
A first N-channel MO that is connected between the OS transistor and the drain of the first P-channel MOS transistor and the first ground node and receives the output of the first inverter at its gate.
An S transistor, a source connected to the second power supply node, a drain connected to the gate of the first P channel MOS transistor, the first P channel MOS transistor and the first N channel MOS transistor A second P-channel MOS transistor having a gate receiving the voltage of the interconnection node of, and a drain of the second P-channel MOS transistor and the first ground node, and an input of the first inverter. Second N-channel MO receiving gate at
A semiconductor integrated circuit device including an S transistor.