JP3524644B2 - Clock recovery device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock reproducing apparatus for reproducing a reference clock for reproduction on the receiving side based on a time reference value sent from the transmitting side in a digital data transmitting system.

[0002]

2. Description of the Related Art In conventional television broadcasting, a real-time video signal output from a television camera or a recording medium reproducing device is transmitted / transmitted, and a receiver processes and displays the received real-time video signal. There is. The recording format of the above recording medium is basically V
It was suitable for real-time reproduction as represented by TR and VD (video disc). In recent years, a large amount of recording medium is required for real-time recording / reproduction, transmission / transmission of the video signal as described above, and a wide frequency band is required. How to do it has been studied. However, image data of televisions, especially moving image data, generally has a huge amount of data, and if it is transmitted as it is, a wide band is required due to a high bit rate, and if it is stored as it is, a huge recording capacity is required. Becomes

As a method for solving these problems, there is a moving picture compression applying a digital image coding technique. As an example of a moving picture compression standard, M is used as one of encoding methods for highly efficient compression of high quality digital video / audio signals.
PEG (Moving Picture s Expert)
There is MPEG2 (international standard ISO / IEC13818-1) proposed by T. Group. This MPE
In G2, a DCT (Discrete Cosine Tra) for reducing the amount of information in the spatial direction of an image.
nsfom: Discrete cosine transform) to encode the input image itself (intra-frame encoding), inter-frame predictive encoding that encodes the difference between the input image and the previous reproduced image, predict an intermediate image from the preceding and following images Bi-directional predictive coding and motion compensation (MC: Motion Compensation) effective for reducing these prediction error powers in the temporal direction.
technology) is used to compress the moving image.

On the other hand, the digital data thus compressed can be transmitted in a packet format.
This enables asynchronous transmission. Also, by increasing the bit rate, time division multiplexing of multiple channels can be performed. In either case, there is no excess or deficiency of data on the transmitting side and the receiving side, that is, there is a delay when the demodulating speed on the receiving side is compared with the speed of the transmitted data processing for a long time. In addition, it is required that the video signal is output based on a clock having a predetermined period. In such a case, the receiving side has an internal clock for generating a reference clock that should be used as a reference for reproduction, compares the clock reference data that is periodically transmitted from the transmitting side with the count value of the internal clock, and detects the sequential error. A method of correcting the frequency of the internal clock is used to correct the.

FIG. 4 schematically shows a transport packet for transmitting image data according to MPEG2, and is assumed to be transmitted in order from left to right on the paper surface. This transport packet 1, 2 has a certain 1
It is assumed to be responsible for the image data of one program. Each of the transport packets 1 and 2 is provided with a fixed-length header 3 of 4 bytes, and the header of the header 3 is an 8-bit synchronization signal for detecting the beginning of the transport packet ( 0x47 data)
A synchronization bit 4 of each of the packets is arranged, and a PID (packet identifier) 5 of 13 bits is provided at a predetermined position of the header 3. The attribute of the individual stream of the transport packet, that is, which program, image The contents of the packet such as voice or voice are shown.

Further, the header 3 is provided with an adaptation field control 6, and this adaptation field control 6
It is described by 2 bits whether or not the optional field 7 following the field control 6 is included. This optional field 7 contains an image and audio demodulator M
ST as the time reference in the PEG2 system demodulator
PCR (program time reference reference value) 8 is provided as information for setting and calibrating the value of C (synchronization information serving as a reference) to a value intended on the transmitting side. The upper bits of the adaptation field control 6 indicate the presence or absence of the optional field 7, and the lower bits indicate the presence or absence of the payload 9 (execution data) described later. The payload 9 is a portion in which actual image or audio data is stored. When the transport packet does not include the optional field 7, variable length data such as extended spare is provided so that the transport packet always has a fixed length of 188 bytes. Further, the data length of the PCR is defined as 6 bytes including 33 bits for the valid data portion and invalid bits.
The distance to the leading bit of CR is fixed (the leading bit of PCR is the 49th bit). This PCR is actually inserted for each program, for example, every 0.1 seconds. Further, in MPEG2, the standard book of the position of the PCR the valid data portion (hereinafter, referred to as PCR field) for defining the last bit of the PCR at the time of arrival of the last bit of the PCR field is the decoder side It is required to modify the clock according to the values shown.

Next, a method of demodulating a transport packet will be described with reference to FIG. For simplification, 1
Only the block diagram of the packet receiver for the program will be described. In FIG. 5, reference numeral 10 is an input terminal, and a digital signal including a transport packet is input from the input terminal 10 to the synchronization detection circuit 11. The output of the synchronization detection circuit 11 is supplied to the CPU 14 via the buffer circuit 13. C
The PU 14 is connected to send a command to the PCR detection circuit 12. The output of the synchronization detection circuit 11 is PC
It is connected to the R detection circuit 12, and the output of the PCR detection circuit 12 is connected to one input of the comparison circuit 23 provided in the CPU 14. Further, the output of the PCR detection circuit 12 is connected to the counter 24 in order to send a later-described latch signal. The output of the counter 24 is connected to the other input of the comparison circuit 23. The output of the comparison circuit 23 is PW
It is supplied to the M (pulse width modulation) wave generation circuit 26, and this P
The output of the WM wave generating circuit 26 is smoothed by an LPF (low-pass filter) 27, and the obtained DC voltage is connected to control a VCO (voltage controlled oscillator) 28. The counter 24, the comparison circuit 23, and the PWM wave generation circuit 2 described above.
6, the LPF 27 and the VCO 28 form an internal clock circuit, and the output of the VCO 28 is the counter 24,
It is connected to the CPU 14 and the video signal decoder 17, respectively.

The video signal output from the CPU 14 is supplied to the video signal decoder 17 via the buffer circuit 15, where the 27 MHz signal from the VCO 28 is used as a clock signal to demodulate the video signal according to the MPEG2 system. The demodulated output is converted into a standard television signal by the NTSC encoder 18 and output to the output terminal 19.
On the other hand, the audio signal output from the CPU 14 is supplied to the audio signal decoder 20 via the buffer circuit 16, where V
A 24.5 MHz signal obtained by using a newly provided PLL circuit 29 and VCO 28 from the signal from the CO 28 is used as a clock signal to demodulate an audio signal according to the MPEG system. The demodulated output is converted into an analog signal via a DAC (digital / analog conversion circuit) 21, and an output terminal 22
Is output to.

In such a configuration, for example, one program is 4.
A 21 Mbps transport stream in which four 713878 Mbps program streams are multiplexed is transmitted and input to the input terminal 10. Sync detection circuit 1
1 detects the data (0x47) of the sync bit 4 which is the packet sync signal from the incoming bit string, and supplies this sync bit 4 to the PCR detection circuit 12 together with the bit string. Further, each packet whose delimiter has been identified by the synchronization detection circuit 11 is once taken into the buffer circuit 13 and then taken into the CPU 14 as appropriate. Sync detection circuit 1
In 1, accidentally in other data such as execution data,
Since the same data (0x47) as the sync bit 4 may appear, the true packet delimiter can be determined by continuously detecting the data (0x47) of the sync bit 4 that arrives at substantially predetermined intervals many times. I try to identify.

Further, the CPU 14 detects the PID 5 and the adaptation field control 6 in the received packet. According to the detected contents of the PID 5 and the adaptation field control 6, if it is determined that the packet includes image data or audio data of the program to be reproduced, those data are extracted and the image data is temporarily stored in the buffer circuit 15, Demodulate with the video signal decoder 17,
It is sent to the output terminal 19 via the NTSC encoder 18. The audio data is once stored in the buffer circuit 16, demodulated by the audio signal decoder 20, and sent to the output terminal 22 via the DAC 21. If the packet includes the PCR8 of the program, the CPU 14
The R detection circuit 12 is instructed to detect the PCR field in which the PCR 8 is described. PCR detection circuit 12
Detects a PCR field at a predetermined position from the synchronization bit 4, extracts and decodes the data of PCR8, and as a result, compares the numerical value (reference value) indicated by PCR8 with the comparison circuit 23.
To one input end. PCR detection circuit 12 which and concurrent to detects the arrival of the last bit of the PCR field, and supplies the latched signal to the counter 24 when the last bit arrives.

The output of the VCO 28 is output to the CPU 14 and the video demodulation circuit 17 as a reproduced reference clock, and is also supplied to the counter 24 to count the number of waves. Counting is always continued, the count value of the counter 24 is latched at the timing of the supplied latch signal (the count itself does not stop, and the intermediate value at that time is held separately), and the comparison circuit 23 is input to the other input terminal. In the comparison circuit 23, the output of the PCR detection circuit 12 and the counter 2
The count values of the outputs of 4 are compared to obtain a difference (error) indicating the advance or delay of the internal clock, and a signal corresponding to this is sent to the PWM wave generation circuit 26. The PWM wave generation circuit 26 outputs a PWM wave in which the difference is reflected in the pulse width by this signal. The LPF 27 removes not only the fundamental frequency component of the PWM wave and its harmonic components but also a relatively fast variation component of the difference that is successively obtained, and outputs it as a DC voltage to the VCO 28, thereby reducing the oscillation frequency of the VCO 28 by this difference. Correct in the direction. In order to comply with the above-mentioned MPEG2 standard, the VCO 28 is controlled by PCR in the comparison and PWM wave generation described above.
It should be done at the last bit of the field. As described above, the reference clock for reproducing and reproducing the original image data without excess or deficiency is reproduced.

[0012]

As described above, MPE is used.
For the configuration to reproduce the clock as specified by G2, P
Since the detection means for detecting the time point of the last bit of the CR field is necessary and the decoding of the PCR must be completed by that time, the configuration becomes complicated. That is, PCR
When the clock arrives, correcting the clock based on the PCR means that the decoding of the PCR must be completed and the comparison must be completed by that time, which is technically difficult. . That is, a high-speed circuit is required to realize with hardware, and an extremely high-speed CPU is required to realize with software. The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a clock recovery device that can be simply configured with software and hardware.

[0013]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and in order to reproduce data to be reproduced on the receiving side based on a reference clock, which are sequentially transmitted in packets from the transmitting side. A clock reproducing device for reproducing the reference clock of 1. at the receiving side, wherein the packet has a predetermined synchronization bit at the head, and at least some of the packets have a fixed number of bits from the head of the packet as a sampling position. The clock reproducing device has a field for describing a PCR , and a clock detecting device for detecting a synchronization bit of a packet, a PCR detecting means for detecting a field and detecting a PCR described in this field, and a clock frequency. oscillation frequency is controlled by a control signal for modifying the variable <br/> frequency oscillating hand that this oscillation output and reference clock When, counting means for counting a reference clock, storage means for storing a count value of the reference clock of the detection time point of synchronization bits, only when the field containing the PCR is detected, the PCR described in the field And a comparison unit that outputs a control signal based on at least the count value of the current packet in which the field is detected. Further, when the sampling position is the last bit of the field, the output time of the control signal is a predetermined time after the detection time of the last bit of the field.

[0014]

[Action] In the clock regeneration apparatus of the present invention, using the oscillation output of the variable frequency oscillating means as a reference clock, counting means for counting the reference clock. When the synchronization detection means detects the synchronization bit of the packet, the storage means stores the count value at this point. On the other hand, the PCR detecting means detects the field describing the PCR in the packet and obtains the PCR described therein. The means of comparison is this PCR
A control signal for controlling the oscillation frequency of the variable frequency oscillation means is output based on the PCR and the count value of the reference clock only when a field including the is detected. This allows
The oscillating frequency of the variable frequency oscillating means is a certain distance (time difference) in which the cumulative value of the clock wave number is a value based on PCR.
Since the feedback control is performed so as to follow with a deviation of a minute, it is possible to regenerate the reference clock with no advance or delay when viewed from the transmitting side for a long time. Further, in the present invention, the count value storage timing of the reference clock is
Because they utilize that may not match the sampling position of the PCR, also it will be may not match the also control timing of the variable frequency oscillation means, samples of PCR
The control was performed after a predetermined time from the position of conversion . As a result, the processing speed of the hardware or software that performs such processing can be reduced.

[0015]

EXAMPLE An example of the present invention will be described with reference to FIG.
In FIG. 1, portions corresponding to the blocks of the conventional example shown in FIG. 5 are designated by the same reference numerals, and duplicate description will be omitted. In the block diagram, the difference is that the output of the PCR detection circuit 12 is connected to the counter 24 as a latch signal in the conventional example, whereas in the embodiment of the present invention, the synchronization detection circuit 1
The output of 1 is directly connected to the counter 24 as a latch signal. Details of the operation will be described below. First, the bit string transmitted in the transport packet is input to the synchronization detection circuit 11 as the synchronization detection means via the input terminal 10. When the synchronization detection circuit 11 detects the data (0x47) of the synchronization bit 4 which is the packet synchronization signal from the incoming bit string, the synchronization bit 4 together with the bit string is sent to the PC as PCR detecting means.
It is supplied to the R detection circuit 12.

Further, each packet whose delimiter has been identified by the synchronization detection circuit 11 is passed through the buffer circuit 13 to the C
It is taken into PU14. When the CPU 14 detects the PID 5 and the adaptation field control 6 in the captured packet and determines that the packet contains image data or audio data of the program to be reproduced, these data are extracted and the buffer circuit 15 respectively. , 16 are sent. At the same time, the CPU 14 controls the PCR 8 of the program.
It is determined whether the packet contains the PCR8 of the program, and if the packet contains the PCR8 of the program, the PCR detection circuit 12 is instructed to detect the PCR field in which the PCR8 is described. Upon receiving this command from the CPU 14, the PCR detection circuit 12 detects the PCR field, extracts the data about the PCR 8 described therein, and supplies it to the comparison circuit 23 as a comparison means as one input. Further, the synchronization detection circuit 11 supplies the detected synchronization bit 4 as a latch signal to the counter 24 as the counting means. Counter 24 when the synchronization bit 4 is input, it latches the count value of VCO28 output of a variable frequency oscillating means. In other words, even when the packet has no relation to the program, all the packets are latched, and the count value (interim progress value) at that time is supplied to the comparison circuit 23 as the other input. However, the CPU 14 makes the comparison only when the count value of the packet including the PCR 8 of the program is obtained.

(1) When the PCR value is an increasing value Here, a method of comparing the count value of the counter 24 and the PCR value will be described with reference to the flowchart of FIG. Here PCR values used denote advances clocks from PCR target the reduction position of the previous (increase value). When the packet receiving device is turned on, the counter 24 is reset and starts counting immediately, and when it reaches a predetermined maximum value (which should be sufficiently larger than the predicted increase value), it returns to 0 and starts counting again. It is designed to repeat itself. The symbols used in the flowcharts have the following meanings. CC: current count value of counter 24 CM: midway progress value of counter 24 CML: midway progress value one time before First, in step S1, the synchronization detection circuit 11 monitors the arrival of the synchronization signal (synchronization bit 4) and performs synchronization. If no signal is detected, the process returns to step S1. When the synchronization signal is detected, the current count value CC of the counter 24 is set to the midway progress value CM.
The latch signal for storing as is output to the counter 24. That is, in step S2, the counter 24 latches the current count value CC, and the CPU 14 stores this value as the midway progress value CM. Next, the CPU 14 detects the PID in the packet fetched in step S3. Then, the process proceeds to step S4, and it is determined whether the packet includes the PCR of the program by the detected PID.

If no PCR is included, the process returns to step S1 to monitor the arrival of the next synchronization signal. If the PCR is included, the process proceeds to the next step S5. In step S5, the CPU 14 stores the midway progress value CM of the counter 24 stored in step S2 as the previous midway progress value CML for the midway progress value CM when the PCR comes next. It should be noted that the steps up to this point are preliminary operations until the PCR of the first program is detected after the power is turned on. Then, the process proceeds to step S6, and the arrival of the sync signal is monitored. If not detected, the process returns to step S6. When the synchronization signal is detected, a latch signal for storing the current count value CC of the counter 24 as the midway progress value CM is output to the counter 24. That is, the process proceeds to step S7, the current count value CC of the counter 24 is latched, and the CPU 14 stores this value as the midway progress value CM. Next, the CPU 14
Detects the PID in the fetched packet in step S8. Then, the process proceeds to step S9 and the detected PI
Based on D, it is determined whether the packet includes the PCR of the program.

If the PCR is not included, the process returns to step S6 and the arrival of the next synchronization signal is monitored. When the PCR is included, the CPU 14 causes the PCR detection circuit 12 to read the value and input it to the comparison circuit 23, and then proceeds to the next step S10. In step S10, the CPU 14 sets the current intermediate progress value C of the counter 24 stored in step S7.
Subtract the intermediate progress value CML of the previous time from M, and increase value ΔCC
Is input to the comparison circuit 23. If the difference becomes negative, it means that the maximum value was exceeded during counting, so the correction is performed by adding the maximum value. Next, proceeding to step S11, the CPU 14 stores the current midway progress value CM as the previous midway progress value CML for the midway progress value CM when the PCR comes next. After that, in step S12, the comparison circuit 23 compares the increment value ΔCC with the PCR value stored in step S9. Then, the process proceeds to step S13 and the comparison circuit 23
Generates a control signal for correcting the clock frequency according to the comparison result of step S12, and the PWM wave generation circuit 26
Supply to. Then, the process returns to step S6, and the arrival of the next synchronization signal is monitored.

(2) When the PCR value is a cumulative value When the PCR is a cumulative value and is cycled with a certain maximum value, for example, the maximum value is set to 10,000, and 1000, 2000, ... For each PCR. 10,000 (= 0), 1
In the case of the counting method such as 000, ..., The counter 24 is also set so as to cyclically count the maximum value. The flowchart in this case is shown in FIG.
Even in this case, the counter 24 is reset when the power of the packet receiving device is turned on, and immediately starts counting.
However, even if the maximum value is the same as the PCR value and they circulate in synchronization, the numerical values themselves do not necessarily match.
Steps S1 to S5 are for obtaining the difference CA between the two by the PCR that first arrives after the power is turned on. First, in step S1, the sync detection circuit 11 monitors the arrival of the sync signal, and if no sync signal is detected, the process returns to step S1. When the synchronization signal is detected, a latch signal for storing the current count value CC of the counter 24 as the midway progress value CM is output to the counter 24. That is, the process proceeds to step S2 and the counter
4 latches the present count value CC, and the CPU 14 stores this value as the midway progress value CM. Next, the CPU 14 detects the PID in the packet fetched in step S3. Then, the process proceeds to step S4, and it is determined from the detected PID whether or not the packet includes the PCR of the program. If the PCR is not included, the process returns to step S1 and the arrival of the next synchronization signal is monitored. When the PCR is included, the CPU 14 causes the PCR detection circuit 12 to read and store the value, and the process proceeds to step S5. In step S5, the CPU 14 sets P stored in step S4.
The midway progress value CM stored in step S2 is subtracted from the CR value and stored as a deviation CA. Then, step S6
Then, the arrival of the sync signal is monitored. If not detected, the process returns to step S6. When the synchronization signal is detected, a latch signal for storing the current count value CC of the counter 24 as the midway progress value CM is output to the counter 24.

That is, the process proceeds to step S7 and the counter 2
The current count value CC of 4 is latched, and the CPU 14 stores this value as the midway progress value CM. Next, the CPU 14 detects the PID in the received packet in step S8. Then, the process proceeds to step S9, and it is determined from the detected PID whether or not the packet includes the PCR of the program. If the PCR is not included, the process returns to step S6,
Monitor the arrival of the next sync signal. When the PCR is included, the CPU 14 causes the PCR detection circuit 12 to read the value and input it to the comparison circuit 23, and the next step S10.
Move to. In step S10, the CPU 14 sets the midway progress value CM stored in step S7 and the step S5.
The difference CA stored in step S3 is added and input to the comparison circuit 23. The comparison circuit 23 compares this added value with the PCR value input in step S9. Then, in step S11, the comparison circuit 23 generates a control signal for correcting the clock frequency according to the comparison result in step S10, and supplies the control signal to the PWM wave generation circuit 26. Then, the process returns to step S6, and the arrival of the next synchronization signal is monitored. In this method, since the numerical value circulates with the maximum value, the result of comparison may deviate by the maximum value if the same calculation is always performed. In such a case, the maximum value is appropriately adjusted to correct the comparison result so that it falls within the correct range.

In both of the above (1) and (2),
The oscillation frequency of the VCO 28 is feedback-controlled so that the error of the cumulative value of the clock wave number with respect to the value based on PCR converges. Here, finally timing for controlling the VCO28 need not be (the last bit of the PCR field in MPEG2) PCR target present reduction position,
Even after this, if the timing variation is negligible, it can be determined that the predetermined time has passed. That is, in the present invention, the timing of reading the current clock count value is set as the timing of the synchronization signal, and P
Since even when deviated from the CR target the reduction position has been made in view of that it is possible the feedback control, no longer controls the timing of the VCO28 is PCR targets
It does not have to be the realization position. Therefore, the processing speed of the hardware or software for executing the above steps does not need to be particularly high, and a general-purpose one can be used, and thus the configuration of the device can be simplified.

In the description of the embodiment of the present invention, the digital data transmission method is described as a packet, but the present invention is not limited to this, and the packet format need not be a fixed length. That is, it may be of a type in which there is at least some identification information or a synchronization signal with respect to the clock reference signal, and the clock reference signal is transmitted at a fixed distance (time) from the identification information or the synchronization signal. Further, the digital data to be transmitted is not limited to compressed image data such as MPEG, but may be audio data, M
It may be IDI data, game software, computer software, or the like. That is, the present invention can be applied to general data communication in which a predetermined reference clock is reproduced on the receiving side based on the transmitted clock reference and data is reproduced based on this.

[0024]

As described above, in the present invention, the reference clock counting time is set as the packet synchronization signal detection time, so that the means for detecting the PCR sampling position becomes unnecessary. The device can be simplified. Further, the oscillation frequency control timing of the variable frequency oscillating means so was after a predetermined time than the sampling position location of PCR, it is possible to slow down hardware or software, it is possible to further simplify the apparatus .

[Brief description of drawings]

FIG. 1 is a block diagram of a packet reception device according to an embodiment of the present invention.

FIG. 2 is a flowchart of the clock recovery device according to the present invention (Example 1).

FIG. 3 is a flowchart of a clock recovery device according to the present invention (second embodiment).

FIG. 4 is a schematic diagram of a transport packet for transmitting image data according to MPEG2.

FIG. 5 is a block diagram of a conventional packet receiving device.

[Explanation of symbols]

10 ... Input terminal 11 ... Synchronous detection circuit 12 ... PCR detection circuit 13 ... Buffer circuit 14 ... CPU 23 ... Comparison circuit 24 ... Counter 26 ... PWM wave generation circuit 27 ... LPF 28 ... VCO

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Katsuya Nakazawa 4-15-5 Omorinishi, Ota-ku, Tokyo Pioneer Co., Ltd. Omori Plant (72) Inventor Kenji Tsunekawa 4-15 Omorinishi, Ota-ku, Tokyo No. 5 Pioneer Co., Ltd. Omori Factory (56) Reference JP-A-7-46592 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N ^7/ 24-7/68

Claims (2)

(57) [Claims] 1. A clock regenerator for regenerating, on the receiving side, the reference clock for regenerating on the receiving side data to be regenerated on the basis of the reference clock, which is sequentially transmitted from the transmitting side in packets. packet has at the top a predetermined synchronization bit, at least a portion of the packet one from the head of the packet
There is a field that describes a PCR with a constant number of bits as a sampling position. The clock reproduction device detects a synchronization bit of the packet and a field that detects the field and is described in this field. a PCR detection means for detecting the PCR, a variable <br/> frequency oscillation means for the oscillation output before and Kimoto reference clock oscillation frequency is controlled by the control signal for clock frequency correction, before Kimoto quasi counting means for counting the clock, storage means for storing a count value of the previous Kimoto reference clock detection time point of the synchronization bit, only when the field containing the PCR is detected, the PCR described in the field And comparing means for outputting the control signal based on at least the count value in the current packet in which the field is detected Clock reproducing apparatus characterized by comprising a. 2. The sampling position is the last bit of the field, and the output time of the control signal is the last bit of the field.
2. The clock regenerator according to claim 1, which is after a predetermined time from the point of detection of .