JP3523294B2 - State storage circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a state storage circuit for storing a logic state by means of cross-coupled logic elements.

[0002]

2. Description of the Related Art A typical conventional example of a state storage circuit for storing logic states by cross-coupled logic elements is shown in FIGS.

The circuit of FIG. 1 is an example of a circuit having a switch element, and includes a first switch 11 and an inverter 1 in series.
2 and 13 and the second switch 14 in parallel with these inverters, the upstream first switch 11 is turned on by the control signal C for controlling the timing of sampling and hold for writing, and the input signal (data) D is supplied. Taking in (sampling), the second switch 14 on the downstream side is turned on by the inverted signal CB of the control signal C to maintain (hold) the logic state Q.

The circuit of FIG. 2 is a D-type flip-flop circuit composed of an inverter 21 and NOR gates 22 to 25, and a NOR gate cross-coupled when CB = H (high level) has its logic state Q. Maintain and CB
= L (low level), the logical state Q is updated by the input signal D. The circuit of FIG. 3 has an inverter 31 and a NAN.
This is a well-known D-type flip-flop circuit composed of D gates 32 to 35, and performs substantially the same operation as the circuit of FIG.

[0005]

However, in the conventional state memory circuit as described above, the input signal D happens to be almost coincident with the transition from the "writable period" to the "unwritable period" by the write control signal C. When the level changes from the H level to the L level or from the L level to the H level, the input voltage of each element may become the same as the level of the logic threshold value. At this time, the input of each element does not change as it is. Therefore, there is no force for the output of each element to change to the H level or the L level, so that the output may be stabilized at the intermediate level, or may remain at the intermediate level for a long period (the broken line "conventional in FIG. 6"). Q in case of)).

At this time, when the state storage circuit outputs the intermediate level output Q, if there is a next-stage logic element or a plurality of next-stage logic elements driven by this state storage circuit, the logic element having that logic element is There is a serious problem to be solved that an erroneous logical operation which is not intended by the user occurs because the intermediate level is determined to be the H level, and the other is determined to be the L level. It was

The present invention has been made in view of the above points, and an object thereof is to provide a state memory circuit capable of quickly exiting from an intermediate level state and thereby preventing an unexpected logic operation from occurring. It is in.

[0008]

In order to achieve the above object, the present invention provides a data signal to a cross-coupled logic element according to a write control signal for controlling the timing of sample and hold for writing data. In a state storage circuit for storing a delay control signal for delaying the write control signal by a predetermined time, and using the delay signal , at least one logic element of the cross-coupled logic elements The logic threshold is changed after a predetermined time from the write control signal.
And a means for moving it.

Here, it is preferable that the delay signal is generated from a delay element or a D-type flip-flop circuit that outputs a signal obtained by delaying the write control signal for a predetermined time.

[0010]

In the present invention, in order to change the logic threshold value of at least one logic element among the cross-coupled logic elements, for example, from the delay circuit 46 which delays the write control signal C (see FIG. 4). Using the output delay signal, a specific M included in a logic element 42
Controls the voltage applied to the gate of the OS transistor. As a result, even when the cross-coupled logic element is stabilized at the intermediate level, the logic threshold value of at least one logic element changes after a certain delay time after the end of the writable period by the write control signal. Due to this, the logic element is given a force to change its output to the H level or the L level, and can quickly escape from the unstable state of the intermediate output level. Thus, unexpected logic operation is prevented from occurring in the subsequent logic element.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 4 shows a state storage circuit according to an embodiment of the present invention. In the figure, 41 and 44 are switch circuits for turning on / off the signal flow according to a write control signal C for controlling the timing of write sampling and hold of the input signal D and an inverted signal CB of the write control signal, for example, FIG. A complementary switch using a CMOS transistor as shown in can be applied.

In the complementary switch shown in FIG. 5,
The write control signal C drives the gate of the N-type transistor 51, the signal CB obtained by inverting the control signal C by the inverter 45 drives the gate of the P-type transistor 52, and C = H (that is, CB = L). The circuit is ON when
Becomes an input signal.

In the present embodiment shown in FIG. 4, between the input side of the first inverter 42 and the output side of the second inverter 43, which are connected in series with the upstream first switch circuit 41, The second switch circuit 44 is connected. Then, when the first switch circuit 41 is ON, the second switch circuit 44 is OFF and the input signal D is sampled, and when the first switch circuit 41 is OFF, the second switch circuit 41 is OFF.
The switch circuit 44 is turned on and holds the logic state Q.

Reference numeral 46 is a delay circuit which outputs a delay signal C'which is obtained by delaying the write control C by a predetermined time. The delay signal C ′ is applied to the gate of the N-type transistor 42-1 included in the inverter 42. That is, as shown in FIG. 6, when the delay signal C ′ is at the H level, the N-type transistor 42-1 makes a state transition to the ON direction, so that the logic threshold value of the inverter 42 is a low voltage (T
h1) while the delayed signal C'is at L level, the N-type transistor 42-1 is turned off, and the operation of the P-type transistor 42-2 connected in series with this N-type transistor 42-1 is performed. Causes the logic threshold value of the inverter 42 to shift to a high voltage (Th2).

Next, the operation peculiar to this embodiment will be described with reference to FIGS.

That is, the level of the input signal D gradually rises while the write control signal C is at the H level, and the logic threshold value Th1 of the inverter 42 is set at the end of the writable period (sample period) T1. FIG. 6 shows the operation when exceeding. As is clear from this figure, the delay signal C'is H at the end of the writable period T1.
Since it is at the level, the output Q exhibits an intermediate value between the H level and the L level. However, when the delayed signal C ′ reaches the L level thereafter, the logical threshold value of the inverter 42 becomes Th.
Change to 2.

As a result, the logic threshold value Th2 exists at a level higher than the level of the output Q, and the output of the inverter 42 surely goes to the H level. Therefore,
The L level is output from the second inverter 43 connected to the output side of the inverter 42, and converges to Q = L.

Thus, in this embodiment, the inverter 42
By increasing the logical threshold value of Th1 from Th1 to Th2, a force to change its output to the H level is given.
Will give a force to change the output of the inverter 43 to L level. Therefore, the response of the output Q of this embodiment to the write control signal C is much faster than the output Q of the conventional example, as can be seen from FIG. As a result, it is possible to prevent a malfunction in the subsequent logic circuit.

Other Embodiments In the embodiment shown in FIG. 4, the logic threshold value of one of the inverters is changed. However, by changing the logic threshold value of all the inverters, the intermediate level The escape from the stable state can be achieved earlier (in a shorter time).

That is, as a method of changing the logic threshold value, at least one of the logic element such as an inverter, which drives the output in the H level direction and the one which drives the output in the L level direction, is driven. It suffices to change the abilities, but if the driving abilities of both are changed in the opposite directions, it becomes possible to escape from the intermediate level stable state in a shorter time.

When a CMOS is used, a transistor may be provided in parallel with the logic element to change the transistor size, or a transistor may be inserted in series to control the voltage input to its gate. Therefore, the ON resistance may be changed, and as a result, the threshold value of the logic element may be changed.

Further, such a cross-coupled state storage circuit can be used as part of a flip-flop having a master-slave structure.

A signal C'which is obtained by delaying the write control signal C.
As a means for generating the above, as shown in FIG. 7, a D-type flip-flop circuit 71 is connected instead of the delay circuit 46 of FIG.
As shown in FIG. 8, the write control signal C changes from H level to L level.
After changing to the level, the second signal (high-speed clock) CK is changed to L level → H level or H level → L level to generate a signal C ′ delayed from the write control signal. May be.

FIG. 9 shows the one-shot generating circuit 91 shown in FIG.
Next, another embodiment of the present invention will be described, which is connected to the preceding stage of the delay circuit 46 and is configured to generate a delayed one-shot pulse signal. Since the operation is basically the same as that of FIG. 4, detailed description will be omitted.

[0026]

As described above, according to the present invention,
Force signal becomes the same as the logic threshold, even if the logic
When the output signal of the element becomes stable at the intermediate level
Also, a signal obtained by delaying the write control signal by a predetermined time is used
Therefore, after a certain time, the logic of the logic element
The threshold can be shifted. As a result,
The output signal of the output
Output the stable state of the logical value of H level or L level.
Can be placed in a state of
Logic malfunction can be prevented. More specifically, by implementing the present invention, the following particular effects can be obtained.

(1) By applying the present invention, it is possible to quickly escape from the intermediate level state by using the state memory circuit that has been stagnation in the intermediate level for a long time, so that it is possible to expect a logic element in the subsequent stage. It is possible to prevent the occurrence of unintended logical operation.

(2) In particular, when a plurality of logic elements are in the subsequent stage, the logic elements do not make different judgments, and malfunctions can be prevented.

(3) Further, for a logic element such as a CMOS having a through current between both power sources at the time of inputting an intermediate level value, by applying the present invention, the time spent in the intermediate level is reduced. Since it can be shortened, power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional state storage circuit.

FIG. 2 is a circuit diagram showing another example of a conventional state storage circuit.

FIG. 3 is a circuit diagram showing still another example of a conventional state storage circuit.

FIG. 4 is a circuit diagram showing a state storage circuit according to an embodiment of the present invention.

5 is a circuit diagram showing a specific example of a switch circuit in FIG.

6 is a waveform diagram showing the input / output characteristics of the state storage circuit of FIG.

FIG. 7 is a circuit diagram showing a state storage circuit according to another embodiment of the present invention.

FIG. 8 is a timing diagram showing output timing of the D-type flip-flop circuit in FIG.

FIG. 9 is a circuit diagram showing a state storage circuit according to another embodiment of the present invention.

[Explanation of symbols]

41,44 switch circuit 42, 43, 45 inverter 46 Delay circuit 51 N-type transistor 52 P-type transistor 71 D-type flip-flop circuit 91 One-shot generation circuit

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Claims (2)

(57) [Claims] 1. A state memory circuit for storing the data in a cross-coupled logic element according to a write control signal for controlling sampling and holding timings for writing data, wherein the write control signal is kept for a predetermined time. means for generating a delayed signal delayed by using the delay signals, shifting the logic threshold value of at least one of the logic device, after a predetermined time of the write control signal of the cross-coupled logic elements < and a state storage circuit. 2. The state storage circuit according to claim 1, wherein the delay signal is generated from a delay element or a D-type flip-flop circuit that outputs a signal obtained by delaying the write control signal for a predetermined time.