JP3521166B2 - Computer system and arbitration method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a hard disk,
A computer system that relates to a connection structure of a computer having a plurality of buses to which peripheral devices such as memories are respectively connected (hereinafter referred to as a computer system), and arbitrates the bus usage right of those peripheral devices to transfer data. And the arbitration method thereof.

[0002]

2. Description of the Related Art In recent years, in computer systems, the number of peripheral devices (hereinafter referred to as devices) connected to one CPU is increasing in order to meet a variety of uses. For this reason,
In such a computer system, a plurality of buses are provided in the computer system, and a plurality of devices are distributed and connected to each bus. Moreover, in such a computer system,
When a usage request is issued to one bus from a plurality of devices, it is necessary to permit one of the plurality of devices to use the bus, and an arbitration device that arbitrates the usage right is provided for each bus. It is provided.

An example of a conventional computer system described in "Open Design No. 7, Details of PCI Bus and Steps to Application", pages 54 to 57, issued by CQ Publisher, is shown in FIG. It will be described with reference to FIG. Figure 12
It is a block diagram which shows the structure of the conventional computer system.
In FIG. 12, a conventional computer system 30 includes a CPU
Two PCI buses 31, 32 indirectly connected to 34
And a host bus 33 directly connected to the CPU 34. PCI (Peripheral Component Interconnec)
t) Buses 31 and 32 have recently been frequently used as local buses for computer systems, and they are ISA (Industrial).
ryStandard Architecture) can transfer data faster than conventional local buses. PCI
The bus 31 has two master devices 31a and 31b.
And one target device 31c are connected, and P
The CI bus 32 has one master device 32a and two master devices 32a.
The two target devices 32b and 32c are connected. The master device means a device such as a hard disk or a graphic card in which a controller unit (not shown) that starts data transfer to a connected bus is added or built in. Further, the target device means a device such as a memory that does not have the above-mentioned controller section, that is, cannot start data transfer by itself to the connected bus. In addition to the CPU 34, a cache memory 33a and a main memory 33b are connected to the host bus 33. The CPU 34 accesses these cache memory 33a and main memory 33b via the host bus 33. A bridge device is provided between the two buses to connect the buses to each other.
Specifically, the PCI-PCI bridge 35 is
PCI bus 3 connected to bus 31 and PCI bus 32
1 and the PCI bus 32 are connected to each other. In addition, the host bridge 36 uses the PCI bus 31 and the host bus 3
3 and the PCI bus 31 and the host bus 33 are connected to each other. It should be noted that these bridge devices can themselves initiate data transfer to the connected bus in the same manner as the master device described above.

Further, in the conventional computer system 30, P
Arbitration devices 37 and 38 for arbitrating the usage rights of the CI buses 31 and 32 independently of each other are provided. Between each arbitration device and the master device and bridge device, a request signal line for transmitting a request signal for use of the connected bus from the master device and the bridge device to the arbitration device (hereinafter abbreviated as REQ # line). And a permission signal line (hereinafter abbreviated as GNT # line) that gives a permission signal for its use from the arbitration device to the master device and the bridge device.
And are provided respectively. Specifically, the arbitration device 37 includes REQ # lines 39a, 39b, 39c, and 39d.
And GNT # lines 40a, 40b, 40c, and 40d are provided between the master devices 31a and 31b, the PCI-PCI bridge 35, and the host bridge 36, respectively. Similarly, the arbitration device 38 has a RE
Q # lines 39e and 39f and GNT # lines 40e and 40f
They are provided between the master device 32a and the PCI-PCI bridge 35, respectively. These REQ # lines 39a to 39f and GNT # lines 40a to 40f are signal lines based on negative logic, and the request signal and the permission signal are activated by, for example, setting the voltage of the signal line to 0V, It is deactivated by setting its voltage to 5V.
In the following description, the activation of the request signal or the permission signal is asserted, and the deactivation of the request signal or the permission signal is negated. In addition, the arbitration devices 37 and 38 have preset priorities for asserting the permission signal. And
When a plurality of request signals are asserted at the same time, each arbitration device 37, 38 asserts a permission signal only to a device with a high priority according to its priority and gives a right to use the bus (details will be described later). . The arbitration of the right to use the host bus 33 is performed by the same arbitration device (not shown) as the arbitration devices 37 and 38.

Next, the operation of the conventional computer system 30 will be described. First, the case where a data transfer request signal completed within one PCI bus is asserted from one master device will be described. For example, when the master device 31a uses the PCI bus 31 to transfer data to the target device 31c, the REQ # line 3
Assert the request signal 9a. The arbitration device 37 asserts the permission signal of the GNT # line 40a when receiving the request signal and giving permission. After that, master device 3
1a uses the PCI bus 31 to transfer data to the target device 31c. Next, a case where a request signal for data transfer using the two PCI buses 31 and 32 is asserted from one master device will be described. For example, if the master device 31a is the target
When transferring data to the device 32b, first,
As described above, the device 31a receives the P from the arbitration device 37.
Obtain the right to use the CI bus 31. And PCI-PCI
When the bridge 35 has a built-in buffer memory, the master device 31a uses the PCI bus 31 to transfer data to the PCI-PCI bridge 35,
Data is temporarily stored in the buffer memory. afterwards,
The PCI-PCI bridge 35 asserts the request signal on the REQ # line 39f. The arbitration device 38 asserts the permission signal of the GNT # line 40f when receiving the request signal and giving permission. After that, PCI-PCI bridge 35
Uses the PCI bus 32 to target device 3
Data transfer to 2b. If the PCI-PCI bridge 35 does not include a buffer memory, the master device 31a and PCI-PCI bridge 3
5 from the arbitration devices 37 and 38 to the PCI buses 31 and 3
Master device 31a after obtaining each usage right of 2
Performs data transfer to the target device 32b via the PCI-PCI bridge 35.

Next, as an arbitration method of the conventional computer system 30, for example, an arbitration method when request signals are asserted from a plurality of devices to the arbitration device 37 will be described below. As described above, the arbitration device 37 has a preset priority level for asserting the permission signal, and when request signals are asserted from a plurality of devices, the permission signal is sent only to the device having the highest priority level. Assert and leave the enable signals for the remaining devices negated. As a result, the device with the highest priority can transfer data using the PCI bus 31, and the right to use the PCI bus 31 is arbitrated. In addition, a system generally called round robin is applied to this priority, and for example, each priority is sequentially circulated for all devices in synchronization with the clock cycle (for example, 20 MHz) of the arbitration device 37.

There is also known an arbitration method in which devices are grouped and the priorities are sequentially circulated so that the priorities are differentiated to perform arbitration. For example, as shown in FIG. 13A, the host bridge 36, PCI-
The priority is set in the order of PCI bridge 35 and group 1, and the master device 31
The priority is set in the order of a and the master device 31b. As a result, as shown in (b) of FIG.
When the request signals are always asserted from all the devices, the host bridge 36 and the PCI-PCI bridge 35 are given priority over the master devices 31a and 31b, and the priority is sequentially cycled. Alternatively, if a particular device is desired to be prioritized, a fixed priority is given to the device, and when the request signal is asserted, this is given the highest priority and the permission signal is asserted.

[0008]

In the above-mentioned conventional computer system and arbitration method thereof, since the arbitration devices provided for each bus arbitrate each usage right of the buses independently of each other, two buses are When data is transferred by using the bus, there is a risk that the bus usage efficiency may decrease. In addition, there is a problem that data transfer cannot be performed in real time. For example, when data is transferred from the master device 31a to the target device 32b using the PCI buses 31 and 32, even if the right to use the PCI bus 31 is given to the master device 31a by the arbitration device 37, the transfer is performed. P if the previous PCI bus 32 is in use
The right to use the PCI bus 32 is not given to the CI-PCI bridge 35. Therefore, the master device 31a needs to wait for data transfer until the PCI bus 32 is released, and the data transfer cannot be performed in real time. Further, while the master device 31a suspends data transfer, the arbitration device 37 negates the permission signal for the device having a lower priority than the master device 31a, so that device transfers data. In addition, the PCI bus 31 was not used, and the usage efficiency was lowered.

The present invention has been made in order to solve the above problems, and provides a computer system capable of real-time data transfer without lowering the bus usage efficiency, and an arbitration method thereof. The purpose is to

[0010]

A computer system or an arbitration method thereof according to the present invention transmits a status signal indicating a status of a second bus from at least a second arbitration device to a first arbitration device, and Each of the N devices connected to the bus transmits the external use signal indicating the bus used for the data transfer to the first arbitration device. With such a configuration, the first arbitration device preferentially performs the data transfer of the device completed on the first bus when the second bus is in use.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION In the computer system of the present invention, N
A first bus connecting N (N is an integer of 1 or more) devices, a second bus connecting M (M is an integer of 1 or more) devices, the first bus and the second bus A computer system comprising: a bridge device that connects to the first bus; a first arbitration device that arbitrates the right to use the first bus; and a second arbitration device that arbitrates the right to use the second bus. A status signal line for transmitting a status signal indicating a status of the second bus from at least the second arbitration device to the first arbitration device, and at least each of the N devices to the first arbitration device. , N external use signal lines for transmitting external use signals indicating buses used by the N devices for data transfer. In the computer system configured as described above, the status signal indicating the status of the second bus is transmitted from the second arbitration device to the first arbitration device.
The arbitration device can monitor not only the state of the first bus but also the state of the second bus. Further, each of the N devices transmits an external use signal indicating a bus used for data transfer to the first arbitration device, so that the first arbitration device is configured such that each of the devices outputs the first and second buses. It is possible to determine which bus to use. As a result, the first arbitration device is:
Data transfer of devices completed by the first bus is preferentially performed.

Further, a computer system of another invention is a priority use request signal line for transmitting a priority use request signal for opening the second bus from at least the first arbitration device to the second arbitration device. It is equipped with. In the computer system configured as described above, since the priority use request signal for opening the second bus is transmitted from the first arbitration device to the second arbitration device, the device connected to the first bus is The data transfer is performed in real time with priority over the device connected to the second bus.

Further, a computer system of another invention is one in which the bridge device and the first and second arbitration devices are integrated into one component. In the computer system configured as described above, the wiring connecting the bridge device and each of the first and second arbitration devices can be omitted.

The arbitration method for the computer system of the present invention is N
A first bus connecting N (N is an integer of 1 or more) devices, a second bus connecting M (M is an integer of 1 or more) devices, the first bus and the second bus An arbitration method for a computer system, comprising: a bridge device for connecting to each other; a first arbitration device that arbitrates the right to use the first bus; And transmitting a status signal indicating the status of the second bus from at least the second arbitration device to the first arbitration device, and at least the N arbitration devices from the first arbitration device. A step of transmitting an external use signal indicating a bus used by the N devices for data transfer. According to the arbitration method of the computer system as described above, the first arbitration device preferentially performs the data transfer of the device completed on the first bus when the second bus is in use.

Further, the arbitration method for the computer system according to another invention includes a step of transmitting a priority use request signal for opening the second bus from at least the first arbitration device to the second arbitration device. It is provided. By the arbitration method of the computer system as described above, the device connected to the first bus is prioritized over the device connected to the second bus and the data transfer is performed in real time.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a computer system of the present invention and an arbitration method thereof will be described below with reference to the drawings.

<< Embodiment 1 >> FIG. 1 is a block diagram showing the configuration of a computer system which is Embodiment 1 of the present invention. FIG. 2 is a block diagram showing a specific configuration of the first and second arbitration devices shown in FIG. In FIG. 1, a computer system 10 includes first and second buses 1a and 1b, first and second buses.
A bridge device 2 that connects the buses 1a and 1b to each other, and first and second arbitration devices 3a and 3b that arbitrate the usage rights of the first and second buses 1a and 1b, respectively.
The first and second buses 1a and 1b are PCI (Peripheral C
A local bus such as an omponent interconnect) bus, for example, the first bus 1a is connected to a CPU (not shown) via a host bus (not shown). Two master devices 4a and 4b are connected to the first bus 1a, and two master devices 4a and 4b are connected to the second bus 1b.
c and 4d are connected. These master devices 4a to 4d are devices such as a hard disk and a graphic card provided with a controller unit (not shown) that starts data transfer to each of the connected buses 1a and 1b. The target devices described in the [Prior Art] column are connected to the first and second buses 1a and 1b. These are arbitration targets of the first and second arbitration devices 3a and 3b. Therefore, the description thereof will be omitted. Like the master devices 4a to 4d, the bridge device 2 is capable of starting data transfer to each of the connected buses 1a and 1b by itself, and the first and second arbitration devices 3a and 3b.
It is a device that is a target of arbitration for both of b.

The first arbitration device 3a includes a first bus 1a.
Request signal lines (hereinafter, abbreviated as REQ lines) 5a, 5b, and 5c for transmitting the request signal for the use of the master device 4a, 4b and the bridge device 2 to the arbitration device 3a, and the permission signal for the use thereof. From the arbitration device 3a to the master devices 4a and 4b and the bridge device 2
A permission signal line (hereinafter abbreviated as GNT line) 6a,
6b and 6c are provided, respectively. Similarly, to the second arbitration device 3b, a REQ line 5 that transmits a request signal for use of the second bus 1b from the master devices 4c and 4d and the bridge device 2 to the arbitration device 3b.
There are provided dNTs 5d, 5e, and 5f, and GNT lines 6d, 6e, and 6f that give permission signals for their use from the arbitration device 3b to the master devices 4c, 4d and the bridge device 2, respectively. In addition, the first arbitration device 3
External use signal lines (hereinafter abbreviated as EXT lines) 7a and 7b are provided between a and the master devices 4a and 4b, respectively. These EXT lines 7a and 7b are signal lines that convey the use of the second bus 1b, which is an external bus, from the master devices 4a and 4b to the first arbitration device 3a, and the master devices 4a and 4b are bridges. When the data transfer is performed using the second bus 1b via the device 2, the external use signals of the signal lines 7a and 7b are activated respectively. Also, these EXT lines 7
a and 7b are the master devices 4a and 4b,
For example, it is connected to the external use signal generation circuit 11 (FIG. 4) provided in the controller section.

Here, the external use signal generation circuit 11 will be specifically described with reference to FIGS. 3 and 4. FIG. 3 is an explanatory diagram showing a memory map in the computer system which is Embodiment 1 of the present invention, and FIG. 4 is a circuit diagram showing an external use signal generation circuit built in a master device of the computer system. In the computer system 10, as shown in FIG. 3, a predetermined address sandwiched between the base address 12a and the limit address 12b is assigned to each device such as the master devices 4a and 4b connected to the first bus 1a. Other addresses are assigned to each device such as the master devices 4c and 4d connected to the second bus 1b. As shown in FIG. 4, the external use signal generation circuit 11 includes a base address register 13a storing the value of the base address 12a and a limit address 1
Limit address register 13b that stores the value of 2b,
A first comparator 14a that compares the value of the base address 12a with the value of the transfer destination address of the data transfer, a second comparator 14b that compares the value of the limit address 12b with the value of the transfer destination address, And the first and second comparators 14
It is composed of an OR gate 15 which takes the logical sum of the comparison results from a and 14b. When the value of the transfer destination address is smaller than the value of the base address 12a, the first comparator 14a activates the LT signal of the signal line 16a and transmits it to the OR gate 15. Further, the second comparator 14b activates the GT signal of the signal line 16b and transmits it to the OR gate 15 when the value of the transfer destination address is larger than the value of the limit address 12b. The OR gate 15 outputs the EX signal when either the LT signal or the GT signal is activated.
The first arbitration device 3 is activated by activating the external use signal of the T line 7a.
tell a. With this configuration, the first arbitration device 3a (FIG. 1) operates as a master device 4a, 4b.
Whether or not (FIG. 1) uses the external second bus 1b (FIG. 1) for data transfer can be determined by an external use signal. For example, when the master device 4a transfers data to the master device 4c (FIG. 1) connected to the second bus 1b, either the LT signal or the GT signal is activated and the OR gate 15 is externally connected. The use signal is activated and transmitted to the first arbitration device 3a. If, for example, the master device 4a transfers data to the master device 4b connected to the same first bus 1b, the LT
The signal and GT signal are not activated, and the OR gate 15
The external use signal of the EXT line 7a is transmitted to the first arbitration device 3a without being activated.

Returning to FIG. 1, the first arbitration device 3a and the second arbitration device 3a
Between the second arbitration device 3b and the second arbitration device 3b, there is provided a status signal line (hereinafter, abbreviated as SIT line) 8 for transmitting the status of the second bus 1b from the second arbitration device 3b to the first arbitration device 3a. There is. The second arbitration device 3b activates the status signal and transmits the status signal to the first arbitration device 3a through the SIT line 8 when the second bus 1b is in use, for example.

As shown in FIG. 2, the first and second arbitration devices 3a and 3b are provided with priority determining means 9a and 9b, respectively. The priority determination means 9a has the REQ
Lines 5a-5c, GNT lines 6a-6c, EXT lines 7a, 7b and
SIT line 8 is connected. Similarly, the priority determination means 9
b, REQ lines 5d to 5f, GNT lines 6d to 6f, and SIT
Line 8 is connected. The signal lines such as the REQ lines 5a to 5f are signal lines based on, for example, positive logic, and a signal such as a request signal is activated by setting the voltage to 5V, and the signal is set by setting the voltage to 0V. Is deactivated. Further, in the following description, it is abbreviated as asserting activation of the above-mentioned signals and negating deactivation of the signals, respectively. Further, the priorities for asserting the permission signals are set in advance in the priority determination means 9a and 9b, respectively. For example, the priority determination means 9
In a, the priority is initialized in the order of the master device 4a, the master device 4b, and the bridge device 2. This priority applies the round robin method,
It cycles in order according to a predetermined time, for example, a clock cycle (for example, 20 MHz) of the first arbitration device 3a. That is, as shown in FIG. 5, the priority is in the order of the master device 4a, the master device 4b, and the bridge device 2 at the time of state 1, and the master device 4b and the bridge device at the time of state 2. The device 2 and the master device 4a are in this order. In addition, state 3
At this time, the priority is bridge device 2, master
The order is the device 4a and the master device 4b.

Next, the operation of the computer system 10 and the arbitration method will be described. First, a case where a data transfer request signal completed within one bus is asserted from one device will be described. For example, master
When the device 4a uses the first bus 1a to transfer data to the master device 4b, the master device 4
a asserts the request signal on the REQ line 5a. The first arbitration device 3a asserts the permission signal of the GNT line 6a when receiving the request signal and giving permission. After that, the master device 4a transfers data to the master device 4b using the first bus 1a.

Next, a case where a plurality of request signals are asserted from a plurality of devices will be described with reference to FIG. In the following description, the priority in the first arbitration device 3a is the order at the time of state 1 shown in FIG.
That is, the master device 4a and the master device 4
b and the bridge device 2 are set in this order. FIG. 6 is a flowchart showing an arbitration method of the first arbitration device shown in FIG. As shown in FIG. 6, when a plurality of devices respectively assert their request signals to the first arbitration device 3a (step 101), the first arbitration device 3a receives the first signal.
The arbitration device 3a checks whether the master device 4a having the highest priority among these devices asserts the external use signal (step 10).
2). When the master device 4a has not asserted the external use signal, the first arbitration device 3a asserts the permission signal for the master device 4a (step 103). As a result, the master device 4a
Starts data transfer using the first bus 1a to a device connected to the bus 1a, for example, the master device 4b. If the master device 4a is asserting the external use signal, the first arbitration device 3a examines the status signal from the second arbitration device 3b to obtain the second signal.
The state of the bus 1b is checked (step 104). When the second bus 1b is not used and is in an open state, the first arbitration device 3a asserts a permission signal to the master device 4a (step 105). Thereby, the master device 4a starts data transfer to the bridge device 2 using the first bus 1a. Then, after the bridge device 2 obtains the right to use the second bus 1b from the second arbitration device 3b, the bridge device 2 transfers the data from the master device 4a to, for example, the master device 4c. To do. When the second bus 1b is in use, the first arbitration device 3a keeps the permission signal for the master device 4a negated, and gives priority to other devices which have asserted the request signal. The inspection is performed in order, and the permission signal is asserted for the highest priority device that has not asserted the external use signal (step 106). For example, master device 4b
However, when the request signal is asserted and the external use signal is not asserted, the first arbitration device 3a asserts the permission signal to the master device 4b. As a result, the master device 4b, which has a lower priority than the master device 4a, uses the first bus 1a,
Data transfer to the master device 4a or the like connected to the bus 1a.

As described above, according to the computer system 10 and the arbitration method thereof of this embodiment, the first arbitration device 3a is used.
Can monitor not only the status of the first bus 1a but also the status of the second bus 1b by the status signal. Also,
The first arbitration device 3a can check whether or not the device asserting the request signal by the external use signal performs the data transfer using the second bus 1b. As a result, the first arbitration device 3a uses the second bus 1b.
When the device is in use, the data transfer of the device using the second bus 1b can be suspended, and the data transfer of the device completed by the first bus 1a can be preferentially performed. Therefore, the usage efficiency of the first bus 1a does not decrease,
Data transfer completed on the bus 1a can be performed in real time.

The first and second buses 1a and 1b are asymmetrical, that is, the EXT lines 7a and 7b are provided only on the side of the first bus 1a.
In addition to the above configuration in which the second arbitration device 3b transmits the status signal to the first arbitration device 3a, an EXT line is provided on the second bus 1b side and the status signal is transmitted to the first arbitration device. The configuration may be such that 3a is transmitted to the second arbitration device 3b. In addition, after the master device 4a determines that the external use signal is asserted, the state of the second bus 1b is checked, but the state of the second bus 1b is checked and the second bus 1b is checked. When 1b is in use, it may be configured to check whether or not the master device 4a asserts the external use signal.

<Second Embodiment> FIG. 7 is a block diagram showing the configuration of a computer system according to a second embodiment of the present invention. FIG. 8 is a block diagram showing a specific configuration of the first and second arbitration devices shown in FIG. It should be noted that, in the configuration of the computer system 20, that of the first embodiment except that a priority use request signal line (hereinafter, abbreviated as INT line) 21 is provided between the first and second arbitration devices 3c and 3d. Since they are exactly the same as the above, their explanations are omitted. The difference from the first embodiment is that a priority use request signal is transmitted from the first arbitration device 3c to the second arbitration device 3d through the INT line 21 so that a device connected to the first bus 1a, for example, a master device. The point is that it is fixed so that it always has the highest priority. That is,
As shown in FIG. 7, an INT line 21 is provided together with the SIT line 8 between the first arbitration device 3c and the second arbitration device 3d. By this INT line 21, the first arbitration device 3c
When the preferential use request signal is transmitted from the second arbitration device 3d to the second arbitration device 3d, the second arbitration device 3d opens the second bus 1b. As a result, the master device 4a can transfer data to, for example, the master device 4c using the second bus 1b.

Further, as shown in FIG. 8, the first arbitration device 3c has priority determination means 9c for determining the priority of the device with respect to the usage right of the first bus 1a, and data for the second bus 1b. It is composed of an external priority mode register 22 for setting whether to prioritize transfer, and a signal generating means 23 for outputting a priority use request signal to the INT line 21. The priority determining means 9c is similar to the priority determining means 9a shown in the first embodiment, the REQ lines 5a to 5c, the GNT lines 6a to 6c, and the EX.
The T lines 7a and 7b and the SIT line 8 are connected. Further, the priority determination means 9c outputs a priority permission signal to the signal generation means 23 through the signal line 24 when the request signal and the external use signal are asserted from the master device 4a. When giving priority to data transfer to the second bus 1b, the external priority mode register 22 outputs a priority mode signal to the signal generating means 23 through the signal line 25. Signal generating means 23
When the priority permission signal and priority mode signal are input,
The second arbitration device 3 sends the priority use request signal to the INT line 21.
It outputs to the priority determination means 9d provided in d. Also,
The second arbitration device 3d is provided with priority determination means 9d for determining the priority of the device with respect to the right to use the second bus 1b. The priority determining means 9d is similar to the priority determining means 9b shown in the first embodiment, and the REQ lines 5d to 5d.
f, GNT lines 6d to 6f, and SIT line 8 are connected.
When the priority use request signal is transmitted through the INT line 21, the priority determination means 9d negates the permission signals of the GNT lines 6d and 6e and asserts the permission signal of the GNT line 6f.

As shown in FIG. 9, the priority of the priority determining means 9c is such that the master device 4a is fixed and always given the highest priority, and the master device 4b and the bridge device 2 are sequentially cycled. . That is, the priority is in the order of the master device 4a, the master device 4b, and the bridge device 2 at the time of state 1, and the priority is the master device 4a, the bridge device 2, and the master device at the time of state 2. The order is 4b. As shown in FIG. 10, the master device 4a has the highest priority as the priority of the master device 4 as shown in FIG.
It cycles through c, 4d, and bridge device 2 in sequence. In FIG. 10, the (bridge device 2) and the bridge device 2 below the master device 4a
(Master device 4b) below is
This is because the priority determination unit 9d indicates a more accurate priority. That is, in any case where the master devices 4a and 4b perform data transfer using the second bus 1b, the request signal is asserted from the bridge device 2 to the priority determination means 9d. is there.

Next, the arbitration method of the computer system 20 of this embodiment, that is, the case where a plurality of request signals are asserted from a plurality of devices to the first arbitration device 3d, will be described with reference to FIG.
This will be described with reference to FIG. In the following description, the first
It is assumed that the priority of the arbitration device 3c is set in the order at the time of the state 1 shown in FIG. 10, that is, the order of the master device 4a, the master device 4b, and the bridge device 2. Further, the external priority mode register 22 is assumed to give priority to data transfer to the second bus 1b. FIG. 11 is a flowchart showing the arbitration method of the first arbitration device shown in FIG. As shown in FIG. 11, a plurality of devices assert their request signals in the first arbitration device 3a (step 110).
Then, the first arbitration device 3a checks whether or not the master device 4a having the highest priority among those devices asserts the request signal (step 11).
1). If the master device 4a has not asserted the request signal, the first arbitration device 3a negates the permission signal for the master device 4a and gives priority to the other devices that have asserted the request signal as described above. And the permission signal is asserted for the highest priority device that has not asserted the external use signal (step 112). For example, the master device 4b
When the request signal is asserted and the external use signal is not asserted, the first arbitration device 3a asserts the permission signal for the master device 4b. As a result, a master device with a lower priority than the master device 4a
The device 4b uses the first bus 1a to start data transfer to the master device 4a or the like connected to the first bus 1a. Next, the first arbitration device 3a checks whether or not the master device 4a asserts the external use request signal (step 113). When the master device 4a has not asserted the external use signal, the first arbitration device 3a asserts a permission signal to the master device 4a (step 11).
4). As a result, the master device 4a is
The bus 1a is used to start data transfer to a device connected to the bus 1a, for example, the master device 4b. If the master device 4a is asserting the external use signal, the first arbitration device 3a examines the status signal from the second arbitration device 3b to determine the second bus 1
The state of b is checked (step 115). Second bus 1b
If the open state is not used, the first arbitration device 3a asserts a permission signal to the master device 4a (step 116). Thereby, the master device 4a starts data transfer to the bridge device 2 using the first bus 1a. Then, after the bridge device 2 obtains the permission signal for using the second bus 1b from the second arbitration device 3b, the bridge device 2 receives the data from the master device 4a, for example, the master device 4c. Transfer to. When the second bus 1b is in use, the first arbitration device 3a operates as the second arbitration device 3b.
Assert a preferential use request signal to (step 1
17). As a result, the second arbitration device 3 negates the permission signals of the GNT lines 6d and 6e, and the second bus 1b
Is opened. Further, at this time, the permission signal of the GNT line 6f is asserted, and the bridge device 2 receives the second signal.
The use of the bus 1b is granted. Then, the first arbitration device 3a asserts a permission signal to the master device 4a (step 118). As a result, the master device 4a has the first and second buses 1a,
Data transfer to the master device 4c is started using 1b.

As described above, according to the computer system 20 of this embodiment and the arbitration method thereof, the first arbitration device 3a is used.
From the first bus 1 such as the master device 4a by outputting the preferential use request signal from the second arbitration device 3b to the second arbitration device 3b.
The device connected to a can be prioritized over the device connected to the second bus 1b to perform the data transfer in real time.

The priority use request signal is sent to the first arbitration device 3
In addition to the above configuration in which a is transmitted to the second arbitration device 3b, the priority use request signal is transmitted from the second arbitration device 3b to the first
It may be configured to notify the arbitration device 3a.

In addition, in the computer systems 10 and 20 shown in the first and second embodiments, the first arbitration device 3
Although a, 3c, the second arbitration device 3b, 3d and the bridge device 2 are shown as separate components,
These may be integrated into one component, for example, an LSI. With this configuration, the number of external wirings can be reduced and the cost of the computer system can be reduced.

[0033]

According to the computer system of the present invention, the second
A status signal indicating the status of the bus from the second arbitration device to the first
The first arbitration device can monitor not only the state of the first bus but also the state of the second bus. Further, since each of the N devices connected to the first bus transmits an external use signal indicating the bus used for data transfer to the first arbitration device, the first arbitration device causes each of the devices to operate as the first device. And which of the second buses to use can be determined. As a result, the first arbitration device suspends the data transfer of the device using the second bus when the second bus is in use, and
It is possible to preferentially perform data transfer of a device completed by the bus. Therefore, the data transfer completed by the first bus 1a can be performed in real time without lowering the use efficiency of the first bus 1a.

Further, according to the computer system of another invention, since the priority use request signal for opening the second bus is transmitted from the first arbitration device to the second arbitration device, it is connected to the first bus. The data transfer can be performed in real time by giving priority to the connected device over the device connected to the second bus.

Further, according to the computer system of another invention, the wiring for connecting the bridge device and each of the first and second arbitration devices can be omitted.

Further, according to the arbitration method for the computer system of the present invention, the step of transmitting a status signal indicating the status of the second bus from at least the second arbitration apparatus to the first arbitration apparatus, and at least N number of There is a step of transmitting from each device to the first arbitration device an external use signal indicating a bus used by N devices for data transfer. For this reason, the first arbitration device, when the second bus is in use,
The data transfer of the device completed by the first bus can be preferentially performed.

According to another aspect of the computer system arbitration method, at least the step of transmitting a preferential use request signal for opening the second bus from the first arbitration device to the second arbitration device is provided. Therefore, the device connected to the first bus can be prioritized over the device connected to the second bus and the data transfer can be performed in real time.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a computer system that is Embodiment 1 of the present invention.

FIG. 2 is a block diagram showing a specific configuration of the first and second arbitration devices shown in FIG.

FIG. 3 is an explanatory diagram showing a memory map in the computer system of the present invention.

FIG. 4 is a circuit diagram showing an external use signal generation circuit in the computer system of the present invention.

5 is an explanatory diagram showing a cycle of priorities of the first arbitration device shown in FIG. 1. FIG.

FIG. 6 is a flowchart showing an arbitration method for a computer system that is Embodiment 1 of the present invention.

FIG. 7 is a block diagram showing the configuration of a computer system that is Embodiment 2 of the present invention.

8 is a block diagram showing a specific configuration of the first and second arbitration devices shown in FIG.

9 is an explanatory diagram showing a cycle of priorities of the first arbitration device shown in FIG. 7. FIG.

10 is an explanatory diagram showing a cycle of priorities of the second arbitration device shown in FIG. 7. FIG.

FIG. 11 is a flowchart showing an arbitration method for a computer system that is Embodiment 2 of the present invention.

FIG. 12 is a block diagram showing the configuration of a conventional computer system.

FIG. 13 is an explanatory diagram showing a cycle of priorities of the conventional arbitration device shown in FIG.

[Explanation of symbols]

1a, 1b bus 2 bridge device 3a, 3b, 3c, 3d Arbitration device 4a, 4b, 4c, 4d Master device 7a, 7b External use signal line 8 status signal lines 21 Priority use request signal line

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Claims (5)

(57) [Claims] 1. A first bus connecting N devices (N is an integer of 1 or more), a second bus connecting M devices (M is an integer of 1 or more), The first bus A bridge device that connects the second bus to the second bus, a first arbitration device that arbitrates the right to use the first bus, and a second arbitration device that arbitrates the right to use the second bus. A computer system having: a status signal line for transmitting a status signal indicating a status of the second bus from at least the second arbitration device to the first arbitration device; A computer system comprising: a first arbitration device; N external use signal lines for transmitting external use signals indicating buses used by the N devices for data transfer. 2. A preferential use request signal line for transmitting a preferential use request signal for opening the second bus from at least the first arbitration device to the second arbitration device. The computer system according to claim 1. 3. The computer system according to claim 1, wherein the bridge device and the first and second arbitration devices are integrally configured in one component. 4. A first bus connecting N devices (N is an integer of 1 or more), a second bus connecting M devices (M is an integer of 1 or more), and the first bus. A bridge device that connects the second bus to the second bus, a first arbitration device that arbitrates the right to use the first bus, and a second arbitration device that arbitrates the right to use the second bus. An arbitration method for a computer system comprising: transmitting a status signal indicating a status of the second bus from at least the second arbitration apparatus to the first arbitration apparatus; and at least from each of the N devices. An arbitration method for a computer system, comprising: transmitting an external use signal indicating a bus used by the N devices to transfer data to the first arbitration device. 5. The method according to claim 4, further comprising the step of transmitting a priority use request signal for opening the second bus from at least the first arbitration device to the second arbitration device. Arbitration method of the computer system described in.