JP3518952B2 - Function duplication device and function duplication method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function duplication device for duplicating a function of a duplication target device which outputs output data corresponding to given input data,
In particular, it relates to the duplication technique.

[0002]

2. Description of the Related Art PLD (Programmable Programmable) is an LSI that allows a user to write a logical function at hand.
capable Logic Device) is known. PLD has A
Small PLA with ND plane and OR plane as basic structure
(Programmable Logic Array) to large-scale FPGA
There are many types, including (Field Programmable Gate Array).

In all of these, a large number of logic circuits and the like are arranged in advance on a chip, and the logic circuits and the like are connected to each other through programmable switches. Therefore, the user can realize a desired logical function by connecting and disconnecting these many switches according to a predetermined pattern.

As described above, by using the PLD,
An LSI having a desired logical function can be realized with a short delivery time.

By the way, when an LSI having a certain function is developed and an attempt is made to duplicate an LSI having the same function, such as when the specification is lost, it is necessary to perform circuit analysis or the like on the LSI to be duplicated. . However, since such circuit analysis requires a great deal of time and the ability to analyze, it cannot be easily performed by anyone.

It is an object of the present invention to provide a function duplication device for duplicating the function of a duplication target device which outputs output data corresponding to given input data.

[0007]

According to a first aspect of the present invention, there is provided a function duplication device for duplicating a function of a duplication target device which outputs output data corresponding to predetermined input data. Input giving means for giving predetermined input data to the rewriting target device and the duplication target device, judgment information storage means for storing a plurality of logical information as candidates for obtaining output data corresponding to specific input data, the judgment information storage Among the plurality of candidates stored in the means, a candidate in which the output data given from the rewriting target device and the output data given from the duplication target device match all the given input data is specified, and this candidate is identified. Rewriting means for giving a rewriting command to the rewriting target device so as to realize the logical information of 1. When a candidate in which the output data given from the device to be rewritten and the output data given from the device to be copied match is found, a rewriting command is issued to the device to be rewritten so that the logical information of this candidate can be realized. In addition to giving, the given input data is stored, and 2) when another input data is given, whether there is a candidate that satisfies all of this input data and the stored input data. If there is such a candidate, a rewriting command is given to the rewriting target device so that the logical information of this candidate can be realized.

A function duplicating apparatus according to a second aspect is an apparatus for duplicating a function of a duplication target device which outputs output data corresponding to given input data, and rewrites the given input data. Input device for giving the target device and the device to be duplicated, judgment information storage device for storing a plurality of logical information for obtaining output data corresponding to specific input data as candidates, and a plurality of information stored in the judgment information storage device. Of the candidates, the output information given from the rewriting target device and the output data given from the duplication target device for the given input data are identified, and the logical information of this candidate can be realized. As described above, rewriting means for giving a rewriting command to the rewriting target device, for all input data,
When there is no candidate in which the output data given from the rewriting target device and the output data given from the duplication target device match, there are a plurality of areas in the rewriting target device for data processing according to the given input data. It is characterized by giving a rewriting instruction to be provided.

According to a third aspect of the present invention, there is provided a function duplicating apparatus comprising a logical configuration reading means for reading the logical configuration of the rewriting target device and outputting the logical configuration.

According to a fourth aspect of the present invention, there is provided a function duplicating method for duplicating a function of a duplication target device which outputs output data corresponding to predetermined input data when specific input data is given. A plurality of pieces of logical information for obtaining corresponding output data are stored as candidates, the predetermined input data is given to the rewriting target device and the duplication target device, and all of the given input data among the plurality of candidates are given. With respect to the above, the rewrite target device is rewritten so that a candidate in which the output data given from the rewriting target device and the output data given from the duplicated target device match is identified and the logical information of the identified candidate can be realized. A function duplication method for giving an instruction, comprising: 1) output data given from the rewriting target device and given from the duplication target device. When a candidate whose output data matches is found, a rewriting command is given to the rewriting target device so that the logical information of this candidate can be realized, and the given input data is stored. ) If another input data is given, it is judged whether or not there is a candidate that satisfies all of this input data and the stored input data, and if there is such a candidate, the logic of this candidate is determined. A rewriting command is given to the rewriting target device so that information can be realized.

According to a fifth aspect of the present invention, there is provided a function duplicating method for duplicating a function of a duplication target device which outputs output data corresponding to predetermined input data when the predetermined input data is rewritten. A plurality of pieces of logical information, which are given to the target apparatus and the apparatus to be duplicated and are used to obtain corresponding output data for specific input data, are stored as candidates, and the given input data among the plurality of stored candidates is stored. With respect to the rewriting target device, a rewriting command is specified to the rewriting target device so as to identify a candidate in which the output data given from the rewriting target device and the output data given from the copied target device match, and to realize the logical information of the candidate. For all input data, output data given from the device to be rewritten and given from the device to be duplicated If the candidate force data matches does not exist, to provide a plurality provision rewrite instruction area for data processing in response to a given input data to the rewriting target device, and wherein.

The relationship between the terminology of the claims used to express the technical idea devised to solve the problem and the embodiment will be described.

"Input giving means": means for giving input data to the rewriting target device and the duplication target device, and corresponds to the processing of the CPU 23 in step ST9 and step ST33 in FIG. 4 in the embodiment. However, the CPU 23 does not judge whether or not the input data is given, but when the input data is given, it may be given to the PLDs 40 and 41 without making any judgment.

"Judgment information storage means" corresponds to the hard disk 26 which stores the candidates shown in FIG.

"Rewriting means" corresponds to the processing of the CPU 23 in steps ST49 and ST53 of FIG. 5, or the processing of the CPU 23 in steps ST13, ST15 and ST17 of FIG.

[0016]

In the function duplicating apparatus or the method thereof according to claims 1 and 4, a plurality of logical information for obtaining output data corresponding to specific input data is stored as a candidate, and the predetermined information is stored. Input data to the rewriting target device and the duplication target device, and output data given from the rewriting target device and output given from the duplication target device for all given input data among the plurality of candidates. A rewrite command is given to the rewriting target device so as to identify a candidate whose data matches and to realize the logical information of the candidate. Therefore, it is possible to obtain, from the rewriting target device, output data that matches the output data given from the duplication target device for all the given input data. With this, without analyzing the function of the duplication target device,
A rewriting target device having the same function can be obtained.

Further, when a candidate in which the output data given from the device to be rewritten and the output data given from the device to be duplicated match is found, the rewriting is performed so that the logical information of the candidate can be realized. When a rewrite command is given to the target device, the given input data is stored. As a result, the detection work can be ended at the stage when a candidate in which the two output data match is found. When another input data is given, it is determined whether or not there is a candidate that satisfies all of this input data and the stored input data. A rewriting command is given to the rewriting target device so that the logical information can be realized. Thus, by sequentially rewriting the rewriting target device, it is possible to provide a rewriting target device capable of processing all input data at a certain stage as quickly as possible and with a small capacity.

In the function duplicating apparatus or the method thereof according to claims 2 and 5, a plurality of pieces of logical information for obtaining corresponding output data for specific input data are stored as candidates, and the predetermined input data is stored. Given to the device to be rewritten and the device to be copied, among the plurality of candidates,
With respect to all the given input data, a candidate in which the output data given from the device to be rewritten and the output data given from the device to be duplicated match is specified, and the rewriting is performed so that the logical information of the candidate can be realized. Give a rewrite command to the target device. Therefore, it is possible to obtain, from the rewriting target device, output data that matches the output data given from the duplication target device for all the given input data. As a result, a rewrite target device having the same function can be obtained without analyzing the function of the copy target device.

If there is no candidate for which the output data given from the rewriting target device and the output data given from the duplicating target device match for all the input data, depending on the given input data. A rewriting command is provided to provide a plurality of areas for data processing in the rewriting target device. Therefore, it is not necessary to increase the number of candidates to be stored. Since the number of matching judgments is reduced due to the small number of such candidates, the rewrite command can be output in a short time.

In the function duplicating apparatus of the third aspect, the logical configuration reading means reads the logical configuration of the device to be rewritten and outputs it. Therefore, for all the input data, without making the matching judgment,
A rewrite target device having the same function can be obtained easily and in a short time.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to the drawings.

1. Description of Functional Block Diagram The function duplication device 1 shown in FIG. 1 is a device for duplicating the function of a duplication target device which outputs output data corresponding to given input data, and which is an input providing unit. 3, a judgment information storage unit 5, a rewriting unit 7, and a logical configuration reading unit 11.

The input giving means 3 gives predetermined input data to the rewriting target device 19 and the duplication target device 17.

The judgment information storage means 5 stores a plurality of logical information as candidates for obtaining output data corresponding to specific input data. The rewriting unit 7 matches the output data given from the rewriting target device 19 with the output data given from the duplication target device 17 for all the given input data among the plurality of candidates stored in the judgment information storage unit 5. Specify the candidate to do. Then, a rewriting command is given to the rewriting target device 19 so that the logical information of the identified candidate can be realized.

The logical configuration reading means 11 reads the logical configuration of the rewriting target device 19 and outputs it.

Therefore, it is possible to obtain from the rewriting target device 19 output data that matches the output data given from the duplication target device 17 for all the given input data. As a result, the rewriting target device 1 having the same function without analyzing the function of the replication target device 17.
9 can be obtained. Further, a rewriting target device having the same function can be obtained easily and in a short time without performing the matching judgment for all the input data given.

The rewriting means 7 further performs the following optimization processing. When a candidate in which the output data given from the rewriting target device 19 and the output data given from the duplication target device 17 match is found, a rewriting instruction is given to the rewriting target device 19 so that the logical information of this candidate can be realized. Is given, and the given input data is stored. Then, if another input data is given, it is judged whether or not there is a candidate that satisfies all of this input data and the stored input data. A rewriting command is given to the rewriting target device 19 so that the logical information can be realized. As described above, by performing the optimization process of sequentially rewriting the rewriting target device, it is possible to provide a rewriting target device capable of processing all input data at a certain stage as quickly as possible and with a small capacity. it can. Further, it is possible to process more input data without complicating the configuration of the rewriting target device 19.

The rewriting means 7 can also perform the following processing. For all the input data, if there is no candidate in which the output data given from the rewriting target device and the output data given from the duplication target device do not exist, a data processing area is set according to the given input data. A plurality of rewriting commands to be provided to the rewriting target device 19 are given. Therefore, it is not necessary to increase the number of candidates to be stored. Since the number of matching judgments is reduced due to the small number of such candidates, the rewrite command can be output in a short time.

2. Hardware Configuration FIG. 2 shows an example of a hardware configuration in which the function duplication device 1 shown in FIG. 1 is realized by using a CPU.

The function duplicating apparatus 1 includes a CPU 23 and a memory 2.
7, a hard disk 26, a floppy disk drive (FDD) 33, a keyboard 28, an I / O 31, and a bus line 29.

The CPU 23 controls each unit via the bus line 29 according to the control program stored in the hard disk 26.

The control program is read from the flexible disk storing the program via the FDD 33 and installed in the hard disk 26. In addition to the flexible disk, a CD
-The hard disk may be installed from a computer-readable storage medium in which programs such as a ROM and an IC card are substantially integrated. Furthermore, you may make it download using a communication line.

In the present embodiment, the program is installed from the flexible disk to the hard disk 26 so that the program stored in the flexible disk is indirectly executed by the computer. However, the program stored in the flexible disk is not limited to this.
It may be directly executed from. Note that programs that can be executed by a computer include programs that can be directly executed simply by installing them as they are, and programs that need to be converted to another form (for example,
It also includes those that can be executed in combination with other module parts, such as decompressing data compressed data).

The hard disk 26 stores a plurality of candidate algorithms. An example of this candidate algorithm is shown in FIG.
Shown in. Each candidate algorithm is given a number. For example, the candidate with the number 1 is an algorithm of “outputting the input value as it is”.

The memory 27 temporarily stores the calculation results and the like. The I / O 31 includes a PLD 4 which is a circuit to be rewritten.
1. It is connected to the PLD 40 which is the circuit to be replicated and inputs / outputs data. The keyboard 28 is a command input means for inputting commands and the like.

3. Flowchart Next, the programs stored in the hard disk 26 will be described with reference to FIGS. 4 and 5. Note that the following description will be made assuming that the PLD 40 that is the duplication target device outputs the corresponding 3-bit output data when input data having a bit length of 3 bits as shown in FIG. 6 is provided. In addition, the PLD 41 that is the device to be rewritten
With regard to, the description will be made assuming that no logic circuit is configured and, when input data is given, this is output as it is.

First, the CPU 23 determines whether or not the F flag is on (step ST3 in FIG. 4). The F flag is a flag for determining whether or not a rewrite command for creating a switching circuit is given to the PLD 41, and details will be described later.

In the initial state, the F flag is off. Therefore, FIG. 4 step ST3 to FIG. 5 step ST3
In step 1, it is determined whether or not the input data is given (step ST31 in FIG. 5).

PLD 40 and PLD 41 each output output data in accordance with the input data provided.
Here, as shown in FIG. 6A, the reference output data “111” is given from the PLD 40 to the input data “000”. From the PLD 41, the learning target output data “000” is given to the input data “000”.

In this case, the CPU 23 uses two PLDs 4
It is determined that the output data from 0 and 41 do not match, and the process target algorithm number i is initialized (step S in FIG. 5).
T43). Then, the algorithm number i to be processed is incremented (step ST45), and the i-th algorithm is read from the hard disk 26. In this case, since i = 1, the first algorithm “output the input value as it is” is read.

Next, using the read algorithm, the CPU 23 determines whether the same output data as the reference output data can be obtained from the input data stored in the memory 27 (step ST49). In this case, the memory 27 stores the input data “00” shown in FIG. 16A.
“0” is stored. The algorithm of algorithm number 1 does not convert this input data “000” into the reference output data “111”. Therefore, it is determined whether or not all the algorithms have been considered (step ST51). In this case, since there are remaining algorithms that have not been examined, the process returns to step ST45 and the process target algorithm number i is incremented.

Next, the CPU 23 reads out the second algorithm (step ST47). In this case, using the second algorithm "invert input value and output", the input data "000" shown in FIG. 6A can be obtained as output data that matches the reference output data "111". Therefore, in step ST49, it is determined that the input data stored in the memory 27 is satisfied, and the process proceeds to step ST53. Then, the rewrite instruction for rewriting to the circuit for performing the i-th algorithm processing is I / 0.
It outputs to PLD41 via 31 (step ST5.
3). Thus, the PLD 41, as shown in FIG. 7A,
A processing circuit A is formed with the algorithm of algorithm number 2.

In the present embodiment, circuits such as those shown in FIGS. 8 and 9 are formed in the PLD 41, and the switch 11 is turned on and off so that the logic circuit shown in FIG. 8 can be formed. did.

FIG. 8 schematically shows a circuit configuration of a logic array 20 which constitutes a PLA which is a programmable functional device according to one embodiment of the present invention. PLA12
Is a PLD having a relatively simple configuration, and the AND plane unit 2
2 and an OR plane portion 24. Note that FIG. 8 is a diagram in which a part of the circuit configuration of the logic array 20 is extracted for the purpose of explanation, and the actual logic array 20 is
Has a more complex structure.

In FIG. 8, the AND plane section 22 includes four data input lines L11, L12, which are circuit elements.
L13, L14, four AND input lines L21, L2
2, L23, L24 and four AND gates AN
It is provided with D1, AND2, AND3 and AND4.

Data input line L of AND plane section 22
1 of 11 to L14 and AND input lines L21 to L24
At the six intersections, a switch SW11 serving as a switch means
~ SW44 are provided.

The OR plane section 24 includes four AND output lines L31, L32, L33, L34, 3 which are circuit elements.
OR input lines L41, L42, L43, three O
R gates OR1, OR2, OR3 and three ORs
The output lines L51, L52, and L53 are provided.

Similar to the AND plane section 22, the OR plane section 24
The switches SW51 to SW83 as switch means are provided at 12 intersections of the AND output lines L31 to L34 and the OR input lines L41 to L43.

In FIG. 8, for convenience of explanation, four AND gates AND1, AND2, AND3 and AND are provided.
4 and three OR gates OR1, OR2 and OR3 are used, but in an actual circuit, these gates are replaced with seven NAND gates, which are logically equivalent to FIG. The circuit is realized.

FIG. 9 shows a circuit configuration of the switch SW11. In this embodiment, the switch SW11 is composed of the ferroelectric transistor 30. The same applies to the other switches SW12 to SW83.

In the switch SW11, when a predetermined voltage is applied between the gate terminal G and the data input line L11, the ferroelectric layer FE is polarized. Ferroelectric layer FE
The polarization direction depends on the direction of the applied voltage. When the polarization direction of the ferroelectric layer FE is changed, the threshold value of the transistor is changed. In this way, the switch SW11 can be switched from the closed state to the open state and from the open state to the closed state.

The gate terminal G and the data input line L
The relationship between the direction of the voltage applied to the ferroelectric layer 11 and the polarization direction of the ferroelectric layer FE is not necessarily fixed because it is influenced by other factors. However, at least under the same conditions, the same relationship is brought about. For example,
When a voltage in which the gate terminal G is positive is applied to the data input line L11, it is polarized in a direction in which a predetermined drain current flows with respect to a predetermined gate voltage, and when a reverse voltage is applied, a predetermined voltage is applied. If the gate voltage is polarized in such a direction that only a drain current smaller than the predetermined value flows, the former corresponds to the closed state of the switch SW11 and the latter corresponds to the open state of the switch SW11.

As described above, by changing the direction of the voltage applied between the gate terminal G and the data input line L11, the interruption data of the switch SW11 can be rewritten.

In the above-described embodiment, the polarization direction of the ferroelectric layer FE is made different by changing the direction of the voltage applied between the gate terminal G and the data input line L11. An electrode terminal is connected to the end of the ferroelectric layer FE opposite to the gate terminal G, and this is used as a memory gate terminal MG, and the direction of the voltage applied between the gate terminal G and the memory gate terminal MG is changed. Accordingly, the ferroelectric layer FE can be configured to have different polarization directions.

In order to obtain a desired logic circuit, what kind of rewriting instruction, that is, which transistor is turned on or off in FIG.
It can be realized by using the L (Hardware discription Langage) language.

The CPU 23 then proceeds to step ST in FIG.
Returning to step 3, it is determined whether the F flag is on. In this case, since the F flag is not on, the process proceeds to step ST31 in FIG. 5 and it is determined whether or not the next input data is given.
If not given, the process proceeds to step ST39, and it is determined whether or not there is an end command. If the end command is not given, the process of step ST31 is repeated.

Here, the output data "00" shown in FIG. 6B is used.
When "1" is input, the CPU 23 adds the supplied input data to the input value list of the hard disk 26 (step ST32), and outputs this input data to the PLDs 40 and 41 (step ST33).

Next, the CPU 23 determines whether or not the output data (reference output data and learning output data) from both sides match (step ST41). In this case, PL
Output data “110” is obtained from both D40 and D41. That is, since the output signals given from PLD 40 and PLD 41 coincide with each other, the process proceeds to step ST61, and CPU 23 determines that no rewriting is performed.

Next, the input data "11" shown in FIG.
Consider the case where "1" is given. In this case, similarly, in step ST3 of FIG. 4, since the F flag is not on, the process proceeds to step ST31, and when input data is given, this input data is added to the input value list of the hard disk 26 (step ST32), and the PLDs 40 and 41 are added. The input data “111” is output to (ST33).
In this case, the PLD 40 outputs “10
0 ”is given. On the other hand, output data “000” is given from the PLD 41. In this case, since the two do not match, the process proceeds from step ST41 to step ST43,
The processing target algorithm number i is initialized, and then the processing target algorithm number i is incremented (step S
T45), the i-th algorithm is called.

First, the first algorithm is called.
In this case, since the output data “100” is not satisfied with respect to the input data “111” shown in FIG. 6C, the process proceeds to step ST51 in step ST49. Step ST5
In 1, it is determined whether all the algorithms have been detected, and the process returns to step ST45. When the algorithm shown in FIGS. 11A, 11B, 11C is read as the i-th algorithm by repeating this process, the input data “000” “001” stored in the input value list of the hard disk 26 is read.
For each input data of "111", the first bit, the second
The processing of the bit and the third bit is performed as shown in FIG.
When processed by the algorithms of B and C, FIG.
Output data shown in B and C can be obtained. Therefore, the CPU 23 transfers the data to the PLD 41 via the I / 031.
A rewrite command is given so as to satisfy the hardware configuration for executing the A, B, and C algorithms. This allows
The PLD 41 can be rewritten as the processing circuit A ′ shown in FIG. 7B. The rewriting process has already been described and will not be described.

In this way, the inputted input data is stored in the input value list of the hard disk 26, an algorithm that satisfies all the input data is determined, and the PLD 41 is rewritten with such an algorithm to obtain the optimum algorithm. The PLD 41 to be executed can be duplicated.

In this embodiment, the algorithm number to be processed is initialized so that the algorithm once examined can be examined again.
However, the algorithm already examined may not be examined. In this case, in order to prevent such reexamination, the processing target algorithm number i may not be initialized.

Further, for the given input data, the algorithm that satisfies all the input data may not be stored in the hard disk 26. For this reason,
The following processing is performed.

In such a case, step ST51 in FIG.
In, even if all the algorithms stored in FIG. 3 are examined, there is no satisfied algorithm. In this case, the CPU 23 proceeds to step ST55 and issues a rewrite command for creating a switching circuit to P via I / 031.
Give to LD41. Further, the F flag is turned on.

Regarding the processing in step ST55,
This will be described with reference to FIG. In this case, it is assumed that the circuit of the processing circuit A ′ has already been generated in the PLD 41. C
The PU 23 further inputs the input data “010” shown in FIG. 6D.
When the processing circuit A ′ is used when
It is determined that the output data “000” is not given, and the processing circuit A ′ processes the input data “010”.
Separately from the above, the processing circuit B outputs a rewrite command generated in the PLD 41.

In this case, since it is necessary to give the input data "010" to the processing circuit B and the other data to the processing circuit A ', in order to switch this before the processing circuits A'and B. , Comparison circuit, register,
And a switch are provided.

Specifically, given input data,
It is given to the comparison circuit A and the comparison circuit B, respectively. Register A
The input data processed by the processing circuit A ′ and the input data processed by the processing circuit B are stored in the register B and the register B, respectively. It is determined which of the input data matches the given input data, and if they match, the comparison circuits A and B output a connection signal for connecting the switches swa and swb. In this way, the data given in parallel can be processed by either processing circuit A ′ or processing circuit B.

The connection switch is forcibly turned on during the learning operation in order to determine which processing circuit should be used when another input data is given. Specifically, when the F flag is on, the CPU 23 switches the switch sw shown in FIG.
The connection command for connecting the switch a and the switch swd is output.

For example, once in step ST55 of FIG.
When the rewrite command for generating the switching circuit is output, the F flag indicating this is turned on. Therefore, in such a case, in step ST3 of FIG. 4, the CPU 23 determines that the F flag is on and outputs a switch connection command (step ST5 of FIG. 4).

Next, the CPU 23 determines whether or not the input data is given (step ST7), and if it is not given, it is decided whether or not the end command is given (step ST19), and if not given. The process of step ST7 is repeated.

On the other hand, when the input data is given, the CPU
23 outputs this input data to the PLDs 40 and 41. Learning output data and reference output data are provided from the PLDs 40 and 41. In this case, PLD41
Gives the following two learning output data.

First, the processing circuit A'provides a result obtained by executing the algorithms A, B and C shown in FIG. Further, from the processing circuit B, output data is given as a result of executing the No. 5 algorithm shown in FIG. The two output data are compared with the reference output given from the PLD 40.

If they match in either case, it is determined in step ST13 that there is something that is satisfied, and an instruction to add the input data given to the corresponding register is output (step ST15). For example, when the output data processed by the processing circuit A ′ matches, the input data given to the register A is stored. As a result, when the same input data is given again, it is processed by the processing circuit A ′.

In this way, a plurality of processing circuits have already been processed by P.
If it is stored in the LD 41, the contents of each register are changed so as to be processed by one of the processing circuits.

On the other hand, in step ST13, if the learning output data from any of the processing circuits (processing circuits A'and B) does not match the reference output data from the PLD 40, the process proceeds to step ST17 to input the input. The processing circuit C for processing the data outputs a rewrite command for configuring the PLD 41 in the same manner. That is, in this case, the same comparison circuit C and register C are provided to process the processing circuit C (not shown).

In this case, since the switch (not shown) of the newly generated processing circuit C has already been given the switch connection command in step ST5, it is forcibly turned on.

As described above, by providing a plurality of processing circuits and a switching unit for determining which processing circuit is to be supplied with the input data, even when none of the algorithms shown in FIG. PLD4
The PLD 41 having the same function as 0 can be generated.

By repeating the above process, the process shown in FIG.
When the end command is given at 9, the CPU 23 causes the PLD 4
For 1, the switch connection release command for releasing the switch connection command is output. As a result, the switches swa, swb, ... Shown in FIG. 10 are disconnected. Thus, by turning off the switch at the end of the learning operation, the processing is performed by the corresponding processing circuit only when the same input data stored in each register is given.

The PLD thus duplicated
The circuit configuration of 41 may be different from that of the PLD 40. However, the PLD 41 is functionally equivalent to the PLD 40.
Is the same as

As described above, in the present embodiment, as shown in FIG.
In step ST49, it is examined whether or not there is data that satisfies all the input data stored in the memory 27. If there is data that satisfies all of them, a processing circuit that executes an algorithm for processing this is set in the PLD 41. I am trying to generate. In this way, by performing the optimization process,
It is not necessary to configure the circuit that executes each algorithm in the PLD 41. Therefore, P with a small capacity
It is possible to generate an LD having the same function as the PLD 40.

4. Other Embodiments In the above embodiment, the rewriting target device 19 is composed of only the rewriting target circuit.
May be configured as follows.

The rewriting target device 19 is the rewriting target circuit 1
9a, a first control target unit 19b, and a first detection unit 19c that detects the operation of the first control target unit 19b. The first control target section 19b is controlled by the rewrite target circuit 19a. The first detection unit 19c includes the first control target unit 19
The operation of b is detected. Further, the replication target device 17 includes a replication target circuit 17a, a second control target section 17b, and a second control target section 17b.
It has a detector 17c. The second control target unit 17b is controlled by the replication target circuit 17a. Second detector 1
7c detects the operation of the second controlled unit 17b. The rewriting means 7 includes a first detection unit 19c and a second detection unit 17c.
Matching judgment is performed by using the detection data detected in step 2 as output data.

In this way, not only is the PLD 40 having the same function duplicated from the PLD 40, but a device in which an external device (for example, a motor) is added to the PLD is considered as a duplication target device, and a similar rewriting target logic As a device
This may be considered as including another external device (motor).

For example, as shown in FIG. 12, when certain input data is given to the device 70, what kind of detection data can be given from the detector 77 is inputted as reference data, and the rewriting target device is inputted. When the same input data is given to 80, it is determined what kind of detection data can be obtained from the detector 87, and the PLD is set so that they match.
The content of 73 may be rewritten. This allows
Even when the characteristics of the motor M1 and the motor M0 are different, the rewrite target device 80 having the same function as the device 70 can be obtained as a result.

In this embodiment, all the input data are stored in the memory 27, and it is determined whether or not this is satisfied. However, only the input data that is frequently used or used many times may be stored.

Note that the algorithm of the first bit in FIG. 11C may be executed by the algorithm shown in FIG. 11D. The algorithm shown in FIG. 11A can also be executed by the algorithm shown in FIG. 11B. In this way, by storing the algorithm that refers to the relationship with the preceding and following bits, it is possible to store the algorithm that can obtain the output data that satisfies more input data.

In this embodiment, a logic circuit for executing a certain algorithm, such as the processing circuit A'and the processing circuit B (see FIG. 10), is formed in the PLD 41. A table of data may be stored.

Further, in the present embodiment, it is determined whether or not the reference output data and the learning output data match, and by using this, one of the algorithms shown in FIG. There is. However, the present invention is not limited to this, and the input data and the output data may be obtained from the difference between the learning output data and the reference output data and the given input data. In this way, it is possible to obtain the input and output data directly or indirectly.

Although the algorithm numbers shown in FIG. 3 are examined in ascending order, the priority may be designated. For example, a processing algorithm such as a digital filter can be specified by a predetermined calculation formula. Therefore,
You may make it consider preferentially according to the characteristic of the input data given. This makes P faster
The contents of the LD 41 can be rewritten.

Further, in the present embodiment, the given input data is independently examined. However, the output data to be processed may be considered in relation to the input data given one before. In this case, of the input data that has already been input, the input data immediately before the input data is read, and the value of the input data immediately before is read as a condition.

For example, even with the same input data "001",
If the input data immediately before that is “000”,
In the case of "1", the output data may be different.
In such a case, the input data immediately before the input data "001" may be judged to be "000" or the input data "111".

When considering such a history, it is possible to consider not only one before but also two before, three before ....

In this embodiment, the PLDs 40 to 41 are duplicated so as to have the same function. As described above, in order to obtain the PLD 41 from the PLD 40, it is necessary to examine a large amount of input data, which takes a very long time. But once it's done, it doesn't take long to duplicate it. Therefore, once a PLD having the same function is obtained, the contents of this PLD 41 are read out, and this is read by another PLD.
D may be rewritten. Specifically, ROM
Read the data with a reader and use the ROM writer to
You should write it. As a result, when the contents of the PLD 40 cannot be read, or when the circuit to be replicated is not the PLD, P having the same function is used.
A plurality of LDs can be formed in a short time.

In the present embodiment, the case where the input data having a bit length of 3 bits as shown in FIG. 6 has been described, but the data structure of the input data is not limited to this. Absent.

In each of the above-described embodiments, the ferroelectric memory element having the ferroelectric capacitor and the ferroelectric transistor have been described as the memory element having the ferroelectric substance. However, the ferroelectric element has the ferroelectric substance. The memory element is not limited to a ferroelectric memory element having a ferroelectric capacitor or a ferroelectric transistor.

As an example of the programmable functional device, the PLA, which is a type of PLD, has been described in the example shown in FIGS. 8 and 9, but the present invention is not limited to this and is also applicable to an FPGA that is a type of PLD. It is possible. Further, the present invention is
The present invention is not limited to the PLD, and is generally applied to programmable functional devices.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a function duplication device 1 according to the present invention.

FIG. 2 is a diagram showing an example of a hardware configuration of a function duplication device 1 shown in FIG.

FIG. 3 is a diagram showing an example of an algorithm stored in a hard disk 26.

FIG. 4 is an overall flowchart.

FIG. 5 is an overall flowchart.

FIG. 6 is a diagram showing an example of input data given to a duplication target circuit and reference output data outputted.

FIG. 7 is a diagram showing a circuit configuration of a PLD 41.

FIG. 8 is a drawing schematically showing a part of the circuit configuration of the logic array that constitutes the PLA according to the embodiment of the present invention.

FIG. 9 is an enlarged circuit diagram of a switch used in a logic array forming a PLA according to an embodiment of the present invention.

FIG. 10 is a diagram showing a circuit configuration of a PLD 41.

FIG. 11 is a diagram showing an example of an algorithm stored in a hard disk 26.

FIG. 12 is a diagram for explaining another embodiment.

[Explanation of symbols]

─────────────────────────────────────────────────── --- Continuation of front page (56) Reference JP-A-8-46509 (JP, A) JP-A-6-224743 (JP, A) JP-A-6-180664 (JP, A) JP-A-6- 348533 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 19/173 G06F 17/50

Claims (5)

(57) [Claims] 1. A device for duplicating a function of a duplication target device which outputs output data corresponding to given input data, wherein the given input data is a rewriting target device and the duplication target. Input giving means to the device, judgment information storage means for storing a plurality of logical information for obtaining output data corresponding to specific input data as a candidate, of the plurality of candidates stored in the judgment information storage means,
For all the given input data, specify a candidate in which the output data given from the rewriting target device and the output data given from the copied target device match,
Rewriting means for giving a rewriting command to the rewriting target device so that the logical information of this candidate can be realized, 1) the rewriting means, 1) output data given from the rewriting target device and the duplication target device When a candidate whose output data to be given matches is found, a rewriting instruction is given to the rewriting target device so that the logical information of this candidate can be realized, and the given input data is stored. 2) When another input data is given, it is judged whether or not there is a candidate satisfying all of this input data and the stored input data. A function duplication device, wherein a rewriting command is given to the device to be rewritten so that logical information can be realized. 2. A device for duplicating a function of a duplication target device which outputs output data corresponding to given input data, wherein the given input data is a rewriting target device and the duplication target. Input giving means to the device, judgment information storage means for storing a plurality of logical information for obtaining output data corresponding to specific input data as a candidate, of the plurality of candidates stored in the judgment information storage means,
For the given input data, the rewriting is performed so as to identify a candidate in which the output data given from the rewriting target device and the output data given from the duplication target device match, and to realize the logical information of the candidate. Rewriting means for giving a rewriting command to the target device, for all input data, when there is no candidate in which the output data given from the rewriting target device and the output data given from the copied target device do not exist, A function duplicating device, characterized in that a rewriting command is provided to provide a plurality of regions for data processing in the rewriting target device according to given input data. 3. The function duplicating apparatus according to claim 1 or 2, further comprising: a logical configuration reading unit that reads out a logical configuration of the rewriting target device and outputs the logical configuration. 4. A function duplication method for duplicating a function of a duplication target device which outputs output data corresponding to given input data, for obtaining corresponding output data for specific input data. A plurality of pieces of logical information are stored as candidates, the predetermined input data is given to the rewriting target device and the duplication target device, and all the given input data among the plurality of candidates are written from the rewriting target device. A function duplication method that specifies a candidate in which given output data and output data given from the duplication target device match, and gives a rewriting instruction to the rewriting target device so that logical information of the specified candidate can be realized. 1) the output data given from the rewriting target device and the output data given from the duplicated device match. When a candidate is found, the rewriting target device is given a rewriting command so that the logical information of this candidate can be realized, and the given input data is stored, and 2) another input data is stored. Is given, it is judged whether or not there is a candidate that satisfies all of this input data and the stored input data, and if there is such a candidate, the logical information of this candidate can be realized. So that a rewriting command is given to the rewriting target device. 5. A method of duplicating a function of a duplication target device which outputs output data corresponding to given input data, wherein the given input data is a rewriting target device and the duplication target. A plurality of pieces of logical information for giving output data corresponding to specific input data to a device are stored as candidates. Among the plurality of stored candidates, given input data is written from the device to be rewritten. A rewrite command is given to the rewriting target device so that logical information of this candidate can be realized by specifying a candidate in which the output data given and the output data given from the device to be duplicated match, and all the input data A candidate in which the output data given from the rewriting target device and the output data given from the copied target device match If there is not, a function duplication method is provided, in which a rewriting command for providing a plurality of regions for data processing in the rewriting target device according to given input data is given.