JP3511732B2 - Semiconductor nonvolatile storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable memory, for example, a semiconductor nonvolatile memory device such as a flash EEPROM.

[0002]

2. Description of the Related Art As an electrically rewritable memory, data is written by extracting electrons in the floating gate from the drain side by FN (Fowler-Nordheim) tunneling, and erasing is also performed by FN tunneling. There is known a DINOR type flash memory that is implemented by injecting.

Bias conditions in the erase operation, write operation, verify read operation, and read operation of the DINOR type flash memory will be briefly described below with reference to FIGS. 18, 19, 20, and 21, respectively.

18, FIG. 19, FIG. 20 and FIG.
2 of 2 main bit lines and 8 word lines connected to sub bit lines
Each of the DINOR type flash memories composed of groups is shown.

In FIGS. 18, 19, 20, and 21, WL1m to WL8m, WL1m + 1 to WL8m +
1 is a word line, SLm and SLm + 1 are select gate lines, M
BLn, MBLn + 1 are main bit lines, SBLm, n, S
BLm + 1, n, SBLm, n + 1, SBLm + 1, n
+1 is a sub-bit line, SRL is a common source line, MT1m,
n to MT8m, n, MT1m + 1, n to MT8m + 1,
n, MT1m, n + 1 to MT8m, n + 1, MT1m + 1
, N + 1 to MT8m + 1, n + 1 are memory transistors, STm, n, STm + 1, n, STm, n + 1, S.
Tm + 1 and n + 1 indicate selection transistors, respectively.

In the erase example of FIG. 18, WL1m to W
This is a case where the memory cell transistors connected to the L8m word line block are erased. In this case, 20V is applied to the selected word lines WL1m to WL8m, all the selection gate lines SLm and SLm + 1, and the other word lines WL1.
m + 1 to WL8m + 1 and 0 to common source line SRL
V is applied to all the main bit lines MBLn, MBLn
Bias +1 to floating state. as a result,
Electrons are injected into the floating gates of the memory cell transistors connected to the selected word line blocks WL1m to WL8m by FN tunneling, and the threshold voltage Vth of the memory cell transistors becomes 5V or higher.

In the write example of FIG. 19, the word line WL4m is used.
In the case of collectively writing word lines to the memory cell transistors connected to the memory cell transistors MT4m, n +, the memory cell transistor MT4m, n surrounded by a solid line in the figure is written with "1" data, and the memory cell transistor MT4m, n + surrounded by a dotted line in the figure
Write "0" data to 1. In this case, the select gate line SLm has a voltage of 10 V, and the selected word line WL4m has a voltage of −10.
V, other gate lines SLm + 1, and other word lines WL1m to WL3m, WL5m to WL8m, WL1
0V is applied to m + 1 to WL8m + 1, and the common source line S
Main bit connected to memory cell transistor MT4m, n + 1 for writing 6V, "0" data to main bit line MBLn connected to memory cell transistor MT4m, n for writing "1" data by biasing RL to a floating state 0V is applied to the line MBLn + 1. As a result, only the memory cell transistors MT4m, n, FN
The electrons in the floating gate are extracted by the drain due to the tunneling, and the threshold voltage Vth of the memory cell transistor transits to about 1V to 2V.

The verify read operation of FIG. 20 is similar to that of FIG.
Whether the threshold voltage Vth of the memory cell transistor MT4m, n in which “1” data is to be written is changed to the verify read voltage or less, in this case, 2V or less, as a result of the write operation performed immediately after the write operation of 9. Find out. In this case, 3.3V is applied to the select gate line SLm,
2V to the selected word line WL4m, 1V to the selected main bit line MBLn, other gate lines SLm + 1, and other word lines WL1m to WL3m, WL5m to WL
8m, WL1m + 1 to WL8m + 1, and other main bit lines MBLn + 1 and 0 on the common source line SRL
Apply V. As a result, when the selected memory cell transistor MT4m, n is in the off state, it is determined that writing to the memory cell transistor is not sufficient,
When it is in the ON state, it is determined that writing to the memory cell transistor is completed.

The read example in FIG. 21 is a case where the memory cell transistors MT4m, n surrounded by a solid line in the figure are read. In this case, the selected gate line SLm and the selected word line WL4m are 3.3V, the selected main bit line MBLn is 1V, the other gate lines SLm + 1, and the other word lines WL1m to WL3m and WL5m to W.
0V is applied to L8m, WL1m + 1 to WL8m + 1, other main bit lines MBLn + 1, and common source line SRL. As a result, when the selected memory cell transistor MT4m, n is in the off state, it is in the data “0” (erased state), and in the on state, it is in the data “1” (written state).

FIG. 22 shows the bias conditions in the erase operation, write operation, verify read operation and read operation of the DINOR type flash memory described above.

As another electrically rewritable flash memory, data writing is performed by injecting electrons into the floating gate from the drain side by CHE (channel hot electrons), and erasing is performed by FN tunneling. There is known a NOR type flash memory that is performed by extracting electrons from a source to a source.

The bias conditions in the erase operation, verify read operation, write operation, and read operation of the NOR flash memory will be described below with reference to FIGS. 23 and 2, respectively.
4, FIG. 25, and FIG. 26, and will be briefly described.

In FIGS. 23, 24, 25 and 26, WLm-1, WLm and WLm + 1 are word lines and B is a word line.
Ln-1, BLn, BLn + 1 are bit lines, SRL is a common source line, MTm-1, n-1, MTm-1, n, M
Tm-1, n + 1, MTm, n-1, MTm, n, MT
m, n + 1, MTm + 1, n-1, MTm + 1, n, M
Tm + 1 and n + 1 indicate memory cells, respectively.

In the erase example of FIG. 23, memory cell transistors MTm, n connected to the selected word line WLm.
This is a case where word line sector erase is performed for -1, MTm, n, MTm, n + 1. In this case, the selected word line WLm is -10V, and the other word lines WLm-1,
0V on WLm + 1, all bit lines BLn−1, BL
Bias n and BLn + 1 to the floating state,
5V is applied to the common source line SRL. As a result, the memory cell transistor M connected to the selected word line WLm
The electrons in the floating gates of Tm, n-1, MTm, n, MTm, n + 1 are extracted from the source side by FN tunneling, and the threshold voltage Vth of the memory cell transistor becomes about 1V to 2V.

The verify read operation of FIG. 24 is the same as that of FIG.
3 is performed immediately after the erasing operation, and as a result of the erasing operation, the memory cell transistors MTm, n−1 to be erased,
It is checked whether the threshold voltage Vth of MTm, n, MTm, n + 1 has transitioned to the verify read voltage or less, in this case 3V or less. In this case, select the word line WL
3V for m, all bit lines BLn-1, BLn, BL
1V is applied to n + 1, other word lines WLm−1,
0V is applied to WLm + 1 and the common source line SRL. As a result, the selected memory cell transistor MT
When m, n−1, MTm, n, MTm, n + 1 are in the off state, it is determined that the erasing of the memory cell transistor is not sufficient, and when they are in the on state, it is determined that the erasing of the memory cell transistor is completed.

The write example of FIG. 25 is a case where data is written to the memory cells MTm, n surrounded by solid lines in the figure. In this case, 12V is applied to the selected word line WLm, 7V is applied to the selected bit line BLn, and the other word lines WLm−1, WLm + 1, the bit lines BLn−1, BLn.
0V is applied to +1 and the common source line SRL. As a result, electrons are injected into the floating gate by channel hot electrons (CHE) only in the selected memory cell transistor MTm, n, and the threshold voltage Vth becomes 5V or higher.

The read example of FIG. 26 is a case where data is read from the memory cell transistors MTm, n surrounded by a solid line in the drawing. In this case, the selected word line WLm is 5V, the selected bit line BLn is 1V, the other word lines WLm−1, WLm + 1, and the other bit line B.
0V to Ln-1, BL + 1 and common source line SRL
Is applied. As a result, when the selected memory cell transistor MTm, n is in the off state, it is determined that the data of the memory cell transistor is "1" (write state), and when it is in the on state, the data of the memory cell transistor is It is determined to be "0" (erased state).

FIG. 27 summarizes the bias conditions in the erase operation, verify read operation, write operation, and read operation of the NOR flash memory described above.

[0019]

By the way, the above-mentioned D
In the operations of the INOR flash memory and the NOR flash memory, the write operation / verify read operation or the erase operation / verify read operation are alternately repeated. Therefore, during the above operation period, two types of word line application voltages, that is, the applied write voltage or applied erase voltage which is a predetermined negative voltage and the verify read voltage which is a predetermined positive voltage are alternately and repeatedly applied to the selected word line. There is a need.

DINOR shown in FIGS. 19 and 20, for example.
Type flash memory, applied write voltage -10V and verify read voltage 2 are applied to the selected word line.
V is alternately and repeatedly applied. In the case of the NOR flash memory shown in FIGS. 23 and 24, the applied erase voltage −10V and the verify read voltage 3V are alternately and repeatedly applied to the selected word line.

However, since a predetermined negative voltage and a predetermined positive voltage are alternately and repeatedly applied to the selected word line,
There is a problem that it takes a very long time to charge and discharge the word line. Moreover, since the number of repetitions of the above-described write operation / verify read operation or erase operation / verify read operation is performed a great number of times, the time required for charging / discharging the word line is more dominant than the actual write time or erase time. Therefore, high-speed writing or erasing was very difficult.

For example, the DINO shown in FIGS. 19 and 20.
In the case of the R-type flash memory, the number of times the write operation / verify read operation is repeated is about 100 times, and the time required to charge or discharge the word line is about 100 times.
It is about μ seconds. Therefore, the time required for charging / discharging the word lines is about 20 msec in total, which is dominant with respect to the time actually required for writing of about 1 msec.

28 and 29 show the above-mentioned DINO.
FIG. 6 is a circuit diagram showing respective bias states of a selected word line driver in a write operation / verify read operation of an R-type flash memory. 28 and 29
Is a p-channel MOS (hereinafter,
P type) Transistor TP1, n channel MOS
It is an inverter circuit including a transistor TN1 (hereinafter referred to as N type). That is, as shown in FIG. 28, in the write voltage application operation, the selected word line driver operates in the voltage range in which the plus side voltage value is 0 V and the minus side voltage value is −10 V, and the selected word line driver operates in response to the address signal. The word line output is inverted.

On the other hand, as shown in FIG. 29, in the verify read operation, the selected word line driver operates in the voltage range in which the plus side voltage value is 2V and the minus side voltage value is 0V, and the address The word line output is normally output with respect to the signal.

FIG. 30 and FIG. 31 correspond to FIG.
FIG. 30 is a diagram showing a bias state of the N-type transistor TN1 which is a particular problem in the bias state of the word line driver shown in FIG. 29. As shown in FIGS. 30 and 31, the N-type transistor TN1 is formed in PWELL in NWELL because it operates at a negative voltage. That is, as shown in FIG. 30, in the write voltage application operation, the source diffusion layer and the PWELL substrate of the N-type transistor TN1 are biased to −10V.

On the other hand, as shown in FIG. 31, in the verify read operation, the N-type transistor TN is used.
1 biases the source diffusion layer and the PWELL substrate to 0V.

The source diffusion layer of the N-type transistor TN1 and the PWELL substrate are charged / discharged not only in the selected word line driver circuit but also in all word line driver circuits. Therefore, when the write voltage applying operation and the verify read voltage applying operation are switched, or when the verify read voltage applying operation and the write voltage applying operation are switched, a large load is applied to the negative voltage booster circuit that generates the applied write voltage, and the operation voltage switching is performed. It will take a long time.

FIG. 32 is a diagram showing a timing chart of the output voltage value level of the selected word line in the write operation / verify read operation of the DINOR type flash memory described above. In FIG. 32, φw / v
Is a signal for controlling whether a write voltage application operation or a verify read voltage application operation is performed, and operates at a logic operation voltage level of 3.3V / 0V. Further, WL is the output of the selected word line, and is biased to −10 V during the write voltage application operation and to 2 V during the verify read voltage application operation.

As shown in FIG. 32, even if the control signal φw / v changes from the high level to the low level at the times t1 and t3 and the write voltage applying operation is switched to the verify read voltage applying operation, the word line output WL is still It cannot change immediately, but changes from −10V to 2V at times t1 ′ and t3 ′. Similarly, even if the control signal φw / v changes from the low level to the high level at the times t2 and t4 and the verify read voltage applying operation is switched to the write voltage applying operation, the word line output WL cannot immediately change, Time t
It changes from 2V to -10V at 2'and t4 '. Therefore, the time required for charging / discharging the word line becomes dominant over the time actually required for writing, and high-speed writing becomes very difficult.

The present invention has been made in view of such circumstances, and an object thereof is to enable switching between a write voltage application operation or an erase voltage application operation and a verify read operation in a short time, and thus a high speed write or An object is to provide a semiconductor nonvolatile memory device that can be erased.

[0031]

In order to achieve the above object, the present invention provides a write voltage for applying a predetermined voltage for writing or erasing data when a data writing or erasing operation for a memory cell is performed. applying operation or verify read operation for detecting whether a write or erase data has been completed with respect to the erase voltage application operation and the memory cells in the semiconductor nonvolatile memory device is performed by alternately repeating, a plurality of word
A specific word in each word line block consisting of
The main row decoder that selects the line block and the main
Within the word line block selected by the narrow decoder
Predetermined applied write voltage for each word line or
Two types of voltage, applied erase voltage and verify read voltage
Sub-row decoder that can simultaneously output the applied voltage to parallel lines
And the two types of word lines from the sub row decoder
Either one of the applied voltage is applied to the above data write operation or
Is a word that is selectively switched and output according to the erase operation
Line applied voltage switching unit and word line applied voltage switching
Application of the above two types of word lines selected and output by the display section
One of the voltage applied to the word line
-In the word line block selected by the decoder
Word line output transmission for transmission to each word line
And a department .

Further, in the semiconductor nonvolatile memory device, the bit lines are hierarchized into the main bit lines and the sub bit lines, the main bit lines and the sub bit lines are selectively connected according to the operation, and the sub bit lines are sub-connected. This is a DINOR type flash memory in which a plurality of memory cells are connected in parallel to a bit line.

Alternatively, the semiconductor nonvolatile memory device is a NOR flash memory in which memory cells arranged in a matrix are connected to a plurality of word lines and bit lines.

[0034]

Further, the main row decoder decodes at least one row address input signal operating at a logic operation voltage level and determines whether or not the word line block should be selected for each word line block. A decode circuit that outputs a decode signal to be controlled, and the operation voltage level of each of the decode signals is converted from a logical operation voltage level to a predetermined voltage value level and a word line block is selected for each word line block. A voltage conversion circuit that generates a signal.

Further, the sub row decoder decodes at least one row address input signal which operates at a logic operation voltage level, and whether or not the word line should be selected for each word line in the word line block. And a write circuit for outputting a decode signal for controlling whether or not, and an applied write voltage for converting the operation voltage level of each of the above-mentioned decode signals from a logical operation voltage level to a predetermined voltage value level and applying it to each word line. Alternatively, a first voltage conversion circuit for generating an applied erase voltage and a verify operation for converting the operation voltage level of each of the decode signals from a logical operation voltage level to a predetermined voltage value level and applying the voltage to each word line. A second voltage conversion circuit that generates a read voltage.

Further, the word line applied voltage switching section operates according to a control signal for controlling whether the write voltage applying operation or the erase voltage applying operation or the verify read operation should be performed according to the data write operation or the erase operation. A voltage conversion circuit that converts a voltage level from a logic operation voltage level to a predetermined voltage value level to generate a word line applied voltage switching signal, and a word conversion circuit provided corresponding to each word line forming a word line block A multiplexer circuit for receiving at least two inputs and selecting one output, wherein two input terminals are respectively connected to supply lines of two kinds of word line applied voltages from the sub row decoder to receive the word line applied voltage switching signal. And a multiplexer circuit that outputs one of the word line applied voltages.

The word line output transmission section is a switch formed of a semiconductor element provided corresponding to each word line, and one terminal has the word line applied voltage to which the word line corresponds. The word line block of the word line block selected by receiving the word line block selection signal is connected to the supply line of the word line applied voltage selectively output by the switching unit and the other terminal is connected to the word line in the memory array. It has a switch circuit in which only the switches are connected and the other switches are disconnected.

Further, two kinds of word line applied voltages, that is, a word line block selection signal from the main row decoder and an applied write voltage or applied erase voltage and a verify read voltage to each word line from the sub row decoder are During the data writing operation period or the erasing operation period, the respective predetermined voltage values are fixed.

Further, the word line block selection signal and the word line applied voltage switching signal are applied to the respective predetermined applied write voltage or applied erase voltage and verify read voltage output from the sub row decoder. The voltage value on the low voltage side is equal to or less than the voltage value, and the voltage value on the high voltage side is equal to or more than the voltage value. The low-voltage side voltage value is a predetermined negative voltage, and the high-voltage side voltage value is a predetermined positive voltage.

[0041]

According to the semiconductor non-volatile memory device of the present invention, a predetermined applied write voltage or applied erase voltage and verify read voltage to be applied to the selected word line can be used.
Different types of word line applied voltages are always output in parallel during a data write operation or an erase operation, and the above 2
Either one of the types of word line applied voltages is selectively switched to the selected word line and output according to the operation during the data write operation or the erase operation. Thus, for example, in the write operation of the DINOR type flash memory or the erase operation of the NOR type flash memory, it becomes possible to switch the above two types of word line applied voltages in a short time.

In the above operation, for example, the main row decoder selects a specific word line block of each word line block formed of a plurality of word lines. Two of a predetermined applied write voltage or applied erase voltage and verify read voltage are applied to each word line in the word line block selected by the main row decoder.
The types of word line applied voltages are simultaneously output in parallel by the sub row decoder. Then, in the word line applied voltage switching section, either one of the above-mentioned two types of word line applied voltages from the sub row decoder is selectively switched and output according to the data write operation or erase operation. The word line applied voltage of either one of the above-mentioned two types of word line applied voltages selected and output by the word line applied voltage switching unit is stored in the word line block selected by the main row decoder by the word line output transfer unit. Is transmitted and output to the word line.

In the main row decoder, the decode circuit decodes at least one row address input signal operating at the logical operation voltage level, and the word line block is selected for each word line block. A decode signal that controls whether or not to output is output. Then, the voltage conversion circuit converts the operation voltage level of each decode signal from the logic operation voltage level to a predetermined voltage value level, and generates a word line block selection signal for each word line block.

In the sub row decoder,
A decode circuit decodes at least one row address input signal that operates at the logical operation voltage level, and controls the decode signal for controlling whether or not the word line in each word line block should be selected. Is output. Based on this decode signal, the first voltage conversion circuit converts the operation voltage level of each of the decode signals from the logical operation voltage level to a predetermined voltage value level, and applies the write voltage applied to each word line. Alternatively, an applied erase voltage is generated. In the second voltage conversion circuit, the operating voltage level of each decode signal is converted from the logical operating voltage level to a predetermined voltage value level, and the verify read voltage applied to each word line is generated. .

In the word line applied voltage switching unit, the voltage conversion circuit controls whether the write voltage applying operation or the erase voltage applying operation or the verify read operation should be performed according to the data writing operation or the erase operation. The operating voltage level of the control signal is converted from the logical operating voltage level to a predetermined voltage value level, and the word line applied voltage switching signal is generated. Then, the multiplexer circuit receives the word line applied voltage switching signal and outputs one of the word line applied voltages.

In the word line output transmission unit, the switch circuit receives the word line block selection signal, and only the switch of the selected word line block is connected and the other switches are disconnected.

Further, two kinds of word line application voltages, that is, a word line block selection signal from the main row decoder and an applied write voltage or applied erase voltage and a verify read voltage to each word line from the sub row decoder are It is fixed to the respective predetermined voltage values during the data write operation period or the erase operation period. Accordingly, during the operation period, it is not necessary to change the potential of the PWELL substrate of the N-type transistor in the row decoder, and it can be fixed.

Further, with respect to each of the word line block selection signals from the main row decoder and the respective predetermined applied write voltage or applied erase voltage and verify read voltage output from the sub row decoder, the low voltage side is selected. The voltage value is equal to or less than the voltage value, and the high voltage side voltage value is equal to or more than the voltage value. Therefore, the multiplexer circuit in the word line applied voltage switching unit and the switch circuit in the word line output transmission unit can operate with respect to each of the predetermined applied write voltage or applied erase voltage and verify read voltage.

The voltage value on the low voltage side is a predetermined negative voltage, and the voltage value on the high voltage side is a predetermined positive voltage. Therefore, the above-described write operation of the DINOR flash memory or erase operation of the NOR flash memory can be supported.

[0050]

1 and 2 are diagrams showing bias examples of a write voltage application operation and a verify read operation of a DINOR type flash memory according to a first embodiment of the present invention.

The bias example of the write voltage application operation shown in FIG. 1 is the same as the conventional example shown in FIG. 19, but the bias example of the verify read operation shown in FIG. 2 is different from the conventional example shown in FIG. This difference is that the select gate line SLm
That is, the voltage applied to the memory cell does not change at 10 V during the write voltage application operation.

FIG. 3 shows a semiconductor nonvolatile memory device of the present invention for realizing the write voltage application operation and the verify read operation as shown in FIGS. 1 and 2, and particularly the DINOR type flash which is the first embodiment. FIG. 3 is a block diagram of a main part of a memory, centering on a row decoder.

In FIG. 3, 1 is a memory array section of a DINOR type flash memory, 2 is a read / write circuit, 3 is a column decoder, 4 is a main decoder, 5 is a sub decoder, 6 is a word line applied voltage switching section, 7 Indicate the word line output transmission units, respectively.

The memory array section 1 is composed of an array of j word line blocks and k main bit lines, each of which is a block of i word lines connected to the same sub bit line. In the figure, □ represents a selection transistor and ∘ represents a memory transistor.

The main decoder 4 comprises a decoding unit 41, a selection gate line output unit 42, and a word line block selection signal output unit 43. Decoding unit 41
Decodes the row address input signals X1 to Xb operating at the VCC / GND level and generates the corresponding decode signals x1 to xj in each word line block. The selection gate line output unit 42 outputs the decoded signals x1 to xj to VS.
Convert to L / GND level and select gate line output SL1
Generate ~ SLj. The word line block selection signal output unit 43 converts the decoded signals x1 to xj into VPP / VBB levels and controls whether each word line block should be selected or not.
Generate ~ xj '.

The sub row decoder 5 includes a decoding unit 51,
The write / erase word line applied voltage output unit 52 and the verify read word line applied voltage output unit 53 are included. Decoding portion 51 decodes row address input signals x1 to xa operating at the Vcc / GND level and generates decode signals x1 to xi corresponding to the respective word lines in the word line block. The write / erase word line applied voltage output section 52 outputs the decode signals x1 to x.
i is converted to VwE / VBB level to generate write / erase word line applied voltages (Vw) 1 to (Vw) i.
The verify read word line applied voltage output unit 53 converts the decode signals x1 to xi into Vvr / GND level, and the verify read word line applied voltage (Vv) 1.
Generate (Vv) i.

The word line applied voltage switching section 6 is composed of a word line applied voltage switching multiplexer section 61 and a word line applied voltage switching signal generating section 62. Word line applied voltage switching multiplexer unit 61
Is a write / erase word line applied voltage (Vw) 1 to (Vw) i and a verify read word line applied voltage (Vv) 1 to (Vv) i output from the sub row decoder 5.
A word line applied voltage of a type is input, and one of them is output as a word line output V1 to Vi depending on the operation. In the operation of the word line applied voltage switching multiplexer unit 61, the word line applied voltage switching signal generation unit 62
A circuit for generating a word line applied voltage switching signal φw / v ′ for controlling which of the above two types of word line applied voltages is to be selected.
Control signal φw / v that operates at GND level is VPP / VBB
It occurs after converting to a level.

The word line output transmission section 7 comprises switch circuits SW11 to SWji provided corresponding to the respective word lines WL1 1 to WLji, and the main row decoder 4
Word line block selection signals x1 'to x output from
By controlling j ′, the word line outputs V1 to Vi output by the word line applied voltage switching unit 6 are transmitted to the respective word lines in the selected word line block.

In the block diagram of FIG. 3, VCC,
VPP, VwE, Vvr, and VSL are supplied, and the terminal indicated by ○ in the figure is the power source terminal on the positive side, and the voltage GND, V
The terminal indicated by ● in the figure to which BB is supplied is the negative power terminal. Further, Vcc and GND are voltage levels for normal logic operation, which are 3.3 V and 0 V , respectively.

FIG. 4 shows that the voltage value levels of the respective power supply terminals described above are in four operation modes of the erasing operation, the write voltage applying operation, the verify read operation and the read operation of the DINOR type flash memory of the present invention. It is a table showing what kind of voltage value is set.
The particularly important point in the table of FIG. 4 is that the voltage value level of each power supply terminal is set to the same level in the two types of operation modes of the write voltage application operation and the verify read operation. When switching repeatedly,
That is, it is not necessary to repeatedly set the voltage of each power supply terminal again. This is significantly different from the operation of the conventional DINOR flash memory.

That is, as shown in FIG. 4, VCC, GN
Since D is a voltage level for normal logic operation, it is set to 3.3V and 0V regardless of the operation mode. V
PP is set to 20V during the erase operation, and 3.3V during the write voltage application operation, the verify read operation, and the read operation. VBB is set to 0V during the erase operation, −10V during the write voltage application operation and the verify read operation, and 0V during the read operation. VwE
Is set to 20V during the erase operation, 0V during the write voltage application operation and the verify read operation, and 3.3V during the read operation. Vvr is 3.3 during erase operation.
V, 2V during the write voltage application operation and the verify read operation, and 3.3V during the read operation. VSL is set to 3.3V during the erase operation, 10V during the write voltage application operation, and the verify read operation, and 3.3V during the read operation.

FIG. 5 shows a block configuration centered on the row decoder of FIG. 3 and the result of voltage setting of the power supply terminals in each operation mode of FIG. 4, particularly when the write voltage application operation / verify read operation is repeatedly switched. 5 is a timing chart showing how various signals and outputs change in voltage.

Each signal and output shown in FIG. 4 corresponds to the block diagram of FIG. Also, in the figure,
t1 to t13 represent the progress of time, and the progress of this time can be roughly classified into the following two types.

That is, from time t1 to t5, time t
1 for row address input signals X1 to Xa and X1 to Xb
After receiving the write word line applied voltage (Vw) 1 to
(Vw) i and verify read word line applied voltage (V
v) 1 to (Vv) i, two types of word line applied voltages, select gate line outputs SL1 to SLj, and word line block select signals x1 'to xj' are set to respective voltage value levels and output. Is the progression of time.

From time t5 to t13, the write voltage application operation / verify read operation is repeatedly switched, and the word line applied voltage switching signals φw / v and φw / v ′ change at each time, and Accordingly, one of the two types of word line applied voltages is selected, and the word line outputs V1 to Vi and WL11 to WLji are switched and output.

Hereinafter, the timing chart of FIG. 5 will be described sequentially with time. First, at time t1, the sub row decoder 51 receives the row address input signals X1 to Xa, and the main row decoder 41 receives the row address input signals X1 to Xb.

Next, by time t2, the row address input signal is decoded, and in the sub row decoder 51, write word line applied voltages (Vw) 1 to (Vw) i and verify read word line applied voltage (Vv) 1. ~ (Vv) i
2 types of word line applied voltage, main row decoder 41
Within, the selection gate line outputs SL1 to SLj and the word line block selection signals x1 'to xj' are output, but at this point of time, these signals and outputs have not been converted to the predetermined voltage value level, It remains at the logic operating voltage level.

Next, at time t3, the power supply voltages VBB, Vvr,
VSL is 0V → -9V, 3.3V → 2V, 0V, respectively
→ -9V is set, and the power supply voltage VwE is 3. at the time t4.
It is set from 3V to 0V. As a result, by time t5,
Write word line applied voltages (Vw) 1 to (Vw) i and verify read word line applied voltages (Vv) 1 to (V
v) Two types of word line applied voltages i, the selection gate line outputs SL1 to SLj, and the word line block selection signals x1 'to xj' are converted into predetermined voltage value levels.

Next, from time t5, the write voltage applying operation / verify reading operation is repeatedly switched, and the word line applied voltage switching signal φw / v becomes high level at times t5, t9, t11, and t13. The switching signal φw / v is directly converted into a predetermined voltage level by the circuit shown in FIG. 12, which will be described later, and the word line applied voltage switching signal φw / v ′ is generated. Accordingly, the write word line applied voltages (Vw) 1 to (Vw) i are switched and output as the word line outputs V1 to Vi and WL11 to WLji.

At time t6, t8, t10, t12, the word line applied voltage switching signal φw / v becomes low level, and the switching signal φw / v is directly converted to a predetermined voltage level by the circuit shown in FIG. Thus, the word line applied voltage switching signal φw / v ′ is generated. Accordingly, verify read word line applied voltages (Vv) 1 to (V are output as word line outputs V1 to Vi and WL11 to WLji.
v) i is switched and output.

Next, a concrete circuit example in the block diagram of FIG. 3 is shown in FIG. 6 for the selection gate line output section 42.
7 and 8 for the word line block selection signal section 43, FIG. 9 for the write / erase word line applied voltage output section 52, FIG. 10 for the verify read word line applied voltage output section 53, and the word line application. The voltage switching multiplexer unit 61 is shown in FIG. 11, and the word line applied voltage switching signal generation unit 62 is shown in FIG.
The word line output transfer section 7 is shown in FIG. 13 and will be described in order.

FIG. 6 is a diagram showing a specific circuit example of the select gate line output section 42. As shown in FIG. 3, the select gate line output section 42 selects the select gate line CL-SL1.
To CN-SLj, each segment corresponds to each segment, and FIG. 6 is the m-th segment.

As shown in FIG. 6, the selection gate line output unit 4
2 is an AND circuit NAN that operates at the VCC / GND level
It is composed of D1, a level shift circuit 421 operating at VSL / GND level, and an inverter INV1.

The NAND circuit NAND1 is erased (era
SE), select gate lines SLm of all word line blocks regardless of the decode signal xm from the decode section.
Is a circuit for setting to a low level.

The level shift circuit 421 is a latch type circuit for converting the decode signal xm from the decode section into a VSL / GND level voltage, and includes N type transistors TN2 and TN3 and P type transistors TP2 and TP.
It is composed of 3. In the timing chart of FIG. 5, the power supply voltage VSL is 3.3V → 1 at time t3.
The level is converted by setting it to 0V.

The inverter INV1 has a select gate line SL.
It functions as a driver circuit for driving m, and finally the decode signal xm is subjected to voltage conversion in the logic normal state and output to the select gate line SLm.

FIG. 7 and FIG. 8 are diagrams showing specific circuit examples of the word line block selection signal output section 43. The word line block selection signal section 43, as shown in FIG. 3, includes word line block selection signals CN-x1 to CN-x.
7 is the m-th segment.

As shown in FIG. 7, the word line block selection signal output section 43 includes a P-type transistor TP4 and VPP / V.
It is composed of a level shift 431 that operates at the BB level and inverters INV2 and INV3.

The P-type transistor TP4 has a power supply voltage VBB.
Is negative voltage or power supply voltage VPP is boosted, VCC / GN
This is a P-type transistor for completely separating the D system and the VPP / VBB system, and is turned off when VBB is a negative voltage or VPP is boosted by a control signal φr described later in FIG.

The level shift circuit 431 is a latch type circuit for converting the decode signal xm from the decode section into a VPP / VBB level voltage, and is an N-type transistor TN.
4, TN5, and P-type transistors TP5 and TP6.

Further, in the timing chart of FIG. 5, after the decode signal xm is latched, the level is converted by setting the power supply voltage VBB from 0V to -10V at time t3.

The inverters INV2 and INV3 function as a driver circuit for driving the word line block selection signals xm 'and / xm', and finally, the decode signal xm is voltage-converted in the logic normal state to be word line-converted. The voltage is converted as the block selection signal xm ′ and is output in the logic inverted state as the word line block selection signal / xm ′.

FIG. 8 shows the separation P-type transistor T of FIG.
P4 is a circuit that generates a control signal φr for turning off P4 when the power supply voltage VBB is a negative voltage or when the power supply voltage VPP is boosted, and includes an N-type transistor TN6 and a high resistance element R1,
And inverter INV that operates at VPP / GND level
It is composed of four.

The N-type transistor TN6 is normally in the off state, and is turned on only when the power supply voltage VBB is a negative voltage, biasing the input node of the inverter INV4 to the VBB level. The high resistance element R1 is specifically a pull-up resistor having a resistance value in a unit of ~ MΩ, and has a power supply voltage VBB.
When the input node of the inverter INV4 is V
Bias to CC level.

Inverter INV4 functions as a driver circuit for driving control signal φr operating at VPP / GND level, and the logical threshold voltage is set at VPP / 2 level. Therefore, it normally goes to the GND level and turns on the P-type transistor TP4.
VPP only when BB is negative voltage or power supply voltage VPP is boosted
The level is turned on and the P-type transistor TP4 is turned off.

FIG. 9 is a diagram showing a specific circuit example of the write / erase word line applied voltage output section 52.
The write / erase word line applied voltage output unit 52, as shown in FIG.
It is composed of each segment corresponding to each of (Vw) 1 to CN- (Vw) i, and FIG. 9 is the nth segment.

As shown in FIG. 9, the write / erase word line applied voltage output unit 52 includes a NAND circuit NAND2 which operates at the VCC / GND level, a P-type transistor TP7, and V.
a level shift circuit 521 that operates at the wE / VBB level,
And an inverter INV5.

The NAND circuit NAND2 is erased (era
SE) is a circuit for setting the erase word line applied voltage (Vw) n of all the word lines in the selected word line block to a high level regardless of the decode signal xn from the decoding unit. The P-type transistor TP7 is
This is a P-type transistor for completely separating the VCC / GND system and the VwE / VBB system when the power supply voltage VBB is a negative voltage or when the power supply voltage VPP is boosted, and VBB is controlled by the control signal φr described in FIG. It turns off when the voltage is negative or when VPP is boosted.

The level shift circuit 521 is a latch type circuit for converting the decode signal xn from the decode section into a VwE / VBB level voltage, and is an N-type transistor T.
N7, TN8, and P-type transistors TP8, TP9
It is composed by. Further, in the timing chart of FIG. 5, after the decode signal xn is latched, time t3
The level conversion is performed by setting the power supply voltage VBB at 0V → −10V and at time t4 by setting the power supply voltage VwE at 3.3V → 0V.

The inverter INV5 functions as a driver circuit for driving the write / erase word line applied voltage (Vw) n, and finally the decode signal xn is at a high level at the time of erasing and logically inverted at the time of the write voltage applying operation. The voltage is converted in the state and output as the write / erase word line applied voltage (Vw) n.

FIG. 10 is a diagram showing a specific circuit example of the verify read word line applied voltage output unit 53. Verify read word line applied voltage output unit 53
Is composed of segments corresponding to the verify read word line applied voltages CN- (Vv) 1 to CN- (Vv) i, respectively, as shown in FIG.
Is the nth segment.

As shown in FIG. 10, the verify read word line applied voltage output unit 53 is composed of a level shift circuit 531 operating at the Vvr / GND level and an inverter INV6.

The level shift circuit 531 is an inverter type circuit for converting the decode signal xn from the decode section into a voltage level Vvr / GND, and is composed of an N-type transistor TN9 and a P-type transistor TP10. Further, in the timing chart of FIG. 5, level conversion is performed by setting the power supply voltage Vvr to 3.3V → 2V at time t3.

The inverter INV6 functions as a driver circuit for driving the verify read word line applied voltage (Vv) n, and finally the decode signal xn.
Is voltage-converted in the logic normal state and output as the verify read word line applied voltage (Vv) n.

FIG. 11 is a diagram showing a specific circuit example of the word line applied voltage switching multiplexer unit 61. Word line applied voltage switching multiplexer unit 61
Is the multiplexer MPX1 to MPX as shown in FIG.
It is composed of each segment corresponding to each word line applied voltage of Xi, and FIG. 11 corresponds to the nth segment.

As shown in FIG. 11, the word line applied voltage switching multiplexer unit 61 is composed of a switch 611 and a switch 612. Switch 61
Is an analog switch circuit composed of an N-type transistor TN10 and a P-type transistor TP11, which is turned on when the word line applied voltage switching signal φw / v ′ is at a high level, and the write / erase word line applied voltage (Vw ) N is input and is output as a word line output Vn. Further, in the timing chart of FIG.
At times t5, t7, t9, t11, and t13, the switch 6
Switched to 11.

The switch 612 is an N-type transistor TN.
11 and a P-type transistor TP12, which is an analog switch circuit that is turned on when the word line applied voltage switching signal φw / v ′ is at a low level,
The verify read word line applied voltage (Vw) n is input and output as the word line output Vn. Further, in the timing chart of FIG. 5, times t6, t8, t1
The switch 612 is switched at 0 and t12.

FIG. 12 is a diagram showing a specific circuit example of the word line applied voltage switching signal generator 62.
In FIG. 12, a word line applied voltage switching signal generator 62 is a NAND circuit NA that operates at the VCC / GND level.
ND3, NAND4, level shift circuit 621 operating at VPP / GND level, inverter INV7, VPP / V
It is composed of a level shift circuit 622 that operates at the BB level and inverters INV8 and INV9.

The word line applied voltage switching signal generator 62 shown in FIG. 12 has a control signal φw / at the Vcc / GND level.
This is a voltage conversion circuit for generating a word line applied voltage switching signal φw / v ′ of VPP / VBB level by performing voltage conversion of v in two stages. First, the voltage conversion in the first stage causes Vcc
/ GND level to VPP / GND level, and then VPP / GND level to VPP by the second stage voltage conversion.
/ VBB level voltage conversion.

In the timing chart of FIG. 5, these series of voltage conversions are performed at times t5, t7, t9, t1.
At 1 and t13, the control signal φw / v changes from the low level to the high level, and at times t6, t8, t10, t12, and t14, the control signal φw / v changes from the high level to the low level. It is necessary to convert the voltage to. In the timing chart of FIG. 5, the setting of the power supply voltages VPP and VBB is completed by the time t4, so that the voltage conversion can be performed at high speed.

The NAND circuit NAND3 erases (eras)
At the time of E), it is a circuit for setting the word line applied voltage switching signal φw / v ′ to a high level regardless of the control signal φw / v. The NAND circuit NAND4 is irrelevant to the control signal φw / v during the read operation (READ).
This is a circuit for setting the word line applied voltage switching signal φw / v ′ to a low level.

The level shift circuit 621 controls the control signal φw.
/ V is a latch type circuit for converting the voltage to VPP / GND level, and includes N-type transistors TN12, TN13,
And P-type transistors TP13 and TP14. The level shift circuit 622 includes an inverter I
It is a latch type circuit for converting the output stage of the NV7 to the VPP / VBB level, and includes an N-type transistor TN14,
TN15 and P-type transistors TP15 and TP16
It is composed of

The inverter INV7 functions as a driver circuit for driving the output stage of the level shift circuit 621. The inverters INV8 and INV9 finally function as a driver circuit for driving the word line applied voltage switching signal φw / v ′, and the control signal φw /
v is voltage-converted in the logic normal state and is output as a signal φw / v ′, and is voltage-converted in the logic inversion state and output as a signal / φw / v ′.

FIG. 13 is a diagram showing a specific circuit example of the word line output transmission unit 7. As shown in FIG. 13, the word line output transfer section 7 includes word lines SW11 to SWij.
It is composed of each segment corresponding to each of,
FIG. 13 shows a segment corresponding to the nth word line in the mth word line block.

As shown in FIG. 13, the word line output transfer section 7 includes a switch 701 and an N-type transistor TN1.
It is composed of 7. The switch 701 is an analog switch circuit composed of an N-type transistor TN16 and a P-type transistor TP17, and is turned on when the word line block selection signal xm ′ is at high level, and each word in the selected word line block is turned on. The word line output Vn is output to the word line WLmn.
The N-type transistor TN17 is turned on when the word line block selection signal xm 'is at a low level, and biases each word line in the block to 0V when the word line block is not selected.

As described above in detail, the first aspect of the present invention
In the DINOR type flash memory of the above embodiment, the write voltage application operation and the verify read operation can be switched in a short time, and the write operation can be performed at high speed.

14 and 15 show a second embodiment of the present invention.
FIG. 6 is a diagram showing a bias example of an erase voltage application operation and a BayFy read operation of the NOR flash memory according to the embodiment of FIG. The bias example of the erase voltage application operation shown in FIG. 14 is the same as the case of the word line sector erase in the conventional example shown in FIG. The bias example of the verify read operation shown in FIG. 15 is the same as the case of word line sector erase in the conventional example shown in FIG.

FIG. 16 is a semiconductor nonvolatile memory device of the present invention for realizing the erase voltage applying operation and the verify read operation as shown in FIGS. 14 and 15, especially the second embodiment.
3 is a block diagram of a main part centering on a row decoder of the NOR flash memory that is the embodiment of FIG. 16 is different from the block diagram of the DINOR type flash memory according to the first embodiment shown in FIG. 3 in that select gate lines SL1 ...
SLj, the selection transistor, and the selection gate line output section are not required, and the others are the same as the configuration of the block diagram of FIG.

FIG. 17 shows that when the voltage value level of each power supply terminal in FIG. 16 is the erase voltage application operation and the verify read operation of the NOR flash memory of the present invention,
There are four types of operation modes, write operation and read operation.
It is a figure which shows what kind of voltage value is set, respectively.

A particularly important point in the table shown in FIG. 17 is that the voltage value level of each power supply terminal is set to the same level in two kinds of operation modes, that is, the erase voltage applying operation and the verify read operation. This means that it is not necessary to repeatedly reset the voltage setting of each power supply terminal when repeatedly switching the operation mode of each type. This is significantly different from the operation of the conventional NOR flash memory.

That is, as shown in FIG. 17, VCC, G
Since ND is a voltage level for normal logic operation, it is set to 5V and 0V regardless of the operation mode. V
PP is set to 5V during the erase voltage application operation and the verify read operation, 12V during the write operation, and 5V during the read operation. VBB is set to -10V during the erase voltage application operation and the verify read operation, and to 0V during the write operation and the read operation. VwE is 0 during erase voltage application operation and verify read operation
V is set to 12V during a write operation and 5V during a read operation. Vvr is set to 3V during the erase voltage application operation and the verify read operation, and is set to 5V during the write operation and the read operation.

Setting of the power supply terminals in the block diagram of FIG. 16 and the various operation modes of FIG. 17 is performed by alternately repeating the write voltage application operation or the erase voltage application operation and the verify read operation, except for the distinction between the write operation and the erase operation. This is exactly the same in that, when performing, a predetermined negative voltage and a predetermined positive voltage are alternately switched and output to the selected word line. Therefore, it is possible to switch between the erase voltage application operation and the verify read operation in a short time, as in the case of the DINOR flash memory according to the first embodiment, and thus the erase operation can be performed at high speed. It is possible to do.

[0113]

As described above, according to the semiconductor nonvolatile memory device of the present invention, the switching between the write voltage application operation or the erase voltage application operation and the verify read operation can be performed in a short time, which in turn speeds up. A write or erase operation can be performed.

[Brief description of drawings]

FIG. 1 is a diagram showing a bias example of a write voltage application operation of a DINOR type flash memory according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a bias example of a verify read operation of the DINOR type flash memory according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a main part centering on a row decoder of the DINOR type flash memory according to the first embodiment.

FIG. 4 shows that the voltage value level of each power supply terminal of the DINOR type flash memory according to the first embodiment has an erase operation, a write voltage application operation, a verify read operation,
It is a figure which shows what kind of voltage value is set in each of four types of operation modes of read-out operation.

FIG. 5 is a timing chart showing how various signals and outputs change voltage when the write voltage application operation / verify read operation is repeatedly switched in the DINOR flash memory according to the first embodiment. .

FIG. 6 is a diagram showing a specific circuit example of a select gate line output section according to the present invention.

FIG. 7 is a diagram showing a specific circuit example of a word line block selection signal output section according to the present invention.

FIG. 8 is a diagram showing a specific circuit example for generating a control signal φr according to the present invention.

FIG. 9 is a diagram showing a specific circuit example of a write / erase word line applied voltage output unit according to the present invention.

FIG. 10 is a diagram showing a specific circuit example of a verify read word line applied voltage output unit according to the present invention.

FIG. 11 is a diagram showing a specific circuit example of a word line applied voltage switching multiplexer unit according to the present invention.

FIG. 12 is a diagram showing a specific circuit example of a word line applied voltage switching signal generator according to the present invention.

FIG. 13 is a diagram showing a specific circuit example of a word line output transmission unit according to the present invention.

FIG. 14 is a diagram showing a bias example of an erase voltage application operation of the NOR flash memory according to the second embodiment of the present invention.

FIG. 15 is a diagram showing a bias example of the verify read operation of the NOR flash memory according to the second embodiment of the present invention.

FIG. 16 is a block diagram of a main part centering on a row decoder of a NOR flash memory according to a second embodiment.

FIG. 17 shows how the voltage value level of each power supply terminal of the NOR flash memory according to the second embodiment is different in four kinds of operation modes of erase voltage application operation, verify read operation, write operation, and read operation. It is a figure which shows whether it is set to a voltage value.

FIG. 18 is a diagram showing a bias during an erase operation of a DINOR type flash memory.

FIG. 19 is a diagram showing a bias during a write voltage application operation of a DINOR type flash memory.

FIG. 20 is a diagram showing a bias during a verify read operation of a DINOR flash memory.

FIG. 21 is a diagram showing a bias during a read operation of a DINOR type flash memory.

FIG. 22 is a diagram summarizing various operations of the DINOR flash memory.

FIG. 23 is a diagram showing a bias during an erase voltage application operation in word line sector erase of a NOR flash memory.

FIG. 24 is a diagram showing a bias at the time of a BABY read operation of the NOR flash memory.

FIG. 25 is a diagram showing a bias during a write operation of a NOR flash memory.

FIG. 26 is a diagram showing a bias during a read operation of the NOR flash memory.

FIG. 27 is a diagram summarizing various operations of the NOR flash memory.

FIG. 28 is a circuit diagram showing a bias state of a selected word line driver in a write voltage application operation of a DINOR type flash memory.

FIG. 29 is a circuit diagram showing a bias state of a selected word line driver in a verify read operation of a DINOR type flash memory.

30 is a diagram showing a bias state of the N-type transistor TN1 which is particularly problematic in the bias state of the word line driver of FIG. 28.

31 is a diagram showing a bias state of the N-type transistor TN1 which is particularly problematic in the bias state of the word line driver of FIG. 29. FIG.

FIG. 32 is a timing chart of the output voltage value level of the selected word line in the write operation / verify read operation of the DINOR flash memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory array part 2 ... Read / write circuit 3 ... Column decoder 4 ... Main row decoder 41 ... Main row decoder (decoding part) 42 ... Select gate line output part 43 ... Word line block selection signal output part 5 ... Sub row decoder 51 ... Sub row decoder (decoding section) 52 ... Write / erase word line applied voltage output 53 ... Verify read word line applied voltage output 6 ... Word line applied voltage switching section 61 ... Word line applied voltage switching multiplexer section 62 ... Word line applied voltage switching X (sub row decoder) inputs X1 to Xb ... X (main row decoder) inputs Y1 to Xy ... Y (column) inputs WL11 to WLji ... Word lines SL1 to SLj ... Select gate lines B1 to Bk ... Bit lines x1 to xj ... Decode signal (main row decoder) x1 ' ... xj '... Word line block selection signals x1 to xi ... Decode signals (sub row decoder) (Vw) 1 to (Vw) i ... Write / erase word line applied voltage (Vv) 1 to (Vv) i ... Verify read word line Applied voltage φw / v '... Word line applied voltage switching signals V1 to Vi ... Word line output

Continuation of front page (56) Reference JP-A-5-258580 (JP, A) JP-A-5-81887 (JP, A) JP-A-6-124597 (JP, A) JP-A-3-14272 (JP , A) JP 6-77437 (JP, A) JP 6-68690 (JP, A) JP 5-128878 (JP, A) JP 5-210991 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 16/00-16/34

Claims (10)

(57) [Claims] 1. A data write operation or an erase operation for a memory cell includes a write voltage application operation or an erase voltage application operation for applying a predetermined voltage for writing or erasing data and a data write operation for the memory cell. Alternatively, in a semiconductor nonvolatile memory device which is performed by alternately repeating a verify read operation for detecting whether or not erasing is completed, the semiconductor nonvolatile memory device is characterized in that each word line block including a plurality of word lines is characterized.
Main row decoder that selects a fixed word line block
And the word line block selected by the main row decoder above.
Specified write voltage for each word line in the
Pressure or applied erase voltage and verify read voltage
Sub-rows that can output word line applied voltages in parallel at the same time
Decoder and application of the two types of word lines from the sub row decoder
Either one of the
The word line mark that is selectively switched according to the output operation
Selected output by the applied voltage switching unit and the word line applied voltage switching unit
Either one of the above two types of word line applied voltage
The voltage applied to the source line is selected by the main row decoder above.
Output to each word line in the word line block
And a word line output transmission section for performing the operation . 2. A bit line is hierarchized into a main bit line and a sub bit line, the main bit line and the sub bit line are selectively connected according to the operation, and a plurality of memory cells are provided in the sub bit line. The semiconductor nonvolatile memory device according to claim 1, which is connected in parallel. 3. The semiconductor nonvolatile memory device according to claim 1, wherein memory cells arranged in a matrix are connected to a plurality of word lines and bit lines. 4. The main row decoder decodes at least one row address input signal operating at a logic operating voltage level, and whether or not the word line block should be selected for each word line block. And a decode circuit for outputting a decode signal for controlling each of the above-mentioned decode signals, and the operation voltage level of each of the decode signals is converted from a logical operation voltage level to a predetermined voltage value level and a word line block is provided for each word line block. The semiconductor nonvolatile memory device according to claim 1, further comprising a voltage conversion circuit that generates a selection signal. 5. The sub-row decoder decodes at least one row address input signal operating at a logic operation voltage level, and whether the word line should be selected for each word line in a word line block. A decode circuit for outputting a decode signal for controlling whether or not, and a write operation for converting the operation voltage level of each of the above-mentioned decode signals from a logic operation voltage level to a predetermined voltage value level and applying it to each word line. A first voltage conversion circuit that generates a voltage or an applied erase voltage, and converts the operation voltage level of each of the decode signals from a logical operation voltage level to a predetermined voltage value level and applies it to each word line. 2. A second voltage conversion circuit for generating a verify read voltage.
The semiconductor nonvolatile memory device described. 6. The operation of a control signal for controlling whether the word line applied voltage switching unit should perform a write voltage application operation or an erase voltage application operation or a verify read operation according to a data write operation or an erase operation. A voltage conversion circuit for converting a voltage level from a logical operation voltage level to a predetermined voltage value level to generate a word line applied voltage switching signal, and a voltage conversion circuit provided corresponding to each word line forming a word line block A multiplexer circuit which receives at least two inputs and selects one output, wherein two input terminals are respectively connected to two types of word line applied voltage supply lines from the sub row decoder, and the word line applied voltage switching signal is received. 2. The semiconductor circuit according to claim 1, further comprising a multiplexer circuit that outputs a voltage applied to either one of the word lines. Non-volatile storage device. 7. The word line output transmission section is a switch formed of a semiconductor element provided corresponding to each word line, and one terminal has the word line applied voltage to which the word line corresponds. The switch of the word line block selected by receiving the word line block selection signal is connected to the supply line of the word line applied voltage selectively output by the switching unit, and the other terminals are connected to the word lines in the memory array, respectively. The semiconductor nonvolatile memory device according to claim 1, further comprising a switch circuit in which only the switch is connected and the other switches are disconnected. 8. A word line block selection signal from the main row decoder and two kinds of word line application voltages, an applied write voltage or an applied erase voltage and a verify read voltage, applied to each word line from the sub row decoder, 2. A fixed voltage value for each of the data write operation period and the erase operation period.
The semiconductor nonvolatile memory device described. 9. The word line block selection signal and the word line applied voltage switching signal are applied to each of a predetermined applied write voltage or applied erase voltage and verify read voltage output from the sub row decoder. 2. The semiconductor nonvolatile memory device according to claim 1, wherein the voltage value on the low voltage side is equal to or less than the voltage value, and the voltage value on the high voltage side is equal to or more than the voltage value. 10. The semiconductor nonvolatile memory device according to claim 9, wherein the low-voltage side voltage value is a predetermined negative voltage, and the high-voltage side voltage value is a predetermined positive voltage.