JP3509787B2 - TTI mismatch detection circuit and method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trail trace termination circuit for a backbone transmission device.

[0002]

[Prior Art] ITU-T Recommendation G.707 Page.6
7 defines the format of the J0 byte for section trace in SDH (Synchronous Digital Hierarchy), and it is stated that the J0 byte has a 1-byte or 16-multiframe structure.

Also, ITU-T Recommendation G.806 Page.
In 34, it is stated that the J0 byte value received at the section trace termination point is compared with the J0 expected value, a mismatch is detected and a TIM alarm is issued.

[0004]

In these prior arts, the section trace is performed only in a certain specific section, and the J0 byte is also a 1-byte or 16-multiframe structure. It wasn't that big.

However, it is defined in G.709 of ITU-T
The TTI byte has a maximum of 8 sections (8 layers), and since it has a structure of 64 multi-frames, each layer is provided with a register that stores the expected value and the received value of the TTI to detect the mismatch of the TTI and collate. Therefore, there is a problem that the capacity of the register becomes large.

The present invention has been made in view of these problems, and has a circuit configuration in which the capacity of the expected value register is small.
It is an object of the present invention to provide a circuit for detecting the mismatch of the.

[0007]

According to a first aspect of the present invention, ITU-T Recommendation G. 709, SM (Section Monitoring), TCM (T
andem Connection Monitoring), PM (Path Monitorin
In the mismatch detection circuit of the TTI (Trail Trace Identifier) value in g), the circuit is
A means for receiving and storing bytes, the circuit for collating expected values of the TTI bytes of the plurality of layers, and a means for receiving a single DAPI (Destination Access Point) in a multi-frame common to each of the plurality of layers. Identifie
r) means for receiving and storing expected values and said stored DAP
I means for referring to expected values from each layer, means for receiving and storing expected values other than the DAPI, and the stored DAPI
MFAS (Multi Frame Alig
and a means for selecting according to the value of the Nment Signal), and comparing the DAPI received values of a plurality of layers with a single DAPI expected value.

According to a second aspect of the present invention, ITU-T Recommendation G. 709, SM (Section Monitoring) and TCM (Tandem Connection) defined in the Recommendation.
Monitoring), TTI (Trail in PM (Path Monitoring)
Trace Identifier) value mismatch detection method, the method receiving and storing TTI bytes of the plurality of layers;
Collating expected values of I bytes, receiving and storing a single DAPI (Destination Access Point Identifier) expected value in a multi-frame common to each of the plurality of layers in the step, and the stored DAPI
Referring to the expected value from each layer, receiving and storing the expected value other than the DAPI, and storing the expected value other than the stored DAPI and the DAPI expected value in the MFAS (Multi Frame
e Alignment Signal) value selected step,
A TTI mismatch detection method is provided which is characterized by comparing DAPI reception values of multiple layers with a single DAPI expected value.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIG. 3 showing a circuit configuration of the present invention.

FIG. 3 shows an expected value collation circuit for eight layers of TTI bytes.

The TTI byte reception value register section a is composed of a register having a capacity of 64 bytes for each layer in order to store a TTI byte reception value of 64 multiframe structure.

The DAPI expected value register section b is composed of a register having a capacity of 16 bytes for storing the DAPI value at the TTI byte receiving point.

The expected value register section c other than the DAPI value is composed of a register having a capacity of 48 bytes for each layer in order to store the SAPI value and an arbitrary value set by the network administrator.

The selector d selects the expected value supplied from the DAPI value register section b and the expected value supplied from the expected value memory section c other than DAPI according to the MFAS value, and sends it to the expected value matching section e. Supply.

The expected value matching unit e performs expected value matching based on the received value supplied from the received value register unit a and the expected value supplied from the selector d, and issues a TIM alarm when the matching does not match. .

The operation of the circuit of FIG. 3 in the embodiment of the present invention will be described with reference to FIG.

When the TTI byte values of SM, TCM1-6, and PM are input to the mismatch matching circuit of the present invention, the TTI byte received value of each layer is synchronized with the MFAS value. Therefore, the MFAS value is used as an address for each layer. Is written to the 64-byte received value register a.

Next, when the expected value is set, the DAPI value at the receiving point where the expected value matching of the TTI byte is performed is common to all layers, so the DAPI expected value register section having a capacity of 16 bytes is provided. Written to b.

At this time, the MFAS value is used as an address and the MFAS
When the value is 15 to 31, it is written to the register address 1 to 16.

Further, expected values other than DAPI values, that is, SAPI
Since the value and the arbitrary value set by the network administrator are different in each layer, they are written in the expected value register part c other than DAPI of each layer having a capacity of 48 bytes.

At this time, using the MFAS value as an address, the MFAS
When the value is 0 to 15, register address 1 to 16
When the value is 32 to 63, it is written to register address 17 to 48.

In the selector d, when the MFAS value indicates 0 to 15 and 32 to 63, the value stored in the expected value register c other than DAPI is selected as the expected value, and the MFAS
When the value shows 16 to 31, the DAPI expected value register part
The value stored in b is selected as the expected value, and the expected value of a total of 64 bytes is supplied to the expected value matching unit e.

In the expected value collating section e, the received value supplied from the received value register section a is collated with the expected value supplied from the selector d, and a TIM alarm is issued if the collation does not match.

In the SONET / SDH section trace using the J0 byte and the path trace using the J1 byte, a fixed pattern signal is repeatedly transmitted using the J0 / J1 byte, and the receiving side expects the received value. TIM (Trace Identifier Mismatch)
match) alarm to check if the connection with the sender is still alive, i.e. section layer,
Alternatively, the continuity of the pass layer can be confirmed.

OTH (Op (Op) defined in ITU-T G.709
In the same way as SONET / SDH, the TTI (Trail Trac
e Identifier) bytes are defined.

The trail trace realizes a trace function equivalent to a section trace and a path trace in SONET / SDH.

That is, the transmitting device repeatedly transmits a fixed pattern signal, and the receiving device is used to confirm that the expected connection with the transmitting device is established.

FIG. 1 shows a multi-frame structure of TTI bytes in OTH.

Bytes 0 to 15 in FIG. 1 are SAPI (Sou
rce Access Point Identifier) value, which is a unique value of the access point identifier of the point transmitting the TTI byte, and is a fixed value that does not change as long as that point exists.

The 16th byte to the 31st byte are DAPI (Destina
access point identifier) value, which is a unique value of the access point identifier of the point that receives the TTI byte, that is, the expected value matching, and is a fixed value that does not change as long as that point exists. The 32nd to 63rd bytes are values that can be arbitrarily set by the network administrator.

In OTH, OTU (Optical Channel Tra
nsport Unit) Section layer, ODUk (Optical Channel Da)
ta Unit-k) Tandem Connection 1 to 6 layers and ODUkPath layer are supported for CM (Connection Monitoring) of 8 layers in total, and SM (Section M
onitoring), TCM (Tandem Connection Monitoring) 1-6
There are 8 TTI bytes in total for PM (Path Monitoring).

FIG. 2 shows an example of the network management section.

At the D2C2B2 point in FIG. 2, T of TCM1, 2, 3
The TI byte is terminated.

The DAPI value at this time is a unique value of the D2C2B2 point, and is common to TCM1, 2, and 3.

In this example, it is necessary to match the expected value of the TTI byte of 3 layers, but it is necessary to match the expected value of the TTI byte of 8 layers depending on the configuration of the network management section.

When performing expected value matching in all layers, a received value and expected value register having a maximum capacity of 64 × 8 = 512 bytes is required.

Therefore, FIG. 3 shows a configuration in which the registers required for the expected value comparison can be reduced when the trail tracing in OTH is performed.

[0038]

The effect of the present invention is that the conventional method is achieved by sharing the DAPI expected value in each layer in the circuit for performing the OTH trail trace expected value matching.
Where a 1024-byte register is required, this method requires 912
A byte register is required, and the number of registers required in the circuit can be reduced by 11%.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a multi-frame of TTI bytes in OTH according to the present invention.

FIG. 2 is a configuration diagram showing a network management section in the present invention.

FIG. 3 is a block diagram showing a circuit configuration according to the present invention.

FIG. 4 is a sequence diagram showing the operation of the circuit according to the present invention.

[Explanation of symbols]

a Received value register group bDAPI expected value register Expected value register section other than cDAPI d selector eExpected value collation group

Claims (2)

(57) [Claims] 1. The ITU-T Recommendation G. 709 regarding SM (Section Monitorin) defined in the recommendation.
g), TCM (Tandem Connection Monitoring), PM (Pa
TTI (Trail Trace Identifie) in th Monitoring
r) In the value mismatch detection circuit, the circuit is means for receiving and storing the TTI bytes of the plurality of layers, the circuit is a means for collating the expected value of the TTI bytes of the plurality of layers, in the means, A single DAPI (Destination Access Point Id) in a multi-frame that is common to multiple layers
entifier) means for receiving and storing expected values, means for referring to the stored DAPI expected values from each layer, means for receiving and storing expected values other than the DAPI, and expectations other than the stored DAPI Value and DAPI expected value MFAS
A TTI mismatch detection circuit that is equipped with a means to select by the value of (Multi Frame Alignment Signal), and compares the DAPI received values of multiple layers with a single DAPI expected value. 2. G. Recommendation ITU-T. 709 regarding SM (Section Monitorin) defined in the recommendation.
g), TCM (Tandem Connection Monitoring), PM (Pa
TTI (Trail Trace Identifie) in th Monitoring
r) In the value mismatch detection method, the method includes receiving and storing the TTI bytes of the plurality of layers, the method matching the expected value of the TTI bytes of the plurality of layers, in the step, Single DAPI (Destination Access Point) in a multi-frame that is common to each layer
Identifier) receiving and storing an expected value, referring to the stored DAPI expected value from each layer, receiving and storing an expected value other than the DAPI, and expecting other than the stored DAPI Value and DAPI expected value MFAS
A TTI mismatch detection method characterized by comprising the step of selecting according to the value of (Multi Frame Alignment Signal), and comparing the DAPI received values of multiple layers with a single DAPI expected value.