JP3507785B2 - S / T point receiving method and receiving circuit for ISDN line termination device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an S / T point reception signal sampling circuit and a reception signal sampling method in an ISDN digital line terminal device.

[0002]

2. Description of the Related Art ISDN has a merit in that it can provide a wide variety of services on a single subscriber line. For this reason, an interface applicable to multiple purposes is defined, and a user / network interface which is a demarcation point between a terminal and a telecommunication line facility is one of them. ISDN basic user / network interface ISDN digital line terminal (D
FIG. 4 shows an example of a wiring configuration in which the SU) and a plurality of terminals (TE) are connected by a short distance passive (short passive) bus wiring. DSU in conventional S / T point bus wiring on the terminal side
In the receiving circuit of, the reception discrimination between the terminal connected to the near-end side and the terminal connected to the far-end side considers the maximum phase difference between the near-end and far-end received signals, and the sampling points are located at positions where no deviation occurs. Is fixedly set by a fixed sampling method. This short passive connection has a maximum extension of 20
Guaranteed up to 0m. In recent years, indoor wiring has come to form a wide variety of networks, and the crosstalk power from it has become a disturbance source for bus wiring. Further, since the signal level from the far-end terminal is low, the influence of the induced noise at the S / T point is large, which improves the reception characteristic of the data signal from the terminal connected to the far-end of the bus wiring. Measures are required.

In the ISDN basic interface, two B channels (64 Kbps) and one D channel (1
In order to provide an interface structure of 6 Kbps, a bit stream of 192 Kbps is defined by adding bits for frame synchronization, control and maintenance. D
One frame transmitted / received between SU and TE has a 48-bit structure. FIG. 5 shows the configuration of the first half of the reception frame received by the DSU from the TE. FIG. 5A shows a signal frame from the near-end terminal and FIG. 5B shows a signal frame from the far-end, and there is a phase difference of about 4 μs between them. Each B
In each channel and each D-bit data bit, there are arranged a total of two L-bits, namely an F-bit for synchronization, a pair of 1-bit, and a 1-bit arranged at the end of the frame. The L bit is a DC balanced bit for removing the DC component on the interface. A pseudo ternary code is used as the transmission code, and code violation (also called bipolar violation) is applied to the F bit and L bit to make the polar arrangement unique for frame synchronization. . Transmission signal from near-end terminal Figure 5
(A) and the transmission signal (B) from the far-end terminal are combined on the bus wiring to be as shown in (C). Therefore, in the signals transmitted from the near-end terminal and the far-end terminal, bits adjacent to each other overlap each other.

In the receiving circuit of the DSU, fixed sampling is normally performed by detecting the change point of the F bit of the received frame as described above. FIG. 6 shows an example of a conventional received signal sampling circuit section. F-bit change point detection is performed by the violation detection unit 13 and the F-bit phase detection unit 15, and a 2-bit offset is added and fixed in the reception timing delay circuit 17 based on the frame of the receiving end terminal. Typical sampling points are generated and the data of each B1 channel and B2 channel is extracted. This fixed sampling is performed at a position where signals of the near-end side terminal and the far-end side terminal overlap, that is, a 1 μs width after one pulse (see FIG. 5).
The white part (C) of the signal waveform is sampled. However, even if the sampling point is fixed to the phase of the terminal at the near end depending on the connection position of the bus to which the terminal is connected, the received signal from the terminal connected to the actual bus has a phase difference in the data channel at the far end. Therefore, the time width for normal data extraction is narrowed and the sampling point margin (time margin) is small. Further, the signal train of the terminal connected to the far end side of the bus line has a low signal amplitude due to the attenuation in the bus line and is easily affected by noise. Therefore, the reception characteristic of the data signal from the terminal connected to the far end of the bus line is not necessarily good.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the conventional receiver circuit of the ISDN digital line terminal device having the short-distance passive bus wiring. Even when the data channels of each terminal have a phase difference and the signals from each terminal are combined on the bus wiring, the channel used by one terminal does not have the signal of the other terminal. It is an object of the present invention to improve the signal noise resistance of the terminal connected to the far end side by making the best use of the far end side terminal phase and fixedly adjusting the sampling point for each channel of B1 and B2.

[0006]

According to a first aspect of the present invention, a method for receiving an S / T point of an ISDN line terminating device according to the invention is short in that a plurality of terminals are connected from the near end side to the far end side. Transmission signal from the near-end side terminal at the terminal-side S / T point of the ISDN line termination device having the distance passive bus wiring
And a signal transmitted from the far-end side terminal on the bus wiring
A method of receiving a bus wiring reception signal which is a signal synthesized by the method, wherein the phase of the transmission signal of a terminal connected to the near end side of the line termination device of the bus wiring is included in the bus wiring reception signal. Detecting from the bit change point, the phase of the transmission signal of the terminal connected to the far end side of the bus line from the line terminating device is detected from the L bit change point included in the bus line receive signal, Transmission data of the near-end side terminal and the far-end side terminal is extracted from the bus wiring reception signal by two sampling signals having different phases generated based on the timing of the bit change point and the timing of the L bit change point. It is characterized by The S / T point receiving circuit of the ISDN line terminating device according to the second aspect of the present invention includes a plurality of S / T point receiving circuits from the near end side to the far end side.
ISDN with short-distance passive bus wiring to which terminals are connected
The near-end side end at the terminal side S / T point of the line terminating device
A transmission signal from the end, and a transmission signal from the far-end side terminal
Is a signal synthesized on the bus wiring
A signal receiving circuit, which detects a phase of a transmission signal of a terminal connected to a side closer to the line terminating device of the bus wiring, from a change point of an F bit included in the bus wiring receiving signal; Means for detecting the phase of the transmission signal of the terminal connected to the far end side of the bus line from the line terminating device from the change point of the L bit included in the received signal of the bus line, and the timing of the change point of the F bit. Means for extracting transmission data of the near-end side terminal from the bus wiring reception signal by a first sampling signal generated based on the above; and the first sampling signal generated based on the timing of the change point of the L bit. Second phase with different phase
And a means for extracting transmission data of the far-end side terminal from the bus wiring reception signal according to the sampling signal. Further, the S / T point receiving circuit of the ISDN line termination device according to the invention according to claim 3 of the present invention extracts the transmission data of the near-end side terminal from the bus wiring reception signal according to the invention according to claim 2. The extracting means generates a clock signal having a phase based on the timing of the change point of the F bit, and the two B's in which the transmission data of the near-end side terminal and the far-end side terminal are included in the bus wiring reception signal. Channel identification means for identifying which of the channels is inserted, a signal of the identified signal, a signal of the timing of the F-bit change point, and a clock signal having a phase based on the timing of the F-bit change point. And a means for extracting transmission data of the near-end side terminal from the bus line reception signal. Further, the IS according to the invention according to claim 4 of the present invention
The S / T point receiving circuit of the DN line terminating device is the above-mentioned claim 2.
And a means for extracting transmission data from the far-end side terminal from the bus wiring reception signal according to the invention related to the invention, and means for generating a clock signal having a phase based on the timing of the change point of the L bit; Channel identification means for identifying which channel of the two B channels included in the bus wiring reception signal the transmission data of the remote side terminal and the far end side terminal is inserted, and a change point of the identified signal and the L bit. It is characterized by further comprising means for extracting transmission data of the far-end side terminal from the bus wiring reception signal by a timing signal and a clock signal having a phase based on the timing of the change point of the L bit. Further, in the S / T point receiving circuit of the ISDN line termination device according to the invention according to claim 5 of the present invention, the channel identifying means according to the invention according to claims 3 and 4 is configured by a pseudo ternary code. Which of the two B channels included in the bus line reception signal the transmission data of the near-end side terminal and the far-end side terminal is inserted by detecting the time width of the L-bit negative polarity pulse It is characterized by identifying. Further, in the S / T point receiving circuit of the ISDN line terminating device according to the invention according to claim 6 of the present invention, the channel identification means according to the invention according to claims 3 and 4 is constituted by a pseudo ternary code. If the time width of the L-bit negative polarity pulse is a prescribed length, the transmission data of the far-end side terminal is inserted in the B1 channel,
If the time width of the negative polarity pulse is shorter than the specified length, it is characterized that the transmission data of the near-end side terminal is inserted into the B1 channel.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of an embodiment of a received signal sampling circuit of a DSU having a function of adjusting a sampling position for each channel of the present invention. The reception signal sampling circuit unit includes a multi-point sampling circuit unit 1 that samples a received signal sequence at multiple points at a cycle faster than the bit cycle of the signal, a violation detection unit 2 that detects a violation in a frame, An F-bit phase detection unit 4 for detecting the F-bit phase from the signal in which the violation is detected by the rotation detection unit 2;
The L-bit phase detection unit 5 for detecting the bit phase, the reference clock generation unit 6, and the F-bit phase detection change the sampling timing clock of the near-end channel from the clock signal output from the reference clock generation unit 6. The reception timing delay circuit unit A7 to be generated and the reception timing delay circuit unit B8 to variably generate the sampling timing clock of the far-end channel from the clock signal output from the reference clock generation unit 6 by detecting the L-bit phase.
A channel identification circuit 11 for identifying which of the near-end terminal and the far-end terminal has inserted data into the B1 channel and the B2 channel, and the near-end of the output of the F-bit phase detection signal and the reception timing delay circuit section A7. A hunting gate generation circuit unit A10 that generates a strobe signal for extracting the data signal sequence of the near-end channel from the channel sampling timing clock and the output of the channel identification circuit 11.
And hunting for generating a strobe signal for extracting a data signal string of the far end channel from the L bit phase detection signal, the far end channel sampling timing clock of the output of the reception timing delay circuit section B8, and the output of the channel identification circuit 11. It comprises a gate generation circuit section B9 and a frame aligner 3 for extracting the data signal strings of the near-end and far-end channels by the strobe signals output from the hunting gate generation circuit sections A and B.

Next, the operation of the received signal sampling circuit of FIG. 1 will be described with reference to FIGS. 2 and 3. 2 shows that data is inserted from the near-end terminal into the B1 channel and data from the far-end terminal into the B2 channel, and FIG. 3 shows that data is inserted into the B2 channel from the near-end terminal and from the far-end terminal into the B1 channel. The following shows the case where it is done. As shown in FIGS. 2A and 3A, the reception signal from the near-end terminal and the reception signal from the far-end terminal are combined on the bus wiring.
Therefore, in the signals transmitted from the near-end terminal and the far-end terminal, the adjacent bits overlap, and the width of normal data becomes narrow. The width of one pulse transmitted / received by the DSU is specified as 5.2 μs, and the transmission signal from the terminal connected to the near end and the transmission signal from the terminal connected to the far end are delayed by the bus wiring. Has a phase difference. The terminal phase at the nearest end is specified to be 10 μs, and the terminal phase at the farthest end is specified to be 14 μs. Normally, in order to absorb this phase difference, considering the overlap of adjacent data signal sequences due to the delay amount at the maximum line length, 1
4 μs difference between 0 μs phase pulse and 14 μs phase pulse
5.2 μ shown in white in FIG. 2A, excluding the portion
The 1 μs width after the s pulse width is sampled at multiple points. The multipoint sampling extraction circuit unit 1 multipoints the received signal sequence in the above time slot. The violation detection unit 2 detects a violation based on the sampling number. From the output of the violation detection unit 2, the F bit phase detection unit 4 and the L bit detection unit 5 detect the F bit phase and the L bit phase. The phase of the terminal at the near end is F of the F bit of the frame.
Can be detected at the change point of (+ polarity) → L (zero potential),
The phase of the terminal at the far end is L bit (potential zero) → (-polarity)
Can be detected at the change point of. The reception timing delay circuit unit A7 and the reception timing delay circuit unit B8 respectively output the clocks sent from the reference clock generation unit 6 by detecting the change points of the F bit and the L bit of the frame to the data signal sequence of the near-end side terminal. And delaying the timing clock according to the data signal sequence of the far-end side terminal (see FIG.
(E), (f) and FIGS. 3 (e), (f)) are generated. The channel identification circuit 11 identifies which of the B1 channel and the B2 channel the data of the far-end side terminal is inserted, and outputs the identification result to the hunting gate generation circuit units A and B. The hunting gate generation circuit units A and B are
The clocks generated by the reception timing delay circuits A and B, and the output of the F-bit phase detection unit 4 and the output of the L-bit phase detection unit 5 sample the data of the near-end terminal and the data of the far-end terminal, respectively. To generate a strobe signal (FIG. 2 (g) and FIG. 3 (g)).
The frame aligner 3 samples the data of the near-end terminal and the data of the far-end terminal based on the strobe signals from the hunting gate generation circuit units A and B. Here, the operation of the channel identification circuit 11 is as follows. The channel identification circuit 11 detects the width of the L bit by sampling the L bits of the combined frame to detect whether the data of the terminal on the near end side is inserted in the B1 channel or the data of the terminal on the far end side is detected. You can identify whether it has been inserted. That is, when the data of the near-end terminal is inserted into the B1 channel (FIGS. 2C and 2D), the L bits of the far-end side terminal frame received with a delay from the first bit of the B1 channel are combined. Since the L bit of the far end side terminal frame does not show a normal (-polarity) value, it is identified that the data of the near end terminal has been inserted into the B1 channel.
On the other hand, conversely, when the data of the terminal at the far end is inserted into the B1 channel (FIGS. 3C and 3D), since the first bit of the B1 channel from the near end is no data, the terminal at the far end side The L bits of the frame have a normal length, and by recognizing the normal L bit time length, it is possible to identify that the data from the far-end terminal has been inserted into the B1 channel. It

[0009]

As described above, in the reception sampling circuit section of the ISDN line terminating device having the bus wiring of the present invention, the sampling clocks for extracting the B1 channel and the B2 channel are set to the B1 channel and the B2 channel independently and at the far end side. Since it is possible to make adjustments at the time when the data channel data is detected so that the sampling clock of the channel in which the data signal sequence of the terminal is inserted has a delay, the far-end terminal that is easily affected by noise such as extraneous The signal extraction clock of can be adjusted to the optimum sample position. Therefore, the noise resistance of the signal of the terminal connected to the far end side in receiving the bus wiring can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a received signal sampling circuit in an ISDN digital line terminating device terminal side S / T point bus wiring according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an operation of a received signal sampling circuit in an ISDN digital line terminating device terminal side S / T point bus wiring according to an embodiment of the present invention.

FIG. 3 is a diagram for explaining the operation of a received signal sampling circuit in the ISDN digital line terminating device terminal side S / T point bus wiring of one embodiment of the present invention.

[Fig. 4] ISDN digital circuit terminating device terminal side S / T
It is a figure explaining the structure of point bus wiring.

FIG. 5 is a diagram illustrating a frame structure of an ISDN basic interface.

FIG. 6 ISDN digital line terminating equipment terminal side S / T
It is a figure which shows the structure of the conventional received signal sampling circuit in point bus wiring.

[Explanation of symbols]

1 Multipoint sampling circuit 2 Violation detection section 3 frame aligner 4 F bit phase detector 5 L-bit phase detector 6 Reference clock generator 7 Reception timing delay circuit section A 8 Reception timing delay circuit section B 9 Hunting gate generation circuit B 10 Hunting gate generation circuit section A 11 channel identification circuit 13 Violation detection section 15 F bit phase detector

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 7/02 H04L 12/02 H04L 25/40 H04M 11/00 303

Claims (6)

(57) [Claims] 1. A plurality of terminals are connected from the near end side to the far end side.
From the near-end side terminal at the terminal-side S / T point of the ISDN line terminator having the short-distance passive bus wiring to be continued.
The transmission signal and the transmission signal from the far end terminal are
A method of receiving a bus wiring reception signal which is a signal synthesized on a bus wiring , wherein the phase of a transmission signal of a terminal connected to the near end side of the line termination device of the bus wiring is the bus wiring reception signal. Detecting from the change point of the included F bit, the phase of the transmission signal of the terminal connected to the far end side of the line termination device of the bus line is detected from the change point of the L bit included in the received signal of the bus line. , The transmission data of the near-end side terminal and the far-end side terminal from the bus wire reception signal by two sampling signals having different phases generated based on the timing of the change point of the F bit and the timing of the change point of the L bit A method for receiving an S / T point of an ISDN line terminating device, characterized in that 2. A plurality of terminals are connected from the near end side to the far end side.
From the near-end side terminal at the terminal-side S / T point of the ISDN line terminator having the short-distance passive bus wiring to be continued.
The transmission signal and the transmission signal from the far end terminal are
A receiving circuit for a bus wiring reception signal which is a signal synthesized on the bus wiring, wherein the phase of the transmission signal of the terminal connected to the near end side of the line termination device of the bus wiring is the bus wiring reception signal. A means for detecting from a change point of the F bit included therein, and a change point of the L bit included in the received signal of the bus wire from the change point of the transmission signal of the terminal connected to the far end side of the line termination device of the bus wire. Detecting means; means for extracting transmission data of the near-end side terminal from the bus wiring reception signal by a first sampling signal generated based on the timing of the changing point of the F bit; The second sampling signal having a phase different from that of the first sampling signal generated on the basis of A S / T point receiving circuit of an ISDN line terminating device comprising means for extracting data. 3. A means for extracting transmission data of the near-end side terminal from the bus wire reception signal, a means for generating a clock signal having a phase based on the timing of the change point of the F bit, and the near-end. Channel identification means for identifying which of the two B channels included in the bus wiring received signal the transmission data of the side and far end terminals is inserted, and a change point of the identified signal and the F bit. The apparatus further comprises means for extracting transmission data of the near-end side terminal from the bus wiring reception signal with a timing signal and a clock signal having a phase based on the timing of the change point of the F bit. ISD according to claim 2
S / T point receiving circuit of N line terminating device. 4. A means for extracting transmission data of the far-end side terminal from the bus line reception signal, a means for generating a clock signal having a phase based on the timing of the change point of the L bit, and the near end. Channel identification means for identifying which of the two B channels included in the bus wiring reception signal the transmission data of the side terminal and the far-end side terminal is inserted, and a change point of the identified signal and the L bit. The apparatus further comprises means for extracting transmission data of the far-end side terminal from the bus wiring reception signal by a timing signal and a clock signal having a phase based on the timing of the change point of the L bit. ISD according to claim 2
S / T point receiving circuit of N line terminating device. 5. The transmission data of the near-end side terminal and the far-end side terminal are transmitted to the bus by detecting the time width of the L-bit negative polarity pulse formed by the quasi-ternary code by the channel identification means. 5. The S / T point receiving circuit of the ISDN line terminating device according to claim 3 or 4, wherein which of two B channels included in the wiring reception signal is inserted is identified. 6. The transmission data of the far-end side terminal is inserted into the B1 channel when the time width of the L-bit negative polarity pulse composed of a pseudo ternary code is a prescribed length. If the time width of the negative polarity pulse is shorter than the specified length, the transmission data of the near-end side terminal is B1.
The SDN of the ISDN line terminator according to claim 3 or 4, characterized in that it is identified as being inserted in a channel.
T point receiving circuit.