JP3506761B2 - Transceiver - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to transceivers.

[0002]

BACKGROUND OF THE INVENTION Due to the ever-increasing number of electronic devices used in vehicles, the Society of Automotive Engineers (So
ciency of Automatic Engin
eers) (SAE) has encouraged the entire automotive industry to develop standard data links, preferably medium speed (B class) multi-access serial communication links. The SAE has already established Recommended Practices J1850 (a set of technical requirements and parameters), and the automotive industry recommends Class B data links to Recommended Practices J185.
Accepted as 0.

J1850 specifies the use of symbols to communicate serial data over a communication bus. In the variable pulse width modulation (VPWM) coding used in the present invention, a symbol constitutes a voltage logic level that extends over a period of time, from which a voltage transition or edge occurs.

The length of time between the previous edge trip point and the current edge transition point defines the meaning of the symbol. For example, a logical zero bit that can be either short and low 64 μS or long and high 128 μS
It represents the time between the edges or transitions of the VPWM signal. The J1850 uses 3.875 volts to nominal receiver (no
minal receiver) It is specified as a transition point voltage parameter.

In order to minimize EMC (electromagnetic interference) problems during each transition of a waveform containing symbol information, the VPW
Waveform shaping of the M edge portion must be performed. In order to meet the RFI requirements of the signal arriving on the bus, each edge must have a certain slope and shape.

Within the transceiver, these problems result in attempts to maintain the consistency of the transmitted transition points. Since the transition point of the previous edge is the reference point for the current edge, a problem occurs if transition transitions occur at different times.

J1850 specifies a communication bus that can consist of two wires drawn adjacently, or a twisted pair of wires that can be scattered throughout the network.

In conventional systems, VPWM pulses are reshaped to meet the RFI requirements, but are typically reshaped without maintaining the consistency of the transmitted pulse transition points. is there. Perhaps the designers of conventional systems were more concerned with the problem of voltage offset between nodes than sending tidy pulses.

In an effort to minimize symbol time spread distortion, a search was made to find other alternatives to compensate for symbol time spread distortion. As a result of this search, the present invention is obtained which defines a consistent transition point along the edge of the pulse signal placed on the communication data line.

[0010]

SUMMARY OF THE INVENTION The present invention is a novel symbol time transfer device in a J1850 VPWM symbol communication network. The device converts variable pulse width modulated symbol information into a symmetrical trapezoidal waveform that maintains consistent symbol information between voltage transition points at the pulse edges. With twisted wire pairs used as communication buses, the noise problem is kept reasonably low, and the symbol information is kept constant between nodes when referenced to the ground return of the signal at the receiver.

[0011]

1 is a block diagram of a vehicle small area network 1 including a transceiver of the present invention. Battery 2 supplies battery power (+ V _batt ) to the nodes of the network because the negative terminal is grounded to the vehicle chassis.

5V DC stabilized power supply 3 at nodes 4-4
Each of which receives V _batt and supplies an appropriate stabilized 5 volt DC to a plurality of signal conditioning circuits. In addition to the regulated power supply 3, each node 4 has a microcontroller (MCU).
5 (ordinary 8-bit, one-chip microcontroller preferred) and a suitable symbol encoder / decoder (S
ED) 7, transceiver 10, and termination network 1
Including 1 and.

The MCU 5 receives the sensor or switch signals and uses those signals to operate the SED 7 to generate a plurality of message symbols in the appropriate VPWM format. Transceiver 10 interfaced with bus 18 via termination network 11.
Receives the message symbol from SED 7 and sends the symbol in VPWM format to another node 4 via bus 18.

Bus 18, which is a stranded bus, relies on a larger number of stranded wires to minimize noise. It extends throughout the small area network as a strand connected to the strand extension exiting each node.

FIG. 1 shows a block diagram of a communication network 1 having several nodes 4-4 employing a transceiver 10. A stranded bus 18 connects the nodes 4-4 to each other. The transceiver 10 is a transmitter (TRMT
R) circuit 16 and receiver (RCVR) circuit 20. Transmitter Circuit Reference is now made to FIG. 2, which is a schematic diagram of transmitter 16 including bus driver circuit 80. FIG. 2 also shows the interconnection of the receiver 100 of the transceiver 10 to the output terminals of the bus driver circuit. The limited VPWM signal from the integrator SED7 is sent to the transmitter 1 at terminal A.
6 and is transmitted through the normal buffer 22 to the terminal B.
To the restricted integrator 24. The integrator 24 produces a symbol signal at the output port C whose edge rise time and fall time are lengthened, the amplitude is reduced, and the trigger point voltage is established. These parameters keep the length of each symbol equidistant with respect to the pulse width of the symbol represented by the square wave input waveform. The integrator 24 is responsive to the square wave signal at the inverting input terminal of the operational amplifier 26 to produce an inverted and limited linear pulse at port C that is symmetrical about the trigger voltage level at the pulse edge. . A reference voltage of approximately 2.5 Vdc is applied to the non-inverting input terminal of amplifier 26 with the selected voltage gain. This reference voltage defines the trigger point voltage. From its trigger voltage, each rising pulse edge extends upwards by about 0.5 Vdc and each falling edge extends about 0.5 Vdc below the trigger point voltage forming the limited voltage level. It Diode 32 connected in the feedback loop of amplifier 26
And 34 perform the amplitude limiting function. By fixing the trigger point to a fixed voltage and limiting the amplitude of the pulse, the voltage amplitude above and below the transition point can be made approximately equal. This operation changes the square wave pulse into a trapezoidal pulse. Limited Waveform Shaper Increasing the curvature of the corners of the waveform pulse at point C further reduces EMI on bus 18. The output signal from the limited integrator 24 at point C is provided to the input resistor 38 of the conventional operational amplifier inverter circuit 42 of the limited waveform shaping device 36. The input and feedback signals are applied to the inverting input terminal of operational amplifier 42, as in a conventional operational amplifier inverter. The voltage at the inverting input terminal (Vn) due to constraints in the operational amplifier
Must be equal to the voltage (Vp) at the non-inverting input terminal of operational amplifier inverter 42. Since Vp is equal to 2.5 Vdc in this configuration, any voltage change in Vn is not the earth offset voltage, but V
Vary with respect to p. Therefore, assuming that the input resistor 38 detects a negative ramp voltage from the integrator 24,
The operational amplifier inverter 42 produces a positive going ramp voltage with a closed loop gain (K) referenced to about 2.5 Vdc, the transition point voltage. If the input resistor 30 detects a positive going ramp voltage, the operational amplifier inverter 42 produces a negative going ramp voltage with a closed loop gain (-K) referenced to the transition point voltage. Voltage Gain Reduction Also, the waveform shaping device 36 employs a voltage gain reduction (reduction) circuit with the operational amplifier inverter 42 to further increase the curvature of the corners of the waveform pulses during the waveform shaping process. Resistor 44 and diode circuits 46 and 48
Form a voltage gain reduction circuit that shunts the feedback resistor 40. The voltage gain reduction circuit reduces the closed loop gain when the negative or positive ramp voltage appearing at the output terminal of the operational amplifier inverter 42 reaches the first predetermined voltage level. Limiting Voltage Gain Drop Along with voltage gain drop, the amplitude of the reshaped pulse is limited. When the negative or positive going ramp voltage reaches a second predetermined voltage level, a forward biasing limiting diode 50 or 52 limits the ramp voltage to the limiting diode 50 or 52 and the complementary diode circuit 46 or 48. Clamp voltage determined by, and level. Therefore, the reshaped output waveform signal appears at the point D. The signal includes a pulse having an increased curvature and an increased amplitude with respect to the transition point voltage. Voltage-to-Current Converter The reshaped output pulse signal at point D enters the voltage-to-current converter 54 and exits as a programmed current sink signal used by the associated device below. As an example, for the symbol pulse shown, the pulse signal at point D holds an offset of 1.60 Vdc, an amplitude of 1.8 V _pp , a transition point voltage of 2.50 Vdc and 64 μs. Pulse width (PW).

A voltage divider network consisting of resistors 56 and 57 receives the pulse from point D, halves the amplitude to 0.9 V _pp , offsets 0.8 Vdc, 1.25 transition voltage, pulse width 64 μs. Then, the signal whose level has been lowered is applied to the non-inverting input terminal of the non-inverting operational amplifier 58.

The sense resistor 64 is used for feedback control of the pulse-responsive output current in the emitter circuit of the NPN buffer transistor 60, which is about 1.60 V _pp with respect to the signal ground 12.

Diodes 78, 76, 74 and resistor 72,
The offset voltage circuit composed of 70 is about 1.60V.
A fixed offset voltage of dc is applied to the diode 76
Supplied from the cathode of. The resistor 68 constitutes a part of the feedback circuit together with the resistor 66, and has an offset voltage of 0.
A corresponding pulse of approximately 1.60 V _pp , which is 80 Vdc, is produced at the inverting input terminal of operational amplifier 58.

The operational amplifier 58 responds to the voltage difference between the input pulses at the non-inverting input terminal and the inverting input terminal by:
At about 2.5 V _pp dc, it outputs a pulse in phase with the pulse at the non-inverting input terminal. This action subtracts 1.60 Vdc from the signal at point D, producing a transition point at the emitter of transistor 60 at about 0.9 Vdc. The output voltage of the operational amplifier 58 supplies the base current to the NPN buffer transistor 60 through the base resistor 62. The emitter voltage of transistor 60 produces a feedback voltage and system ground potential across the terminals of current sampling resistor 64 of a selected value. The output current of this circuit flows through the sampling resistor 64, and the feedback current flows through the feedback resistor 66. Any tendency for the output current to change appears as a change in the emitter voltage of transistor 60. This change is fed back to the inverting input terminal of the operational amplifier 58 via the feedback resistor 66, and as a result, the emitter voltage and the output current are corrected to the static closed loop value. Bus Driver Circuit The bus driver circuit 80 operates as a voltage variable current source circuit. The variable voltage between the terminals of the current detection resistor 64 of the voltage-current converter 54 enters the non-inverting input terminal of the differential operational amplifier 81. The operational amplifier 81 compares its variable voltage with the divided emitter voltage of the bus driver transistor 90. The resistors 82 and 84 form a voltage dividing circuit. The voltage at the inverting terminal is generated by the output current from the operational amplifier 81. The output current is transistor 90
Change the current in the input loop of. Input loop is resistor 8
6, 84, 82 are included.

The output loop of transistor 90 contains current from V _batt . The current flows through resistor 88 and the emitter-collector circuit of transistor 90 to bus 18.

The current from the operational amplifier 81 makes the collector-emitter voltage (Vce) of the transistor 90 almost zero. Transistor 90 then saturates and the maximum current that can flow in the output loop flows to bus 18. In other cases, if the product of the amplification factor (β) and the base current I _b remains below the maximum saturation current (I _c , sat),
Transistor 90 operates in the active or amplifying mode. However, when the base-emitter voltage (Vbe) of the transistor 90 becomes lower than the turn-on voltage (Vt),
Very little current, if any, will flow through the output loop. Then, the transistor 90 is operated in the cutoff mode. The resulting waveform has a transition point at approximately 3.875 Vdc and a symbol timing of 64μ.
An amplified pulse signal that keeps s is generated on the bus 18. The current flowing through the line bus 18 from the receiver circuit provides a trapezoidal signal that retains approximately the original symbol information at the transition points between the edges of the pulse. To trigger at the transition point of the pulse,
Comparator 101 biased by resistors 102 and 104
The receiver 100, which is configured to receive the trapezoidal signals. The comparator 101 is triggered to digitally generate a trapezoidal signal.
Convert to pulse. The digital pulses are used by SED 7 of FIG. 1 to generate digital messages. These digital messages are sent to each microcontroller in each node 4-4. Waveform Diagrams To further explain the operation of device 10, FIGS.
Refer to the waveform diagram of. FIG. 3A shows a VPWM symbol signal. The signal enters the transmitter 16 of FIG. 1 from the SED 7. The pulse width of the symbol data in the square wave pulse entering the transmitter 16 varies from about 16 μs to as wide as 1024 μs. The pulse shown in FIG. 3A shows the main short symbol with a pulse width of 64 μs.

FIG. 3B shows the output terminal of the buffer 22 and FIG.
3B shows the same symbol message as shown in FIG. 3A at point B of FIG. However, FIG. 3C shows the trapezoidal signal at the output terminal of the limited integrator circuit 24 of FIG.

FIG. 3D shows a trapezoidal signal with an edge reshaping at the tip of the pulse edge portion, with some gain, after passing through the limited waveform shaper circuit 36 of FIG. Show. FIG. 3E shows the pulses appearing in the feedback circuit of the voltage-current converter 54, which pulses appear across the terminals of the sense resistor.

FIG. 3F shows a pulse at the output terminal of bus driver 90. The voltage amplitude of those pulses is about four times the voltage amplitude appearing across the terminals of the sense resistor 64 of the voltage-current converter 54.

It is to be understood that the above embodiments are primarily illustrative of the principles of the present invention. Although a discrete component and integrated circuit combination embodiment is disclosed, an equivalent integrated circuit / firmware / software combination embodiment may be developed.

[Brief description of drawings]

FIG. 1 shows in block diagram a communication network employing the transmitter circuit of the present invention in a transceiver.

FIG. 2 shows in schematic diagram a part of the transmitter circuit of the transceiver of the invention.

3 shows waveforms of signals appearing in the transmitter circuit of FIG.

[Explanation of symbols]

5 Micro controller 7-symbol encoder / decoder 10 transceivers 16 transmitter 20,100 receiver 24 integrator 26,58 Operational amplifier 36 Wave Shaper 42 Operational amplifier inverter 50,52 Limiting diode 54 Voltage-current converter 58 Non-inverting operational amplifier 80, 90 bus driver circuit 81 Differential operational amplifier 101 comparator

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-58-10161 (JP, A) European patent application publication 671834 (EP, A 1) US patent 5268616 (US, A) (58) Fields investigated (Int .Cl. ⁷ , DB name) H03K 5/125 H04B 14/02 B60R 16/02

Claims (8)

(57) [Claims] 1. A transceiver in a node of said network having a communication bus designated for use in an automotive industry standard data link interconnecting nodes of a multi-node automotive communication network, each node being a selection node. The selected measured quantity of digital pulses appearing at a rate that changes in response to a change in the measured quantity being variable pulse width modulated (VPWM) symmetrically containing symbol information representative of the magnitude of the measured quantity. Providing a means of converting to a trapezoidal waveform signal, each node providing a stabilized logic voltage referenced to the signal ground return,
A stabilized power supply connected to the battery of the vehicle and a signal representing the magnitude of the measured quantity are received, the received signal is formatted into a digital message, and a symbol encoder / decoder
D) includes a microcontroller (MCU) connected between the input device and the SED for polling the input and output ports connected to D) and initiating transmissions by the bus through the SED, the SED , Variable Pulse Width Modulated (VPWM) that sends digital messages from the MCU to other transceivers connected to the bus
Interconnected between the MCU and transceiver for conversion to square wave line coding and to digital messages used by the MCU to update or control other peripherals associated with the network In the above transceiver, the transceiver receives (a) a VPWM square wave pulse having a pulse width that defines symbol information with respect to time and logic level at an input terminal, the phase of which is 180 degrees different from that of the square wave pulse, and a fixed voltage level. An integrator which generates a trapezoidal waveform pulse signal at the output terminal, and (b) which receives the trapezoidal waveform pulse signal from the integrator at the input terminal, and selects which shape of both edges at each edge of the pulse is selected. Remake over time and then revert to the original square wave signal that is in phase with the input waveform signal. A waveform that has the same pulse width as the input trapezoidal signal at the transition point voltage so as to retain the rare symbol information, and generates a reshaped trapezoidal waveform signal at the output terminal based on another fixed voltage level. A voltage-current exchanger having a shaper and (c) an input terminal for receiving a trapezoidal waveform signal reshaped from the waveform shaper, and giving a duplicate of the reshaped trapezoidal waveform signal to an output terminal as a control current source signal. The voltage delivered to the current sensor circuit in the voltage-current converter to provide this controlled current source signal with a pulse voltage potential referenced to the signal ground return in an amount proportional to the voltage across the current sensor. A current converter, (d) connected between the car battery and the signal ground return path,
The pulse voltage potential is received at the input terminal from the voltage-current converter, amplified, and holds the symbol information contained in the original square-wave signal after being amplified, with reference to the signal ground return path, and to the other listening node by the bus. A bus driver for generating an amplified signal of a trapezoidal pulse signal which has been reshaped through the output terminal of the unbalanced termination, and (e) is interconnected between the bus and the SED and reshaped A receiver circuit that receives the trapezoidal waveform signals from the bus, extracts the symbol information contained in those waveform signals, and converts the extracted symbol information into a digital pulse signal having a pulse duration equal to the symbol information. And a transceiver in a node of a multi-node automotive communication network, comprising: 2. The apparatus of claim 1, wherein the communication bus is a twisted pair bus. 3. The symbol information in the reshaped trapezoidal pulse received by each receiver in each transceiver remains constant despite the fact that it is associated with a signal ground return at each node. The device according to claim 1. 4. The integrator extends the rise time and fall time of the edge portion of the input square wave pulse to obtain symmetrical rise time and fall time gradients centered on the selected maximum pulse amplitude location. The apparatus of claim 1 including circuitry for producing, wherein the amplitude of the limited pulse is at a selected voltage level. 5. The waveform shaper performs a gain operation and a control gain lowering operation so as to further round the corners of the pulse at the end of each edge portion in the formation of a trapezoidal pulse having a reshaped shape, and the obtained gain is The apparatus of claim 4, wherein the apparatus limits the pulse of selected voltage amplitude greater than the amplitude of the limited pulse from the integrator. 6. The apparatus of claim 5, wherein the amplitude of the bus driver output pulse is a selected multiple of the amplitude of the pulse across the terminals of the sensor in the voltage to current converter. 7. The apparatus of claim 6 wherein the selected multiple of the amplitude of the pulse driver output pulse is about four times the amplitude of the output pulse from the voltage to current converter. 8. A communication bus is provided, which is connected to the bus, for supplying information from an input device such as a sensor and a switch to a network so that the nodes can be connected to each other for synchronous communication between the nodes. Each node is (1) a regulated power supply connected to a fixed voltage to provide a stabilized logic voltage referenced to a signal ground return path, (2) an input device associated with the node, and a symbol encoder. / Decoder (SE
D) is connected to a regulated power supply, receives a signal indicating the magnitude of the measured quantity, formats the received signal into a digital message, and polls the input and output ports connected to the SED. And a microcontroller (MCU) that initiates transmissions over the bus by controlling the operation of the SED, and (3) the SED is connected between the MCU and the transceiver to send digital messages from the MCU. , Convert to a pulse-width modulated square wave signal sent to another transceiver connected to the bus, and update the square wave digital signal received from the other transceiver to another peripheral associated with the network or A node traversal of a multi-node network that translates into digital messages used by the MCU to control In the receiver, A. The VPWM square wave pulse signal received from the SED is a trapezoidal waveform signal whose amplitude is reduced, the phase is different by 180 degrees, and which is based on a limited fixed voltage level, and is included in the original square wave pulse. An integrating means for converting to a trapezoidal waveform signal with a consistent pulse width at the selected trigger point to maintain the definition of the symbol information; Coupled to this integrator means, delimiting the corners at the end of each edge of the pulse of the trapezoidal waveform signal and then reshaping those corners to maintain a consistent pulse width at the pulse's trigger point while maintaining a gain parameter. And a waveform shaper that provides a controlled gain reduction parameter, and A voltage-to-current converter that uses a reshaped trapezoidal waveform signal to provide a controlled current source signal that varies with respect to the signal ground return path in response to changes in the amplitude and duration of the reshaped trapezoidal waveform signal. Device means, and D. Bus driver means for sending an amplified and reshaped pulse signal to a bus carrying a symbol message in response to a changing control current source signal to minimize electromagnetic interference in the vehicle. Node transceiver of a multi-node network having a bus.