JP3500174B2 - Input circuit of semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit of a semiconductor device, and more particularly, to a semiconductor device for detecting that a rising speed or a falling speed of an input signal carrying logic level information changes slower than a predetermined speed. Regarding the input circuit.

[0002]

2. Description of the Related Art The circuit shown in FIG. 4 has been used as an input circuit of a semiconductor memory or a microcomputer. The input circuit shown in FIG. 4 includes an input unit 102 that enables the output of an address input signal 101 that is an input signal when the gate signal ce100 is at a low level, and an output signal H of the input unit 102.
An inverter unit 104 for shaping the waveform of 103 and an output unit 106 for outputting the output signal I105 of the inverter unit 104 to the decoder circuit at both H and L levels.

[0003]

When the rising or falling time of the input signal 101 is 5 to 10 ns or less, the input signal 101 is transmitted to the output section 104 without any particular problem.

However, when the rising or falling time of the input signal 101 is, for example, 50 to 100 ns, there is a problem that noise occurs in the output signal.

That is, as shown in FIG. 5, the input signal 1
When the rising or falling of 01 is blunt, there is a long time to obtain either the high level or the low level, so the output signal H of the input unit 102
An unstable ripple may occur in 103. A signal with a ripple of the output signal H103 is output from the inverter unit 1
The waveform is shaped in 04 to generate a pulse-shaped waveform signal as shown in FIG. When the pulse-shaped waveform signal as shown in FIG. 5C passes through the output unit 106 and the decoder circuit operates, noise is added to the ground potential Vss and the power supply potential Vcc. This noise may be fed back to the input first stage of the input unit 102 and the output signal H103 may be inverted. As a result, noise is further applied to the ground potential Vss and the power supply potential Vcc, so that the noise further increases and an oscillation state occurs.

In such a case, the access time may be delayed, but when operating at a high temperature or a high voltage (for example, in a burn-in test), a high voltage is effectively applied due to noise. There is a risk of latch-up. Particularly in the case of a burn-in test or the like, it is difficult to take sufficient noise countermeasures for the ground potential Vss and the power supply potential Vcc, so that the presence of noise caused by the rising or falling of the input signal 101 is a problem. It was

Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art, and even if the rising or falling of the input signal is blunt, noise is fed back to the first stage of the input circuit and the input signal becomes unstable. It is to provide a semiconductor input circuit that prevents transmission.

[0008]

In order to achieve the above object, in a semiconductor input circuit according to the present invention, an input signal carrying logic level information is provided during a transition period from a high level to a low level or from a low level to a high level. A detection circuit for detecting the presence of the input signal, and preventing the input signal from being transmitted to the next stage during the transition period and holding the state of the input signal at the start or end of the transition period during the transition period. On the other hand, gate means for transmitting the input signal to the next stage during a period other than the transition period, the detection of the transition period by the detection circuit is obtained by inverting the input signal and the input signal. It is characterized in that both the input signal and the inverted input signal having a different speed of change are detected by detecting a range in which both are at a high level or a low level.

[0009]

The gate means prevents the input signal from being transmitted to the next stage during the transition period, and allows the input signal to pass to the next stage outside the transition period, and a gate circuit of the gate circuit. A latch circuit connected to a subsequent stage, which holds a state of the input signal at the start or end of the transition period and allows a signal passed through the gate circuit to pass during a period other than the transition period. .

The gate circuit and the latch circuit are characterized in that their gates are opened and closed by an output signal of the detection circuit.

[0012]

The detecting circuit detects the time range in which the input signal is blunt. The gate means prevents the input signal from being transmitted to the next stage during the time range and holds the state of the input signal at the start or end of the time range, and during the time range other than the time range. Transmits the input signal to the next stage.

Since signal transmission between the input circuit and the next stage is blocked during the time range, noise generated due to the rising or falling of the input signal is fed back to the input circuit. The input signal is not transmitted instable.

Further, since the state of the input signal at the start or end of the time range is maintained during the time range, signal transmission between the input circuit and the next stage is prevented during the time range. However, the information contained in the input signal is transmitted to the next stage without any trouble.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor input circuit of the present invention will be described with reference to FIGS. In FIG. 1, reference numeral 1 is a gate signal ce50 and an input signal 5 which is an address input signal.
1 is an input section composed of a NOR gate, and the output side of the input section 1 is a waveform shaping section 2 composed of two inverters, and the changing speed of rising or falling of the input signal 51 is slower than a predetermined speed. It is connected to the detection circuit 3 which detects the time range for The output side of the waveform shaping section 2 is connected to the gate means 4. The gate means 4 prevents the output signal F53 of the waveform shaping section 2 from being transmitted to the next stage during the time range in which the blunted waveform portion of the input signal 51 is detected by the detection circuit 3. During the period other than the time range, the signal F53 is transmitted to the next stage and the state of the transmitted signal is held. The output side of the gate means 4 is connected to an output section 5 for outputting to a decoder circuit (not shown).

The detection circuit 3 has an inverter 10 on the input side.
And a two-input NAND gate 11 and an output gate 12 composed of two inverters. The output signal E52 that is the output of the input unit 1 and the output signal D55 of the inverter 10 are input to the NAND gate 11. NAN
The output signal C56 of the D gate 11 is input to the output gate 12, and the output signals A and B are output from the output gate 12. The output signal A57 and the output signal B58 are as shown in FIG.
As shown in (f), it is a pulse signal having a pulse width in a time range in which the changing speed of rising or falling of the input signal 51 changes slower than a predetermined speed.

The gate means 4 has a signal A57 and a signal B58.
During the time of the pulse width of the signal A57 and the signal B58 and the gate circuit 13 which is a two-input inverter that opens the gate when and are input, the state of the input signal 51 before the time having this pulse width is held. And a latch circuit 14. The latch circuit 14 is composed of a one-input inverter 15 and a two-input inverter 16.

Next, the operation of this embodiment will be described with reference to FIGS. FIG. 2 shows a case where the waveform of the input signal 51 is blunt. As shown in (b), the signal E
52 is formed by inverting the input signal 51 and has a shorter transition time. The signal D55 has its waveform shaped as a result of the signal E52 passing through the inverter 10, and has a shorter transition time than the signal E52.

When the rising or falling time of the input signal 51 is, for example, 50 to 100 ns, there are times when the signal E52 and the signal D55 are at the high level or at the low level. As a result of inputting the signal E52 and the signal D55 having such a time that they are at a high level or a low level to each other to the 2-input NAND gate 11, a signal C56 is obtained as shown in (d). Signal C56 signal is E5
It is at the low level while both 2 and the signal D55 are at the low level. The signal C56 is waveform-shaped by the output gate 12, and the signal A57 and the signal B58 are output from the output gate 12.
Is output.

The signal A57 and the signal B58 are the gate circuit 1
3 and the inverter 1 of the latch circuit 14
6 is input.

The gate circuit 13 closes the gate when the signal A57 is at the high level and the signal B58 is at the low level, and opens the gate when the signal A57 is at the low level and the signal B58 is at the high level.

Further, the inverter 16 forming the latch circuit 14 opens its gate when the signal A57 is at a high level and the signal B58 is at a low level, and the signal A57 is at a low level, in the opposite manner to the operation of the gate circuit 13. The gate is closed when the signal B58 is at the high level. That is, the inverter 16 functions as an inverter only while the gate of the gate circuit 13 is closed, and forms a latch circuit together with the inverter 15.

When the signal A57 is at a low level and the signal B58 is at a high level, the latch circuit 14
Holds the state of the signal F53 before the gate of the gate circuit 13 starts to close while the gate circuit 13 closes the gate. The signal G54 is a signal output as the output signal of the latch circuit 14 while the gate circuit 13 is closing the gate, and is a signal output as the output signal of the inverter 15 while the gate circuit 13 is opening the gate. . The signal G54 is sent to the decoder circuit at the next stage via the output unit 5.

Next, a case where the falling or rising waveform of the input signal 51 is not blunt will be described with reference to FIG.

In this case, there is almost no time when the signal E52 and the signal D55 are at the high level or at the low level. Therefore, the signal C56 is substantially always at high level. As a result, the signal A57 is always at the low level and the signal B58 is always at the high level.
Due to such signals A57 and B58, the gate of the gate circuit 13 is opened, while the gate of the inverter 16 is closed and the latch circuit 14 does not operate. Therefore,
The signal F53 passes through the gate circuit 13 and the inverter 15, and the signal G54 is obtained.

According to the structure of the present embodiment, the detection circuit 3 detects the time range in which the input signal 51 is blunted, and the gate means 4 detects that the input circuit is in the blunt time range. Since the signal transmission to the next stage is blocked, noise generated due to the rising or falling of the input signal is not fed back to the input circuit and the input signal is not transmitted instable.

Further, since the latch circuit 14 holds the state of the signal F53 at the start of the time range during the time range, signal transmission between the input circuit and the next stage during the time range is performed. Even if blocked, the information contained in the input signal 51 is
It is transmitted to the next stage without any trouble.

The latch circuit 14 may hold the state of the signal F53 at the end of the time range instead of holding the state of the signal F53 at the start of the time range.

[0029]

The detection circuit detects the time range in which the input signal is blunted, and the gate means prevents signal transmission between the input circuit and the next stage during the time range in which the input signal is blunted. Therefore, noise generated due to the rising or falling of the input signal is not fed back to the input circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of an input circuit of a semiconductor device according to the present invention.

FIG. 2 is a waveform diagram of each part in this embodiment when an input signal is blunt.

FIG. 3 is a waveform diagram of each part in this embodiment when the input signal is not blunt.

FIG. 4 is a circuit diagram showing an input circuit of a conventional semiconductor device.

FIG. 5 is a waveform diagram of each part in the input circuit of the conventional semiconductor device.

[Explanation of symbols]

1 Input section 2 Wave shaping section 3 detection circuit 4 gate means 5 Output section 10 inverter 11 2-input NAND 13 Gate circuit 14 Latch circuit 16 inverter

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP 62-77714 (JP, A) JP 61-269515 (JP, A) JP 4-130514 (JP, A) JP 4- 123393 (JP, A) JP-A-2-196507 (JP, A) JP-A-1-186017 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 19/00

Claims (3)

(57) [Claims] 1. A detection circuit for detecting that an input signal carrying logic level information is in a transition period from a high level to a low level or from a low level to a high level, and the input signal to the next stage during the transition period. Gate means for preventing transmission and for holding the state of the input signal at the start or end of the transition period during the transition period, while transmitting the input signal to the next stage during periods other than the transition period. In the detection of the transition period by the detection circuit, both the input signal and an inverted input signal obtained by inverting the input signal and having a different speed of change from the input signal are set to a high level or a low level. An input circuit of a semiconductor device, which is performed by detecting a certain range. 2. A gate circuit for preventing the input signal from being transmitted to the next stage during the transition period and passing the input signal to the next stage outside the transition period, and the gate circuit. A latch circuit that is connected to a subsequent stage of the circuit, holds the state of the input signal at the start or end of the transition period, and passes the signal that has passed through the gate circuit during a period other than the transition period. The input circuit of the semiconductor device according to claim 1. 3. The input circuit of a semiconductor device according to claim 2 , wherein gates of the gate circuit and the latch circuit are opened / closed by an output signal of the detection circuit.