JP3495101B2 - Disk array system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface relay technique for a disk array system, and more particularly to a technique effective when applied to measures such as an increase in the number of connected devices or a connection length in a connection interface between a plurality of devices. .

[0002]

2. Description of the Related Art In recent years, a disk array system has attracted attention as a next-generation magnetic disk device. This is one in which a large number of small magnetic disk devices (hereinafter referred to as HDDs) are arranged side by side and built in one magnetic disk device. Instead of using large magnetic disks, multiple low-priced HDDs are used to achieve high capacity and low cost. Also, multiple HD
Speeding up is possible by accessing D in parallel.

The mainstream HDD interface is ANSI.
It is SCSI (Small Computer System Interface) which is a standard interface established by (American National Standards Institute). The conventional SCSI system will be described below. FIG. 21 is a block diagram showing the outline of a conventional SCSI system. The upper device 100 and the lower device 101 are SCSI specification devices, and the lower device is an HDD. 102 is SC
You can connect up to 8 devices with SCSI specifications using the SI specification cable. 103 is a terminal resistance, SCS
In order to suppress reflection of the I signal, terminating resistors are connected to both ends of the cable (in FIG. 21, the terminating resistor on the host device 100 side is omitted).

The electrical specifications of SCSI include a single end type and a differential type. The single-ended type input buffer is a Schmitt type (for example, 74F24
4 LSI). The output buffer is an open collector type (for example, 74N38 TTL logic LSI) in which the impedance is “L” when active and high impedance when inactive, an open drain type, or a three-state type. Normally, HDDs are equipped with SC signal input and output buffers to reduce size and cost.
The single-ended type that can be built into the SI control LSI (generation of SCSI signal inside HDD) is adopted.

Currently available HDDs have a data bus of 8 bits (+1 bit parity) and can be connected to S.
The maximum number of CSI specification devices is eight. On the other hand, a new HDD compatible with wide SCSI is planned to be commercialized. This means that the data bus is doubled to 16 bits (+2 bits of parity) for speeding up, and the number of connectable devices (wide SCSI compatible) is doubled for expansion to a maximum of 16.

The use of this wide SCSI compatible HDD in the above-mentioned magnetic disk device of the disk array system is very effective in realizing high speed and large capacity, but the following problems occur. If the number of devices to be connected increases or the cable length becomes longer than before, the signal waveform will be disturbed and the single-ended electrical conditions cannot be satisfied. As a result, the impedance increases due to the increase in load, the reflection of the SCSI signal waveform increases, and the noise margin disappears during high-speed data transfer (100 ns cycle in Fast SCSI), making normal operation difficult.

There is a method of using a differential type to secure a noise margin, but a dedicated input / output buffer is required for each HDD to be connected, which makes it difficult to reduce the size and cost.

[0008]

In the above-mentioned prior art, particular consideration is given to stable operation when there are a large number of devices to be connected, a long connection length, or a large number of devices and a long connection length. Therefore, there is a problem that the number of connected devices and the connection length between the devices are restricted.

For this reason, for example, it has been difficult to construct a disk array system or the like by connecting a large number of HDDs under the control of a host device with a SCSI interface.

Further, for example, the above-mentioned SCSI interface includes a bidirectional signal. However, in the case of simply relaying such a bidirectional signal to prevent signal deterioration or the like, the bidirectional signal is In addition, a signal for identifying the transmission direction of the bidirectional signal is additionally required, which causes problems such as an increase in interface signal lines and deviation from the interface standard.

As an example of an interface technique for connecting a plurality of devices, the technique disclosed in Japanese Patent Laid-Open No. 318653/1992 is known. In this technology, in order to connect and control a plurality of lower-level devices under the control of the higher-level device, the higher-level device is provided with a function for issuing a simultaneous address for selecting the lower-level device, and each of the lower-level devices. Discloses a configuration provided with a function of identifying its own individual address from a broadcast address, but does not consider signal deterioration in the process of transmitting the broadcast address on the bus at all.

It is an object of the present invention to provide a disk array system equipped with an interface relay technique capable of accurately relaying bidirectional interface signals without increasing the number of interface signals.

Another object of the present invention is to provide a disk array system equipped with an interface relay technique capable of ensuring stable operation by improving the quality (noise margin) of interface signals.

Still another object of the present invention is to provide a disk array system equipped with an interface relay technology capable of increasing the stable transmission distance of an interface signal and eliminating the distance limitation of the arrangement of devices. Especially.

Still another object of the present invention is to provide a disk array system equipped with an interface relay technique capable of increasing the number of connected devices by preventing the deterioration of interface signals.

[0016]

A disk array system according to the present invention comprises a plurality of disk devices mounted on a substrate, a device controller for controlling data transfer to the disk devices, and a disk device and a device controller. A relay device that is interposed between the disk device and the device control unit, is mounted on the substrate, and drives a signal that is transmitted and received bidirectionally between the disk device and the device control unit. is there. Further, the disk array system of the present invention is
A system having a plurality of disk devices connected by a first cable, a device control section for controlling data transfer to the disk apparatus, a second cable connecting the device control section and the system, and a system A relay device is provided, which is connected to the first and second cables and drives a signal bidirectionally transmitted and received between the disk device and the device control unit. Further, the disk array system of the present invention includes a disk device having a plurality of HDD units connected by a first cable,
A device controller that controls the HDD unit; a second cable that connects the disk device and the device controller;
A first connector that is located near the HDD unit in the disk device and that is electrically connected to the first cable; and a second connector that is electrically connected to the second cable. And a relay device which is connected to the second cable and drives a signal bidirectionally transmitted and received between the disk device and the device controller. More specifically, the interface relay device as the relay device in the disk array system of the present invention has the following configuration. That is, (1) at least N (> = 1)
In a system in which one upper device and M (> = 1) lower devices are connected, the above upper device and lower device are divided into two groups, group A and group B, and they are connected to group A and group B, respectively. A
A bidirectional buffer having two interfaces on the B side and the B side is provided, and when the A group activates the bidirectional interface signal, the corresponding bidirectional interface signal on the B side is based on the change of the bidirectional interface signal. When the B group activates the bidirectional interface signal, the bidirectional interface signal itself is activated by actively driving the corresponding bidirectional interface signal on the A side based on the change of the bidirectional interface signal. The bidirectional signal drive unit is configured to switch the transmission direction in the bidirectional buffer.

(2) A plurality of the interface relay devices are provided, the group A and the side A of the plurality of interface relay devices are connected by one interface, and the group B is distributed by the plurality of interface relay devices. Each of them can be connected by the interface on the B side.

(3) The interface relay device may include a signal delay adjusting section for adjusting a signal delay.

(4) The interface relay device may be configured such that the A side interface and the A group are connected by a cable, and the B side interface and the B group are connected by a wiring pattern routed on the motherboard. it can.

(5) A part or the whole of the interface relay device may be formed into an LSI.

(6) By adopting the interface relay device as a SCSI interface, a disk array system comprising a plurality of small magnetic disk devices can be constructed.

[0022]

In a system in which N (> = 1) upper devices and M (> = 1) lower devices are connected, the plurality of upper devices and lower devices divided into two groups A and B Against
By connecting the A-side interface and the B-side interface of the interface relay device, respectively, in the interface connection including the bidirectional interface signal, the number of connection devices and the connection length can be divided without increasing the number of signal lines. Impedance can be reduced.
Further, the interface relay device activates the corresponding signal on the B side when the A group activates the signal, and activates the corresponding signal on the A side when the B group activates the signal. As a result, the quality of the interface signal (noise margin) is improved, and stable operation can be secured.

[0023]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a conceptual diagram showing an example of the configuration of a disk array system including an interface relay device according to an embodiment of the present invention. In this embodiment, as an example, a case where the interface relay device of the present invention is applied to a disk array system in which one upper device (N = 1) and 15 lower devices (M = 15) are connected by a SCSI interface will be described. To do.

That is, FIG. 1 shows a SCSI in which one host device and 15 HDDs are connected to a wide SCSI.
1 shows a system (a part of a magnetic disk device).

In the figure, the lower device 11 is an HDD unit in which an HDD can be mounted on a motherboard. Reference numerals 1a and 1b are interface relay devices (mounted on the board) that distribute the load to 15 and 15 lower devices 11 connected by SCSI, respectively, and drive SCSI signals. In both the interface relay device 1a and the interface relay device 1b, the connection destinations on the A side and the B side are the upper device 10 and the lower device 11, respectively. 12a and 18a, 1
8b is wide compatible SCSI (single end type)
So, in fact, each cable and motherboard 1
It is a wiring pattern on 3a, 13b. The host device 10 and the interface relay devices 1a and 1b are connected to the cable 12a in a potato-like manner. Motherboards 13a and 13b connect the interface relay device 1a and eight lower devices 11 to each other, and 13b connect the interface relay device 1b and seven lower devices 11 to each other in a potato-like manner. Reference numeral 15 is a connector for connecting the interface relay devices 1a and 1b to the cable 12a,
Reference numeral 16 is a connection connector for connecting the interface relay devices 1a and 1b to the motherboards 13a and 13b, respectively, and 17 is a connection connector for connecting the lower device 11 and the motherboard 13a or 13b.

Host device 10 at both ends of cable 12a
A terminating resistor is connected to the interface relay device 1b in order to suppress reflection of SCSI signals (not shown). Similarly, a terminating resistor 14 is connected to one end of the SCSI signal 18 (wiring patterns 18a and 18b) on the motherboard 13a or 13b, and the other end is also terminated to the B side of each of the interface relay devices 1a and 1b. Connect a resistor (not shown).

The interface relay device 1a of this embodiment,
The function of 1b is the following two points.

(1) Ensuring the quality of SCSI signals The number of connections of the cable 12a for transmitting SCSI signals is three.
Table (host device 10, interface relay devices 1a, 1
b), the SCSI signals 18a and 18b are respectively connected to 9 units (8 lower devices 11 and 1a) and 8 units (7 lower devices 11 and 1b). Therefore, as compared with a system in which 16 units are connected to one SCSI, the maximum number of connections is 9, so that the quality (noise margin) of the SCSI signal can be secured. Further, since one SCSI is divided into three SCSI, the total value of the transmission distances of the SCSI signal 12 (12a) and the SCSI signal 18 (18a, 18b) can be made three times longer than one SCSI.

(2) Functionally, one SCSI connection Originally, the upper device 10 and the 15 lower devices 11 are one S connection.
Where it should be connected to CSI, interface relay devices 1a and 1b are provided to ensure the quality of SCSI signals.
Therefore, functionally, three SCSI signals (12a, 1
8a, 18b) are connected by one SCSI. S
Of the CSI signals, the unidirectional signal may simply be received by the input buffer and driven as it is by the output buffer. Therefore, the method of driving the bidirectional signal is important.

One of the features of the disk array type magnetic disk device is that the failed HDD unit can be replaced even during operation, thereby realizing non-stop operation. In this embodiment, the HDD unit is used as the motherboard 13a, 13b.
Cables are not needed due to the structure of connecting and disconnecting via the connector 17 provided above, and H is not required during assembly and maintenance.
There is an advantage that it is easy to attach and detach the DD unit.

Below, the interface relay devices 1a, 1
The internal configuration of b will be described.

FIG. 2 is an internal block diagram showing an example of the interface relay device 1b. In the figure, 20 is a bidirectional signal driving section for driving bidirectional signals, 23 and 24 are unidirectional signal driving sections for driving unidirectional signals from A side to B side and B side to A side, and 25 and 26. Are S on the A side and B side, respectively
It is a terminating resistor connected to CSI. The internal configuration of the interface relay device 1a is obtained by removing the terminating resistor 25 from the configuration of FIG. 2 (the cable 12a of FIG.
And because terminal resistors are connected to both ends by the interface relay device 1b). The bidirectional signal driver 20 is composed of an output buffer 21 and a drive signal generator 22. The TI SN75LBC968 is an example of an input buffer / output buffer that satisfies the SCSI specifications.

Here, the SCSI signal will be specifically described. FIG. 19 is an explanatory diagram showing the function of a wide range SCSI signal. The direction of each signal in FIG. 19 is uniquely determined because the connection destinations on the A side and the B side are the upper device 10 and the lower device 11, respectively. Next, the bidirectional signal driver 20
The configuration will be specifically described.

FIG. 3 is an internal block diagram showing an example of the bidirectional signal drive section 20 for driving the SCSI signal SEL-N1 in this embodiment. In the figure, 217 and 216 are ASEL-N and BSEL-N, which are A-side and B-side SEL-N signals, and 200 and 201 are signal ASE, respectively.
Output buffers for driving L-N217 and BSEL-N216, and 202 and 203 for A-side and B-side SEL-, respectively.
It is a Schmitt type input buffer that receives an N signal.
The output buffers 200 and 201 are open-drain type. For example, when the signal ASELDRV-P211 is active “H” and inactive “L”, the output signal ASEL-N217 is set to “L” and high impedance (actually, in reality). "H" due to terminating resistance. Reference numerals 204 and 205 are NAND circuits (negative logic of logical products), and 208 and 20.
Reference numeral 9 denotes a delay unit that delays a signal (for example, a shift register circuit that synchronizes with a clock signal).

Reference numerals 210 and 211 denote BSEL-N2, respectively.
16, signals BSELDRV-P and ASELDRV-P for driving ASEL-N217. 21
2 and 213 are signals BSELDRV-P and ASE, respectively.
Logically inverted signal BSELDRV-N, AS of LDRV-P
ELDRV-N. Reference numerals 214 and 215 denote delayed signals B obtained by delaying the signals 212 and 213 with the same polarity, respectively.
SELDRVDLY-N (B side SEL-N drive delay signal) and ASELDRVDLY-N (A side SEL-N drive delay signal).

One input of 206 and 207 is RESE
It is a negative input OR (logical sum) circuit with T-P. RESET-P (active “H”) when power is turned on
Signal BSELDRV-P210 and signal AS
The operation of making the ELDRV-P211 inactive is performed.

FIG. 4 is a time chart showing the operation of the bidirectional signal drive unit shown in FIG. In the figure, the signal ASEL-N
When 217 becomes active "L", signals 213, 21
Since both 5 are "H", the signal BSELDRV-N212 becomes active "L". Therefore, BSEL-N216
Becomes active "L". At this time, the signal ASELDR
The V-N 213 is inactive "H" because the signal 212 is "L". When the signal ASEL-N217 changes to inactive “H”, the signal BSELDRV-N21
2 becomes inactive “H” and BSEL-N216
Becomes inactive "H". This time the signal BSEL-
When N216 goes active low, signals 212,2
Since both 14 are "H", the signal ASELDRV-N213
Becomes active "L". Therefore, ASEL-N21
7 becomes active "L". At this time, the signal BSELD
The RV-N212 is inactive “H” because the signal 213 is “L”. When the signal BSEL-N216 changes to inactive "H", the signal ASELDRV-N2
13 becomes inactive “H” and ASEL-N21
7 becomes inactive "H".

The above operation is summarized as follows.
When both the ASEL-N217 and the BSEL-N216 are inactive "H" and the host device 10 on the A side sets the signal ASEL-N217 to active "L", BSE
L-N216 becomes active "L". Subsequently, when the host device 10 makes the signal ASEL-N217 inactive "H", the BSEL-N216 becomes inactive "H". Similarly, the B-side lower-level device 11 outputs the signal BS.
When EL-N216 is set to active "L", ASEL-
N217 becomes active "L", and subsequently, when the signal BSEL-N216 is made active "L" in the B-side lower device 11, ASEL-N217 becomes active "L".
Becomes As a result, the SEL signal is correctly driven.

Next, the delay unit 208, 209 outputs the signal 2
The reason for delaying 12, 213 will be described. For example, the signal ASEL-N217 becomes active "L" and the signal BSELDRV-N212 becomes active "L".
Consider the case where the signal BSEL-N216 is set to active "L". When the signal ASEL-N217 changes to inactive “H”, the signal BSELDRV-N21
2 becomes "H". After that, the logic circuits 206, 201,
The signal BSEL-N216 changes to inactive "H" with a delay of the total time T of the delay of 203 (from several ns to several tens of ns). If the NAND circuit 205 is the signal BS
If there are two inputs without ELDRVDLY-N214, B
The signal ASELDRV-N213 becomes active "L" until the SEL-N216 changes to inactive "H". As a result, the signal ASELDRV-P21
1 becomes active "H", and the signal ASEL-N217 becomes active "L". Since the signal BSEL-N216 is inactive "H", this is different from the original SCSI drive. Then the signal ASELDRV-N2
Signal BSEL to prevent 13 from becoming active "L"
Delayed DRV-N212 (more than time T:
(A delay time of 100 ns can be secured by shifting twice with a 20 MHz clock in the shift register) Delay signal BSEL
The DRVDLY-N 214 is input to the NAND circuit 205.

As described above, according to the interface relay apparatus of the present embodiment, even when transmitting / receiving the bidirectional interface signal, the control signal other than the bidirectional interface signal is not required, that is, the number of the interface signals is reduced. The bidirectional interface signal can be accurately transmitted without increasing the number. Further, stable operation can be ensured by improving the quality (noise margin) of the interface signal. Further, the stable transmission distance of the interface signal can be increased, and the distance limitation of the arrangement of the upper device and the lower device can be eliminated.

For example, in the case of the SCSI interface, there is an advantage that signals other than the original SCSI interface are not required. Further, the SCSI interface has certain restrictions such as the number of devices to be connected and the distance between the devices, but in the case of the present embodiment, the number of connected devices is improved by improving the quality (noise margin) of the interface signal. Stable operation can be ensured in a system with a large number or a long connection length, or a system with a large number of connection devices and a long connection length.

In the system example of FIG. 1, the host device 10 is connected to the A-side SCSI of the interface relay devices 1a and 1b, and the lower device 11 is connected to the B-side SCSI, respectively. However, the number of connected upper level devices 10 and lower level devices 11 is not limited (arbitrary within the maximum number that can be connected to SCSI). Further, the number of interface relay devices is not limited and is arbitrary. Further, the interface relay device of the present invention relays and drives a SCSI signal, and does not require a unique address value called ID as in the host device 10 and the host device 11.

In the system example of FIG. 1, the upper device 10 and the lower device 11 are separately connected to the A-side and B-side SCSI of the interface relay devices 1a and 1b, respectively. However, a system in which a plurality of higher-level devices 10 and lower-level devices are mixed and connected to the A-side and B-side SCSI may be used. In such a mixed system, S
Since all the CSI signals are bidirectional signals, the unidirectional signals listed in FIG. 19 can be exchanged between the devices without any problem by applying the bidirectional signal driving unit of FIG. 3 or 5.

Each of the interface relay devices 1a and 1b is said to have no terminating resistor connected to the SCSI on the A side. However, a switch is provided in the interface relay device to switch between presence and absence of the terminating resistor. May be.

If a part or all of the unidirectional signal driver, the bidirectional signal driver, and the terminating resistor of the interface relay device are realized by one or several LSIs, there is an advantage that the size and cost can be reduced. is there.

(Embodiment 2) FIG. 5 is an internal configuration diagram of a bidirectional signal drive unit (which drives a SEL-N signal) which constitutes an interface relay device of a disk array system according to another embodiment of the present invention. Is.

In FIG. 3, 300 in the output buffer unit 31,
301 indicates signals ASEL-N217 and BSEL-, respectively.
It is an open drain type output buffer for driving N216. 302 and 303 are A side and B side SELs, respectively
-An input buffer that receives the N signal. 320, 32
1, 322, 323 are AND (logical product) circuits, 328,
329 is an inverter (logical inversion) circuit, 326, 327
Is an SR flip-flop circuit, and 330 and 331 are shown in FIG.
A delay unit that delays a signal similar to 208 and 209 of
BSELDRVDLY-N332, ASELD respectively
Generate RVDLY-N333. BSEL-N216
And a signal BSELDRV- that drives ASEL-N217
P310 and ASELDRV-P311 are the outputs of the SR flip-flop circuits 326 and 327, respectively.

One input of 324 and 325 is RESET
-N and the other input is signal 334 and signal 335, which is a negative input OR circuit. RESET-N (active “L”) when power is turned on
The reset input 340 and the reset input 341 for the SR flip-flop circuits 326 and 327 are inactivated.

FIG. 6 is a time chart showing the operation of the bidirectional signal drive unit shown in FIG. In the figure, the signal ASEL-N
When 217 becomes active "L", signals 337, 33
Since both 3 are "H", the signal BSELDRV-P310 becomes active "H". Therefore, BSEL-N216
Becomes active "L". At this time, the signal ASELDR
The V-P 311 is inactive "L" because the signal 336 is "L". When the signal ASEL-N217 changes to inactive "H", the signal BSELDRV-P31
0 becomes inactive “L” and BSEL-N216
Becomes inactive "H". This time the signal BSEL-
When N216 goes active low, signals 336, 3
Since both 32 are "H", the signal ASELDRV-P311
Becomes active "H". Therefore, ASEL-N21
7 becomes active "L". At this time, the signal BSELD
The RV-P310 is inactive "L" because the signal 337 is "L". When the signal BSEL-N216 changes to inactive "H", the signal ASELDRV-P3
11 becomes inactive “L” and ASEL-N21
7 becomes inactive "H".

Therefore, ASEL-N217, BSEL-
When both of the N216 are inactive "H" and the host device 10 on the A side sets the signal ASEL-N217 to active "L", BSEL-N216 is active "L".
Becomes Then, the higher-level device 10 sends the signal ASEL-N21.
BSEL-N216 when 7 is set to inactive "H"
Becomes inactive "H". Similarly, when any one of the B-side lower devices 11 sets the signal BSEL-N216 to active "L", ASEL-N217 becomes active "L", and subsequently, the B-side lower device 11 outputs signal BS.
When EL-N216 is set to active "L", ASEL-
N217 becomes active "L". As a result, SEL
The signals are driven correctly.

The bidirectional signal driving section described above is operated by the signal SE.
Not only L-N1 but also other bidirectional signals BSY-N of FIG.
2, it can be applied to the drive of DXX-N3. Next, signal B
Another embodiment of the characteristics of the SY-N2 and its bidirectional signal driver will be described.

In SCSI, the signal BSY-N2 may become active "L" in the upper device 10 or the lower device 11 at the same time.

7 and 8 are timing charts showing the first and second examples of the SCSI timing, respectively. 7 and 8, the signals BSY-N2 are simultaneously active "L" in selection and reselection.
5 is added to the signal BSY-N2 (note that the signal numbers are in the 400s and the signal ABSYDRV is used).
-Corresponding to signals in the 300s of FIG. 5 as P411 corresponds to the signal ASELDRV-P311). The upper device BSY-N and the lower device BSY-N in FIGS. 7 and 8 indicate the signal BSY-N2 driven by the upper device and the lower device to "L", respectively. Further, the higher-level device SEL-N and the lower-level device SEL-N indicate a signal SEL-N1 driven by the higher-level device and the lower-level device to "L", respectively.

The reason why a whisker-like thin pulse is generated in the signal BBSY-N416 in the arbitration phase of FIG. 7, the arbitration phase of FIG. 8 and the information transfer phase will be described. In the arbitration phase of FIG. 7, when the lower device 11 changes the signal BSY-N2 from active "L" to inactive "H", the signal ABSYDRV-P411 becomes inactive "L" and the signal BBSY-N416 becomes It becomes inactive “H”. At this time, since the signal ABSY-N417 is driven by the host device 10 and is active "L", the signal BBSY-N416 passes through the delay time by the delay unit 331.
Becomes an active "L" again, so that it becomes a thin pulse (the signal BSY-N2 originally does not have a pulse as shown in FIG. 7). That is, in this circuit, the signal ABSY-N41
Among the 7 and BBSY-N 416, a noise pulse is generated when the signal that has become active first changes to inactive and the other signal is active. The pulse of FIG. 8 is also the same.

In fact, since the active period of the signal BSY-N2 is relatively long, such as several μs or more, the noise pulse can be removed when the signal is taken in the upper device 10 and the lower device 11. FIG. 9 is an internal configuration diagram showing an example of a noise absorbing unit provided inside the higher-level device 10 or the lower-level device 11 to absorb the noise. In the figure, 35
Reference numerals 0 and 351 are flip-flops, and 352 is an OR (logical sum) circuit. FIG. 10 is a timing chart for explaining the operation of FIG.

Signals ABSY-N354 and CLK-P35
From 3 to flip-flops 350 and 351, ABSYL
1-N355 and ABSYL2-N356,
The OR circuit 352 calculates the logical sum of these signals 355 and 356.
By taking the above, ABSYFL-N357 is output.

(Embodiment 3) FIG. 11 is an internal configuration diagram of a bidirectional signal drive unit constituting an interface relay device of a disk array system which is Embodiment 3 of the present invention. In this embodiment, the signal BSY-
A configuration in which no pulse is generated in the bidirectional signal drive unit of N2 will be described.

In the figure, 417 and 416 are the A side and B side, respectively.
Side signals BSY-N2, ABSY-N and BBSY-
N and 400 in the output buffer unit 41 are open drain type output buffers for driving the signals ABSY-N417 and BBSY-N416, respectively. 402
Input buffers 403 and 403 receive the BSY-N signals on the A side and the B side, respectively. 420, 421, 450, 4
51 is an AND (logical product) circuit, 428, 429, 45.
4, 455 are inverter (logical inversion) circuits, 422, 4
23, 452, 453 are OR circuits, 426,
427 is an SR flip-flop circuit, 430, 431
Is a delay unit for delaying a signal, similar to 208 and 209 in FIG.

One input of 424 and 425 is RESET
It is a negative input OR (logical sum) circuit with -N. When the power is turned on, the reset input 440 and the reset input 441 for the SR flip-flop circuits 426 and 427 are inactivated by RESET-N (active “L”).

A feature of this circuit is that the signal 482 is signal ABSY-N417 and signal BBSY when active "H".
A signal FBSYEN-P that forcibly activates both of -N416, and a signal 480 and a signal 481 forcibly make the signals ABSY-N417 and BBSY-N416 active "L", respectively. The signal RSLSTED-P and the signal SELSTRT-P. The other functions are the same as those of the drive signal generator 32 of FIG. The signal FBSYEN-P482 becomes active "H" from the arbitration phase to the start of selection or reselection. Signal RSLSTE
D-P480 is a signal generated at the start and end of reselection, and signal SELSTRT-P481 is generated at the start of selection.

12 and 13 are timing charts showing the operation of FIG. 11 during selection and reselection, respectively. In FIG. 12, the signal FBSYEN
-P482 and the signal SELSTRT-P481, the signal FBSYEN-P482 and the signal RSLS in FIG.
Due to the TED-P480, no pulse is generated in the signals ABSY-N417 and BBSY-N416. In addition,
FIG. 14 shows a part of the signals of FIG. 11 (signal FBSYEN-P4
82, signal RSLSTED-P480 and signal SEL
It is a block diagram which shows an example of a structure of the signal generation part which produces | generates STRT-P481). In FIG. 14, 470, 471, 4
73 and 474 are flip-flops with reset, 47
2, 475 and 476 are AND circuits, 477 is an OR circuit, 478 is a NOR circuit, and 461 and 479 are negative AND circuits.
Circuit, signal 462 is a clock signal, signal 463 is a reset signal (active “H” immediately after power-on), signal 46
Reference numeral 4 is an "H" fixed signal.

Next, the SCSI data bus DXX-N3
A bidirectional signal drive unit focusing on the above feature will be described.
The data bus DXX-N3 has an ID designating function in addition to the data content to be transferred. This drives the bit signal of the data bus corresponding to the ID number unique to the upper device 10 and the lower device 11 to "L". During the information transfer phase (from the change of the signal SEL-N1 from "L" to "H" to the change of the signal BSY-N2 to "H"), the signal DX
The direction of X-N3 is determined by the signal I / O-N5.

(Embodiment 4) FIG. 15 is an internal block diagram of a bidirectional signal driver which constitutes an interface relay device of a disk array system which is Embodiment 4 of the present invention. In this embodiment, the data bus DX
An example of a bidirectional signal driving unit that drives X-N3 will be described (actually, the number of bits of the data bus is required, but they are collectively described as one DXX-N3).

In the figure, 517 and 516 are the A side and B side, respectively.
Side DXX-N signals ADXX-N and BDXX-N
The reference numerals 500 and 501 in the output buffer section 51 are open drain type output buffers that drive the signals ADXX-N517 and BDXX-N516, respectively. Reference numerals 502 and 503 denote input buffers for receiving the DXX-N signals on the A side and the B side, respectively. 520,521,522,52
3, 565, 566 are AND (logical product) circuits, 528,
529 and 563 are inverter (logical inversion) circuits, 561
Is a NOR (logical inversion of OR) circuit, and 526 and 527 are S
R flip-flop circuits 530 and 531 are designated by 2 in FIG.
A delay unit 562 for delaying a signal as in 08 and 209.
Is a negative input AND (logical product) circuit, 540 and 541 are selectors, and 560 is an input buffer for receiving the signal BI / O-N5.

One input of 524 and 525 is RESET
It is a negative input OR (logical sum) circuit in which the other input is the signal 534 and the signal 535. When the power is turned on, SR is activated by RESET-N (active “L”)
The reset input for each of the flip-flop circuits 526 and 527 is made inactive.

The structure of FIG. 15 is characterized in that it has the same structure as the drive signal generator 32 of FIG. 5 in the case of the ID designating function, and the signal A by the data transfer direction controller in the case of the data transfer function.
The DXX-N517 and the BDXX-N516 are driven. That is, as the signal BDXXDRV-P510, when the select signal 516 of the selector 540 is "L" (ID designating function) and "H" (data transfer function), the signal 542 and the signal 567 are selected, respectively. Similarly, the signal ADX
As the XDRV-P 511, when the select signal 516 of the selector 540 is “L” (ID designating function) and “H” (data transfer function), the signal 543 and the signal 568 are selected, respectively. Here, the operation of the select signal 516 will be described. Since the signals 210, 211, 310, 311 are all inactive "L" in the bus-free state where there is no exchange of SCSI signals, the signal 514 becomes "H".
6 is "L". The signal 516 becomes “H” because the signal 550 changes from “L” to “H” at the start of the data transfer function in which the signal SEL-N1 changes from “L” to “H” (the signal 513 becomes “H”). Fixed signal).

The signal 515 is a SCSI signal I / O-N5.
The B side signal indicates the direction of the data transfer function. When the signal I / O-N5 is "L", the signal DXX-N3 at the time of the data transfer function is driven from the signal 519 of the lower device (B side) to the upper device 10 (A side) because of the input direction. In the case of H ", the signal 518 of the host device 10 (A side) is output because of the output direction.
Drive to the lower device 11 (B side).

In high-speed data transfer, the phase relationship between the SCSI signal data bus DXX-N3 and signal REQ-N7 or the data bus DXX-N3 and signal ACK-N9 becomes strict. Therefore, providing the signal delay adjustment unit 604 that can freely adjust these phases is useful for ensuring stable operation.

FIG. 16 is an internal block diagram showing an example of the signal delay adjusting section. In the figure, reference numeral 600 is a delay unit that delays the phase of a signal, and 601 is a selector that can select an arbitrary delay. Therefore, the output signal 603 can delay the input signal 602 by an arbitrary time. In fact, the signal delay adjuster 604 applies to signals 510, 511, etc. that drive output buffers (eg, 500, 501).

(Embodiment 5) Up to now, the electrical specification of the SCSI signal has been described for the case of the single end type. Another electrical specification, the differential type, consists of two (+) and (-) signals per SCSI signal, and the potential of the (+) signal is that of the (-) signal. Larger or smaller are active and inactive respectively. By replacing the input buffer and the output buffer with a differential (differential) type (converting + and − differential signals into digital signals) from the single-ended type, the interface relay device in the disk array system of the present invention can be operated as a differential (differential) type. It can also be applied to the differential type.

Hereinafter, the differential (differential) type S
The case where it is applied to a CSI signal will be described. Since driving of a unidirectional signal does not cause any particular problem because direction switching control is unnecessary, the bidirectional signal driving unit will be specifically described.

FIG. 17 shows a differential type signal on both the A side and the B side (signal SEL-N as an example,
It is an internal block diagram of the bidirectional signal drive part which drives (+) SEL-N and (-) SEL-N). In the figure, the single-ended type input buffer 202 / output buffer 200 and the input buffer 203 / output buffer 201 illustrated in FIG.
0b / differential type output buffer 1200a,
And differential input buffer 1201b /
It is replaced with a differential output buffer 1201a (for example, SN75LBC976 of TI LSI). Note that 1300 and 1301 are A
SELDRV-P1211, BSELDRV-P121
When 0 is active "H", it is a pull-up resistor for setting signals 1217 and 1216 for activating the differential output signal to "H". Other than that, the configuration of the drive signal generation unit 1022 is similar to that in the case of FIG.

When the interface relay device of this embodiment is applied to a differential (differential) type SCSI signal, the distance allowed between the upper device 10 and the lower device 11 (generally 25 m for the differential (differential) type).
This is effective in a system or the like that requires a longer length. In addition, by selecting the input buffer / output buffer, one of the A-side and B-side SCSI signals may be a differential (differential) type and the other may be a single-ended type, which allows free selection according to the system. .

(Embodiment 6) Next, the configuration of a disk array system will be described as an example of a storage device using the interface relay device illustrated in the above embodiments.

FIG. 18 is a conceptual diagram showing an example of a configuration in which the interface relay device of this embodiment is applied to a disk array system constructed by connecting a large number of small magnetic disk devices by a SCSI interface. .

In FIG. 18, reference numeral 701 denotes a host control unit for exchanging data with the host computer 700.
Reference numeral 703 denotes a cache memory unit for holding the data of the lower device, 702 receives the data from the host control unit 701 when writing the data from the host computer 700 to the lower device, and distributes it to many SCSI systems,
When reading data from a lower device, a large number of SCSI
A device control unit that receives data from the system and sends the data to the host control unit 701. Reference numeral 704 is an SCS that accesses a lower-level device via an interface relay device.
I interface control unit (corresponding to the host device 10 in FIG. 1), 705 and 706 are interface relay devices, 7
Reference numerals 10 to 71N or 720 to 72M are subordinate devices such as small magnetic disk devices.

Thus, the interface relay device 70
5, 706 by interposing an arbitrary number between the SCSI interface control unit 704 and the lower devices 710 to 71N and the lower devices 720 to 72M.
The restrictions on the number of connected devices and the restrictions on the connection distance between devices due to the I interface standard have been resolved, and a large number of small magnetic disk devices, etc. can be connected to facilitate an external storage device such as a large-scale disk array system. Can be built.

(Embodiment 7) FIG. 20 is a conceptual diagram showing an example of the configuration of an information processing apparatus incorporating the interface relay apparatus of the present invention.

In the case of this embodiment, the host device 10 and
A plurality of interface relay devices 801 and 802 are connected in series between the plurality of lower device 11 and the interface relay device 802 located at the final end when viewed from the upper device 10 side is connected to the plurality of lower devices. 1
1 is connected. As a result, by increasing the number of interface relay devices 801 on the way as necessary, there is an advantage that the distance from the upper device 10 to the lower device 11 can be increased without being restricted by a specific interface standard. .

In the above description of each embodiment, the case where the present invention is applied to SCSI as an example of the interface has been described, but the present invention is not limited to SCSI and is effective for all interfaces that can be connected in a potato-like manner. .

[0082]

According to the interface relay device of the disk array system of the present invention, it is possible to accurately relay the bidirectional interface signal without increasing the number of interface signals.

Further, by improving the quality (noise margin) of the interface signal, it is possible to obtain the effect that stable operation can be secured.

Further, the effect that the stable transmission distance of the interface signal can be increased and the distance limitation of the arrangement of the device can be eliminated is obtained.

By preventing the interface signal from deteriorating, it is possible to increase the number of connected devices.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing an example of a configuration of a disk array system including an interface relay device according to a first embodiment of the present invention.

FIG. 2 is an internal configuration diagram of an interface relay device of the disk array system that is Embodiment 1 of the present invention.

FIG. 3 is an internal configuration diagram of a bidirectional signal drive unit that constitutes an interface relay device of the disk array system that is Embodiment 1 of the present invention.

FIG. 4 is a time chart diagram showing an example of the operation of the bidirectional signal drive unit that constitutes the interface relay device of the disk array system that is Embodiment 1 of the present invention.

FIG. 5 is an internal configuration diagram of a bidirectional signal drive unit that constitutes an interface relay device of a disk array system that is Embodiment 2 of the present invention.

FIG. 6 is a time chart diagram showing an example of the operation of a bidirectional signal drive unit that constitutes an interface relay device of a disk array system that is Embodiment 2 of the present invention.

FIG. 7 is a timing chart showing an example of an operation when relaying a SCSI interface signal by an interface relay device of a disk array system which is Embodiment 2 of the present invention.

FIG. 8 is a timing chart showing an example of an operation when relaying a SCSI interface signal by the interface relay device of the disk array system which is Embodiment 2 of the present invention.

FIG. 9 is an internal configuration diagram showing an example of a noise absorbing unit that absorbs noise.

FIG. 10 is a timing chart illustrating an example of the operation of the noise absorbing unit.

FIG. 11 is an internal configuration diagram of a bidirectional signal drive unit that constitutes an interface relay device of a disk array system that is Embodiment 3 of the present invention.

FIG. 12 is a timing chart showing an operation at the time of selection in the relay operation of the SCSI interface signal by the interface relay device of the disk array system which is Embodiment 3 of the present invention.

FIG. 13 is a timing chart showing an operation at the time of reselection in the relay operation of the SCSI interface signal by the interface relay device of the disk array system which is Embodiment 3 of the present invention.

FIG. 14 shows an example of a signal generation unit that generates a part of the signals that are input to the drive signal generation unit of the bidirectional signal drive unit that constitutes the interface relay device of the disk array system that is Embodiment 3 of the present invention. It is a block diagram.

FIG. 15 is an internal configuration diagram of a bidirectional signal drive unit that constitutes an interface relay device of a disk array system that is Embodiment 4 of the present invention.

FIG. 16 is an internal configuration diagram showing an example of a signal delay adjustment unit configuring an interface relay device of a disk array system that is Embodiment 4 of the present invention.

FIG. 17 is an internal configuration diagram showing an example of a signal delay adjustment unit constituting an interface relay device of a disk array system which is Embodiment 5 of the present invention.

FIG. 18 is a conceptual diagram showing an example of the configuration of a disk array system including the interface relay device of the present invention.

FIG. 19 is an explanatory diagram showing functions of various signals forming a wide SCSI interface.

FIG. 20 is a conceptual diagram showing an example of the configuration of an information processing apparatus incorporating a disk array system including the interface relay apparatus of the present invention.

FIG. 21 is a configuration diagram showing an outline of a conventional SCSI system.

[Explanation of symbols]

1a, 1b ... Interface relay device, 10 ... Upper device, 11 ... Lower device, 12 ... SCSI signal, 12
a ... Cable, 13a, 13b ... Motherboard, 18 ... SCSI signal, 18a, 18b ... Wiring pattern, 20 ... Bidirectional signal drive section, 21 ...
Output buffer unit, 22 ... Drive signal generation unit, 23, 2
4 ... Unidirectional signal driver, 25, 26 ... Terminator.

Front page continuation (72) Inventor Kenji Kubota 2880, Kozu, Odawara-shi, Kanagawa Hitachi Storage Systems Business Department (72) Inventor Tsuneo Hirose, 2880, Kozu, Kanagawa Prefecture Hitachi Storage Systems Business Department (72) Inventor Tatsuya Ninomiya 2880, Kozu, Odawara-shi, Kanagawa Hitachi Storage Systems Business Division (72) Inventor Kazunori Sanshin 2880, Kozu, Odawara, Kanagawa Hitachi Computer Equipment Co., Ltd. (72) Kazuhiko Ikeda 2880 Kozu, Odawara-shi, Kanagawa Hitachi Computer Equipment Co., Ltd. (56) Reference JP-A-6-60014 (JP, A) JP-A-54-129845 (JP, A) JP-A-52-153313 (JP, A) ) Japanese Patent Laid-Open No. 4-33041 (JP, A) Actually open 6-19032 (JP, U) Actually open 62-201862 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 13/36 310

Claims (11)

(57) [Claims] 1. A system having a substrate having a plurality of connectors interconnected by wiring and a plurality of disk devices provided on the connector and connected to the wiring, and controlling data transfer to the disk device. A device control unit, a cable connecting between the device control unit and the system, an end provided in the system and electrically connected to the wiring, and electrically connected to the cable A signal drive device including the other end side, the signal drive device logically interconnects the wiring and the cable, and is bidirectionally transmitted and received between the device control unit and the disk device. And a function to drive deterioration of the signal caused by the plurality of disk devices without the signal driving device. Disk array system. 2. The disk array system according to claim 1, wherein the signal driver is mounted on a substrate having the wiring. 3. The disk array system according to claim 1, wherein the signal driver identifies a transmission direction of the signal. 4. A SCSI connection is provided between the device control unit and the signal drive device, and between the signal drive device and the disk device.
Alternatively, the disk array system according to item 3. 5. The disk array system according to claim 2, wherein the other end of the signal driving device is connected to the cable via a connector. 6. The disk array system according to claim 2, wherein one end side of the signal driving device is connected to a connector on the substrate, and is connected to the wiring via the connector. 7. A signal is transmitted between the device control unit and a plurality of disk devices in the system, and between the device control unit and the plurality of disk devices, and the disk device is connected to the device control unit by a cable. A signal driving device connected to one end side of the cable, provided near the plurality of disk devices, and connecting the other end side of the cable to the device control unit; A drive device is used to drive a signal transmitted from the device control unit to each of the plurality of disk devices, and the deterioration of the signal that would otherwise be caused by the plurality of disk devices is suppressed. The signal drive device is used to drive a signal transmitted from each of the plurality of disk devices to the device control unit, Method of transmitting a signal, characterized in that to suppress deterioration of the signal device will be caused if the plurality of disk devices without. 8. The method of transmitting a signal according to claim 7, wherein when the signal driving device is provided, the signal driving device and the plurality of disk devices are provided on a substrate. 9. A system having a plurality of connectors interconnected by wiring, a substrate having the plurality of connectors, and a plurality of disk devices provided on the connector on the substrate and connected by the wiring. A device control unit that controls data transfer to the disk device; a cable that connects the device control unit and the system; and an electrical connection between the wiring and the cable that is provided in the system. Signal for driving a signal bidirectionally transmitted and received between the disk device and the device control unit, and suppressing deterioration of the signal caused by the plurality of disk devices without a signal drive device. A disk array system comprising a drive device. 10. The disk array system according to claim 9, wherein the signal driver is mounted on a substrate having the wiring. 11. The disk array system according to claim 9, wherein the signal driver identifies a transmission direction of the signal.