JP3487697B2 - Interpolation processing circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interpolation processing circuit which can obtain relative position information finer than the pitch of the original encoder by using an encoder or the like which outputs two-phase signals.

[0002]

2. Description of the Related Art For example, precise position detection / control is required in various fields such as motor rotational position control, electronic component mounting, NC processing, semiconductor mask, printing, image processing, and the like. An encoder is widely used as a position detecting means in the. When the pitch of the encoder is sufficiently small with respect to the positioning accuracy required for the apparatus, the output of the encoder can be made into two sets of rectangular waves and the position of the positioning target can be detected by combining with the reversible counter. When higher position detection accuracy is required, there is a limit to the fineness of the encoder pitch. Therefore, the encoder output is converted into a two-phase sinusoidal signal, and the encoder undergoes the position modulation and phase modulation processes. A method of taking out the position detection accuracy equal to or less than the pitch of is taken. The interpolation processing circuit performs this processing.

The circuit configuration of the conventional interpolation processing circuit shown in FIG. 7 will be described below. 701 is an encoder,
ea and eb are signals output from the encoder 701.

Reference numerals 702 and 703 are amplifiers for amplifying the output signal from the encoder 701. Reference numerals 704 and 705 are amplifiers 7.
Encoder 7 amplified by 02 and 703, respectively
This is a modulator that amplitude-modulates the output from 01 with carrier signals Sa and Sb output from the carrier generator 710. ma and mb are amplitude-modulated signals output from the modulators 704 and 705. An adder 706 performs addition processing on the amplitude-modulated signals ma and mb using the carrier signal Sc output from the carrier generator 710. A filter 707 removes unnecessary components from the signal added by the adder 706. 708
Is a waveform shaper that shapes the signal from which unnecessary components have been removed by the filter 707 into a rectangular wave. Reference numeral 709 denotes a signal output from the waveform shaper 708 and the carrier generator 71.
It is a phase information demodulator that performs phase comparison with a carrier signal output from 0 and demodulates phase information.

The following is a conventional example (Japanese Patent Laid-Open No. 2-248816).
No.) operation.

The outputs ea and eb of the encoder 701 can be expressed by equations (1) and (2).

Ea = Asin θ (1) eb = A cos θ (2) where A is the amplitude of the amplified encoder output, and θ is the phase of the encoder output signal.

Since the first and second carrier signals Sa and Sb output from the carrier generator 710 are rectangular waves, when expanded to Fourier series, (3),
It can be expressed by equation (4), and a to f shown in FIG. 8 are High.
Switch connection is made to a, b, c, d, e and f in FIG.

Sa = C · {cosωt) -1 / 3 · cos3ωt + ...} (3) Sb = C · {sinωt) -1 / 3 · sin3ωt + ...} (4) where , C is the amplitude of the carrier signal, ω is the carrier angular frequency, and t is time.

The signals ma and mb modulated by the first and second carrier signals Sa and Sb can be expressed by equations (5) and (6), respectively.

Ma = ea · Sa = A · C · sin θ · {cosωt-1 / 3 · cos3ωt + ··) (5) mb = eb · Sb = A · C · cos θ · {sinωt-1 / 3 .Sin3.omega.t + ..) (6) Here, the signal m modulated by the carrier signals Sa and Sb
a and mb are R of the adder 706 depending on the carrier signal Sc.
a, Rb, Rc are added at the ratio determined by the resistance value,
It is output as the signal mc. Output signal m of adder 706
c is mc = (Rb + Rc) / (Ra + Rb + Rc) .ma + Ra / (Ra + Rb + Rc) .mb. (71) when the arm of the switch 26 is tilted to the e side in FIG. When falling to the f side, the following formula is obtained.

Mc = Rb / (Ra + Rb + Rc) -ma + (Ra + Rc) / (Ra + Rb + Rc) -mb ... (72) Encoder outputs ea and eb have the same amplitude and Ra
= Rb, the output of the adder 706 is Ra + Rc:
It changes with the ratio of Ra and Ra: Ra + Rc.

The output mc obtained by the addition processing with the carrier signal Sc can be expressed by the equation (7).

Mc = ma + mb = AC {sin (ωt + θ) + 1 / 3sin (3ωt-θ) + ...} (7) FIG. 9 shows a signal ma modulated with a carrier signal, mb and the output mc of the adder are shown.

From the output mc of the adder, it can be seen from the equation (7) that the phase of the component of the first term is phase-modulated by the displacement of the phase difference with respect to the frequency of the carrier signal.

However, the components after the second term are harmonic components, and it can be seen that unnecessary components remain in the modulated carrier signal mc, as shown in FIG. 9 (c). Here, in order to extract only the component of the first term, a filter 707 having a sharp amplitude characteristic removes an unnecessary component of higher order,
By extracting only the component of the first term and detecting the phase difference between the component of the first term and the carrier signal Sa, the position of the object can be detected.

[0017]

However, in the above-mentioned conventional interpolation processing circuit, although the addition ratio is switched by the carrier signal Sc, many unnecessary harmonic components remain, so that the conventional interpolation processing is configured. However, there was a problem in designing the filter.

Unnecessary components that have not been completely removed by the filter appear as a decrease in position information. Further, since it is necessary to remove high-order unnecessary components when constructing the filter, it is necessary to make the amplitude characteristic of the filter steep. However, when such an amplitude characteristic is used, the phase characteristic deteriorates and an error occurs in the detection of position information due to the phase delay.

The present invention has been made in view of the above problems. By reducing unnecessary signals from the signal from the encoder output signal to the filter input, the load on the filter is reduced and the phase characteristics of the filter are improved. However, the purpose is to enable highly accurate position information detection.

[0020]

In order to solve the above-mentioned problems, the interpolation processing circuit of the present invention (claim 1) has a first phase and a second phase which are different in phase depending on the position of the object. With an encoder that outputs the signal of
Switch switching signal generating means for generating second, third, and fourth switch switching signals, and the first encoder output signal and its inverted output signal according to the first switch switching signal output from the switch switching signal generating means. The encoder output signal and its inverted output in n stages (n is 2) in accordance with the third switch switching signal output from the switch switching signal generating means while switching
A first voltage division ratio switching means for dividing and outputting the ratio while switching the ratio to the above integer), and the second encoder output signal and its inverted output according to the second switch switching signal output by the switch switching signal generating means. The encoder output signal and its inverted output are n stages (n is 2) in accordance with the fourth switch switching signal output from the switch switching signal generating means while switching the signal.
Second dividing ratio switching means for dividing and outputting while switching the ratio to the above integer), adding means for adding respective output signals of the first and second dividing ratio switching means, and the first or first The phase information detecting means for detecting the phase of the output signal of the adding means based on the switch switching signal of No. 2 is provided.

In the interpolation processing circuit according to the second aspect of the present invention, the first and second second circuits having different phases depending on the position of the object.
In accordance with an encoder for outputting a phase signal, a switch switching signal generating means for generating first and second switch switching signals at a predetermined timing, and a first switch switching signal output by the first switch switching signal generating means. The first encoder output signal and the inverted output signal thereof are divided into 2n levels (n is an integer of 2 or more) while dividing the voltage, and a voltage switched by the switch switching signal is output. 2n stages (n is an integer of 2 or more) between the second encoder output signal and its inverted output signal according to the second switch switching signal output from the voltage division ratio switching means and the second switch switching signal generating means. ), The second voltage division ratio switching means for dividing the voltage while switching the ratio to output the voltage switched by the switch switching signal. , Adding means for adding the respective output signals of the first and second voltage division ratio switching means, and phase information detection for detecting the phase of the output signal of the adding means with reference to the first or second switch switching signal. It is characterized by comprising means.

In the first and second inventions,
It is preferable that the n-step or 2n-step voltage division ratio is switched at a predetermined ratio based on a trigonometric function.

According to the present invention, the harmonic component contained in the output signal of the adding means can be reduced and the phase detection error can be reduced by the configuration of the above-mentioned claim 1 or 2.

In particular, the first and second encoder outputs are divided into n stages (n is an integer of 2 or more) or 2n stages at a predetermined ratio based on a trigonometric function, and output.
By adding each output of the division ratio switching means of
As an output signal of the adding means, it is possible to obtain a waveform that includes phase information and is approximately a sine wave.

In this case, by increasing the value of n, the output signal of the adding means can be made closer to a sine wave, and therefore the harmonic component contained in the output signal of the adding means becomes smaller. Therefore, even if the amplitude characteristic of the filter is made gentle, unnecessary components can be removed and the phase characteristic can be improved. Therefore, the detection error of the phase detection means for detecting the phase of the output signal of the addition means on the basis of the switch switching signal is reduced, and the detection accuracy of the position particularly when the object is moved is improved.

[0026]

DETAILED DESCRIPTION OF THE INVENTION

(Embodiment 1) FIG. 1 is a circuit diagram of an interpolation processing circuit according to Embodiment 1 of the present invention. In FIG. 1, 101 is an encoder, which outputs two-phase signals ea and eb whose phases are different from each other by 90 ° depending on the position of the object. 102, 1
Reference numeral 03 denotes an amplifier, which is a two-phase encoder output ea, e
b is amplified respectively. Amplifiers 10 and 104 are provided with switch switching signals Sa, Sb, Sc and Sd output from the switch switching signal generating means 110.
The first and second voltage division ratio switching means divides the two-phase output of the encoder 101 amplified by 2, 103 and its inverted output into n stages (n is an integer of 2 or more). 106
Is addition means for adding the outputs of the first and second voltage division ratio switching means 104, 105. 107 is addition means 1
This is a filter for removing high frequency components from the output signal of 06. Reference numeral 108 denotes a waveform shaper that shapes the signal from which unnecessary components have been removed by the filter 107 into a rectangular wave. Reference numeral 109 is a phase information detecting means for detecting a phase by performing a phase comparison between the signal output from the waveform shaper 108 and the signal Sa output from the switch switching signal generating means 110. It should be noted that the phase comparison may be performed with Sb instead of Sa, and specifically, the phase comparison is performed between the rectangular wave output of Sa or Sb and the output of the waveform shaper 108.

The operation of the present invention will be described below. The encoder 101 outputs two-phase signals having 90 ° different phases according to the position of the object, and outputs Asinθ and Acosθ amplified by the amplifiers 102 and 103, respectively.

In FIG. 1, the first voltage division ratio switching means 104 includes a forward rotation buffer 120, a reverse rotation buffer 121,
It is composed of a two-contact analog switch 122 and a four-contact analog switch 123. Similarly, the second voltage division ratio switching means 105 includes a forward rotation buffer 124, a reverse buffer 125, a 2-contact analog switch 126, and a 4-contact analog switch 127.

In FIG. 1, Sa, Sb, Sc, and Sd are the first, second, third, and fourth switch switching signals, respectively, and these signals determine the switch switching timing as shown in FIG. FIG. 2 shows the timing at which the first and second voltage division ratio switching means 104, 105 perform switching. That is, each switch terminal a in FIG.
It is shown that the switches are connected to b, c, d, e, f, g, h, i, j, k, and l during the period of the high level shown in FIG.

Here, the horizontal axis represents time, and the time from T0 to T16 shown in FIG. 2 is one cycle, and the timing of T0 is the basis for phase comparison.

FIG. 3A shows that the first voltage division ratio switching means 104 switches the output of the forward rotation buffer 120 or the reversal buffer 121 in four stages according to the switch switching signal. ma indicates the output of the voltage division ratio switching means 104. R1 in FIG.
The resistances of the resistors R2, R3, and R4 are determined so that the amplified encoder output signal is divided into four stages at a ratio based on a trigonometric function. Here, the amplified encoder output signal becomes a signal that is resistance-divided and output at the timing shown in FIG. 2, and its output becomes ma. First
The output ma of the voltage division ratio switching means 104 can be approximated to the waveform shown in the equation (8) by resistance division of the ratio based on the switch switching signals Sa and Sc and the trigonometric function.

Ma = Asin θ · cos ωt (8) Here, ω is the angular frequency thereof, where t0 to T16 in FIG. 2 is one cycle, and t is time.

Similarly, FIG. 3B shows that the second voltage division ratio switching means 105 is switching the voltage division ratio by the switch switching signals Sb and Sd, and the output of the voltage division ratio switching means is mb. is there. Every time the switch is switched as shown in FIG. 2, the output mb of the second voltage division ratio switching means 105, which is divided and output, is approximated by the resistance switching of the ratio based on the switch switching signals Sb and Sd and the trigonometric function. Can be approximated to the waveform shown in equation (9).

Mb = Acos θ · sin ωt (9) 106 is the first and second voltage division ratio switching means 104, 1
The addition means 05 adds the outputs ma and mb of 05. FIG. 3C shows the output signal after addition by the adding means 106. Here, the output signal mc of the adding means 106 is 1/2 ·
(Ma + mb), which is expressed by the following equation (10),
It can be seen that the phase information is included.

Mc = 1 / 2 (ma + mb) = 1 / 2Asin (ωt + θ) (10) 107 is a filter that removes high frequency components from the output signal of the adding means 106. Reference numeral 108 denotes a waveform shaper that shapes the signal from which unnecessary components have been removed by the filter 107 into a rectangular wave. Reference numeral 109 denotes a signal including phase information output from the waveform shaper 108 and the switch switching means 11
It is a phase information detecting means for detecting the phase by performing a phase comparison with the switch switching signal Sa of 0, and the phase difference can be detected from the signal output from the waveform shaper 108.

FIG. 3C showing the output signal of the adding means of the present embodiment and FIG. 9 showing the output signal of the adding means of the conventional example.
As is clear from the comparison of (c), it can be seen that the output signal mc of the adding means of the present invention approaches a sine wave waveform.

As described above, the output of the adding means 106, which is obtained by adding the respective output signals ma and mb of the first and second voltage division ratio switching means 104 and 105, which are divided and output in n stages each time the switch is switched. Since the signal mc can be approximated to a sine wave, by increasing the number of voltage divisions of the voltage division ratio switching means 104 and 105, the signal mc can be further approximated to a sine wave waveform, and harmonic components can be reduced. Since the phase characteristic of the filter 107 can be improved, the position of the object can be detected with high accuracy.

(Second Embodiment) Next, a second embodiment of the present invention will be described. The circuit configuration shown in FIG.
Operations similar to those in the embodiment can be performed. Below, FIG.
The circuit configuration in will be described.

In FIG. 4, reference numeral 401 denotes an encoder, which has a phase difference of 90 ° depending on the position of the object.
Output the phase signal. 402 and 403 are amplifiers,
The two-phase outputs from the encoder 401 are amplified respectively. Reference numerals 404 and 405 denote switch switching signals Sa and S output from the switch switching signal generating means 410.
b, Sc, and Sd divide the voltage between the encoder output amplified by the amplifiers 402 and 403 and its inverted output into n steps to output the voltage switched by the switch switching signal. It is a pressure ratio switching means.

Reference numeral 406 is an adding means for adding the outputs of the first and second voltage division ratio switching means 404, 405. A filter 407 removes high frequency components from the output signal of the adding unit 406. 408 is a filter 407
It is a waveform shaper that shapes a signal from which unnecessary components are removed into a rectangular wave. Reference numeral 409 is a phase information detecting means for detecting a phase by performing a phase comparison between the signal output from the waveform shaper 408 and the carrier output (rectangular wave shaping output of the signal Sa or Sb) output by the switch switching signal generating means 410. Is.

In FIG. 4, first and second voltage division ratio switching means 404 and 405 are analog switches 420 and 424 having four contacts, forward rotation buffers 421 and 425, respectively.
It is composed of inverting buffers 422 and 426 and two-contact analog switches 423 and 427.

The switch switching signals Sa, Sb, Sc,
The timing of Sd is the same as that of the first embodiment, and the outputs ma and mb of the first and second voltage dividing ratio switching means 404 and 405 and the output mc of the adding means are the same as those of the first embodiment. .

As described above, in the second embodiment, the position of the object can be detected with high precision as in the first embodiment. However, as shown in FIG. 4, a four-contact analog switch 420 for resistance voltage division is used. After 424, the forward rotation buffers 421, 42
5 and the inversion buffers 422 and 426 are placed, and the switching of the two-contact analog switches 423 and 427 is performed by the switch switching signals Sa and Sb. For this reason,
In the first embodiment, the two-contact analog switch 1 shown in FIG.
When the ON resistances of 22 and 126 vary, the first voltage division ratio switching means 104 and the second voltage division ratio switching means 105.
Since there is a difference in the amplitude of each output signal, the detection accuracy of the position of the object may deteriorate. On the other hand, in the circuit configuration of the second embodiment of FIG. 4, the analog switch 42 is increased by increasing the resistance value of the resistor R5 of the adding means 406.
It is possible to obtain the effect of reducing the influence of variations in the on-resistances of Nos. 3 and 427.

(Third Embodiment) FIG. 5 is an interpolation processing circuit diagram of a third embodiment of the present invention. Also in the circuit configuration shown in FIG. 5, the same operation as that of the first embodiment can be performed. The circuit configuration of this embodiment will be described below.

In FIG. 5, reference numeral 501 denotes an encoder, which outputs two-phase signals having different 90 ° phases according to the position of the object. Reference numerals 502 and 503 denote amplifiers, which amplify the encoder output. Reference numerals 504 and 505 denote 2 between the encoder output amplified by the amplifiers 502 and 503 and the inverted output thereof by the switch switching signals Sa and Sb output from the switch switching signal generating means 510.
It is the first and second voltage division ratio switching means for dividing the voltage into n stages and outputting the voltage switched by the switch switching signal. Reference numeral 506 is addition means for adding the outputs of the first and second voltage division ratio switching means 504, 505. Reference numeral 507 is a filter for removing high frequency components from the output signal of the adding means 506. 508 is a filter 5
It is a waveform shaper that shapes a signal from which unnecessary components have been removed from 07 into a rectangular wave. 509 is a signal output from the waveform shaper 508 and a switch switching signal generating means 510.
Is a phase information detecting means for detecting the phase by performing a phase comparison with the carrier output (rectangular wave shaping output of the signal Sa or Sb).

In FIG. 5, the first voltage division ratio switching means 504 includes a forward rotation buffer 520, a reverse rotation buffer 521,
And an analog switch 522 having eight contacts. Similarly, the second voltage division ratio switching unit 505 is composed of a forward rotation buffer 523, a reverse buffer 524, and an analog switch 525 having eight contacts.

FIG. 6 shows switch switching signals Sa and Sb.
The first and second voltage division ratio switching means 504,
Reference numeral 505 indicates the timing of switching. Here, the switch switching timing of FIG. 6 is determined by Sa and Sb. In FIG. 6, the corresponding switch terminals a, b, c of FIG.
d, e, f, g, h, i, j, k, l, m, n, o, p
Indicates that the switch is connected to. Here, the horizontal axis represents time, and the time from T0 to T16 shown in FIG. 6 is set as one cycle, and the timing of T0 serves as a reference when performing phase comparison, for example.

R1, R2, R3, R4, R5, R in FIG.
6, the resistance division ratio of R7 is determined so that the voltage between the amplified encoder output and its inverted output is approximated to a sine wave in eight steps. The output signals ma and mb of the first and second voltage division ratio switching means 504 and 505 and the output signal mc of the adding means 506 are the same as in the first embodiment.

In the circuit configuration of the third embodiment shown in FIG. 5, as compared with the case of the first embodiment, the analog switches 122 and 1 of the two contacts of the voltage division ratio switching means 104 and 105 shown in FIG.
Since 26 is not used, the effect of compensating for the drawbacks of the first embodiment described in the second embodiment can be obtained.

In the above description, the encoder output is described as a case of two phases, but the present invention can be easily extended to a case of three phases.

[0051]

As described above, according to the present invention, the output signal of the adding means for adding the respective output signals of the first and second voltage division ratio switching means can be made close to a sine wave by the above-mentioned configuration, Since the harmonic components can be reduced,
Even if the amplitude characteristic of the filter is made gentle, the unnecessary component can be sufficiently removed.

Therefore, the interpolation processing circuit of the present invention can accurately detect the position of an object regardless of whether the object is stationary or moving.

[Brief description of drawings]

FIG. 1 is a circuit configuration example diagram of an interpolation processing circuit according to a first embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the switch change timing of FIG.

FIG. 3 is an output signal m of first and second voltage division ratio switching means.
Explanatory drawing of a, mb, and addition output mc of both.

FIG. 4 is a circuit configuration example diagram of an interpolation processing circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit configuration example diagram of an interpolation processing circuit according to a third embodiment of the present invention.

FIG. 6 is an operation explanatory diagram of the switch change timing of FIG. 5;

FIG. 7 is a circuit configuration diagram of a conventional interpolation processing circuit.

FIG. 8 is an operation explanatory diagram of the switch change timing of FIG. 7;

FIG. 9: Output signals ma and mb of modulator and adding means 10
Explanatory drawing of addition output mc of both according to 6.

[Explanation of symbols]

101, 401, 501 Encoder 102 103 402 402 403 502 503 Amplifier 104 105 404 405 504 505 Voltage division ratio switching means 106 406 506 Addition means 107 407 507 Filter 108 408 508 Waveform shaper 109 409 509 Phase information demodulation means 110 410 510 510 Switch switching Signal generation means

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Claims (3)

(57) [Claims] 1. An encoder that outputs first and second two-phase signals having mutually different phases according to the position of an object, and first, second, third, and fourth switch switching signals at predetermined timings. Switch switching signal generating means for making
In accordance with a third switch switching signal output from the switch switching signal generating means while switching between the first encoder output signal and its inverted output signal in accordance with the first switch switching signal output from the switch switching signal generating means. A first voltage division ratio switching means for dividing and outputting the encoder output signal and its inverted output while switching the ratio in n stages (n is an integer of 2 or more);
In accordance with a fourth switch switching signal output from the switch switching signal generating means while switching between the second encoder output signal and its inverted output signal in accordance with the second switch switching signal output from the switch switching signal generating means. Second voltage division ratio switching means for dividing the encoder output signal and its inverted output while switching the ratio in n stages (n is an integer of 2 or more), and outputting the divided voltage.
Adder means for adding the output signals of the first and second voltage division ratio switching means, and phase information detecting means for detecting the phase of the output signal of the adding means with reference to the first or second switch switching signal. An interpolation processing circuit comprising: 2. An encoder that outputs first and second two-phase signals whose phases are different from each other according to the position of an object, and a switch switching signal generator that generates first and second switch switching signals at a predetermined timing. Means and the first encoder output signal and its inverted output signal according to the first switch switching signal output from the first switch switching signal generating means in a ratio of 2n stages (n is an integer of 2 or more) And a second switch switching signal output from the second switch switching signal generating means, the first voltage dividing ratio switching means outputting the voltage switched by the switch switching signal and the second switch switching signal output from the second switch switching signal generating means. Of the encoder output signal and the inverted output signal thereof while switching the ratio in 2n steps (n is an integer of 2 or more). Second voltage division ratio switching means for outputting the voltage switched by the switching signal, addition means for adding the output signals of the first and second voltage division ratio switching means, and the first or second switch switching An interpolation processing circuit comprising phase information detecting means for detecting the phase of the output signal of the adding means on the basis of a signal. 3. The interpolation processing circuit according to claim 1, wherein the division ratios of the n stages or 2n stages are switched at a predetermined ratio based on a trigonometric function.