JP3485854B2 - Function Reconfigurable Integrated Circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit whose function function can be reconfigured. In particular, even after manufacturing, any symmetric function function can be configured in the integrated circuit. The present invention relates to an integrated circuit which can be combined with a selector function.

[0002]

2. Description of the Related Art FPGA (Field Programmable Gate Ar)
Ray) and PLD (Programmable Logic Device) typified by logic function reconfigurable devices have come to be used in various places as their scale increases.

At the beginning of its appearance, it was mainly used in the realization of parts for which a wide variety of products and only a small amount were required, or in the situation of prototyping, but nowadays
SIC (Application Specific Integrated Circuit)
It is often incorporated into the final product instead of. F
Even with PGA, the desired performance is sufficiently satisfied, and the product can be shipped to the time-to-market several months earlier than the ASIC.

Further, research and development of a reconfigurable computing system (Reconfigurable Computing System) capable of adaptively changing the hardware configuration in accordance with an application by using a logical function reconfigurable device has begun to become active.

In this logical function reconfigurable device, there are various structures for realizing variable logic, and a table reference (LUT: Look-Up Table) using the SRAM shown in FIG. 25 as the variable logic unit is provided. 26, a multiplexer type using an antifuse shown in FIG. 26, and a PLA (Programmable Logic Array) type that realizes a product-sum logic by using the EPROM or EEPROM shown in FIG.

Among them, the LUT type is large-scale and highly flexible and is widely used.

In the LUT type logic function reconfigurable device, the LUT realized by the SRAM is used for the variable logic unit to realize an arbitrary k input variable logic function. As shown in FIG. 28, the SRAM cell that constitutes the variable logic portion is usually composed of six transistors. k
The input variable LUT requires 2 ^k SRAMs, and the number of transistors is 6 × 2 ^k in cells alone.

The input variable k of a generally used LUT type FPGA is often 4 or 5. The LUT with the input variable k = 4 requires 96 transistors only in the SRAM cell, and the LUT with the input variable k = 5.
Then, 192 transistors are required. In addition, peripheral circuits such as an address decoder, a write circuit, a precharge circuit, and a sense amplifier are also required, and the circuit scale is large.

As described above, the LUT type FPGA has a problem that the circuit scale is large, and a problem that the variable logic portion occupies a large area on the LSI. Therefore, the advent of a variable logic unit having a small area is desired.

On the other hand, an arithmetic operation circuit is frequently used in a microprocessor (μP), which is a typical example of a logic LSI, and an arithmetic unit (data path unit) of a digital signal processor (DSP). ing. This arithmetic operation circuit is an addition circuit, a subtraction circuit, a multiplication circuit, or the like, and these arithmetic operation circuits often use full adders that are symmetric functions.

Here, the above-mentioned "symmetrical function" means a logical function whose function value does not change even if the input variables are arbitrarily replaced. For example, even if the values of the two inputs X1 and X2 of the 2-input AND are exchanged, the output value is the same. Examples of symmetric functions include AND, OR, NAND, NOR,
There are XOR, XNOR, etc. The symmetric function is described in, for example, “Logical Design Switching Circuit Theory: Tsutomu Sasao: Modern Science Co., Ltd., pp. 84-85”.

Further, in the control section of the logic LSI, a circuit using a selector function is often used.

As described above, in a logic LSI, a circuit having a symmetric function function and a circuit having a selector function are used very frequently, except for a sequential circuit including a register, a latch and the like.

The LUT type FPGA can represent any Boolean function, but does not have a selector or multiplexer function.

Further, since the logic built into the LUT is not always complicated, the function of realizing an arbitrary k input variable logic function is not always necessary.

On the other hand, the multiplexer type FPGA uses a multiplexer when expressing an arbitrary logic, but since it expresses a function by multi-stage connection, it is usually
There is a problem that reconfiguration is not easy because it is programmed by a low resistance element such as an antifuse. Further, in order to form a complicated logic, there are problems that many elements are needed and a large area is required.

As described above, up to now, a circuit configuration which has both a symmetric function function frequently used in an arithmetic operation circuit and the like and a selector function often used in a control unit at the same time and can hold the symmetric function function has been provided so far. , Not yet proposed.

[0018]

Among the conventional logic function reconfigurable devices, a device capable of reconfiguring logic functions at high speed is a LUT type FPGA, and its variable logic unit uses SRAM. It is composed of the original LUT. The k-input variable LUT using SRAM can realize all Boolean functions that can be generated by k-input variables, but has a problem of requiring a large area on an LSI. Therefore, it is desired to realize a variable logic unit which can reconfigure a logic function in a small area and at high speed.

The present invention provides a variable logic unit which has a small area of a variable logic unit on an LSI, has a symmetric function function, a selector function and a memory function, and which can reconfigure the logic function at high speed. The purpose is.

[0020]

According to the present invention, the number of terminals in which the states of k first signal terminals are logically either "1" or "0" is defined as the number of input states. That is, the number of input states of the first input signal terminal and the state of the n (1 ≦ n ≦ k + 1) th input signal terminal in the k + 1 second signal terminals are made to correspond one-to-one, and By matching the output state with the state of the associated second input signal terminal or corresponding to the logical inversion, one of the k + 1 input state numbers of the k first input signal terminals is It is an integrated circuit which, when selected, is either the logical state of the k + 1 second input signals, "1" or "0", or its inversion, which causes the output of the integrated circuit.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) FIG. 1 is a diagram showing the structure and principle of a functional function reconfigurable integrated circuit IC1 according to a first embodiment of the present invention.

The function circuit reconfigurable integrated circuit IC1 is
It has both a symmetric function function of k input variables and a selector function of selecting one of k + 1 data inputs by k control inputs.

FIG. 1A is a diagram showing a functional function reconfigurable integrated circuit IC1 having both a symmetric function function and a selector function.

The function circuit reconfigurable integrated circuit IC1 is
k first input signal terminals input1 [1], inp
ut1 [2], ..., Input1 [k], and k + 1 second input signal terminals input2 [1], input
2 [2], ..., input2 [k], input2
It has [k + 1] and one output signal terminal output.

When the symmetric function function is to be developed, k first input signal terminals input1 [1] to input1 are input.
[K] is used as k input variable terminals, and k + 1 second input signal terminals input2 [1] to input2
[K + 1] is used as a configuration data input terminal for inputting data configuring the symmetric function function.

The symmetric function is a logical function whose function value does not change even if the input variables are arbitrarily replaced. Further, the data forming the symmetric function function is data for determining a symmetric function such as AND and OR.

When the number of terminals whose input variable terminal states are logically "1" is m, it is called "the number of input states is m". At this time, the number of input states is from 0 to Take k + 1 integer values up to k.

In FIG. 1B, the horizontal axis shows the number of input states, and the vertical axis shows the output signal states which are the states of the output signal terminals.

There is a one-to-one correspondence between the output signal state at each number of input states and the state of the k + 1 terminals of the second input signal terminal shown in FIG. 1 (1). That is, the output signal state when the number of input states is “0” corresponds to the state of the input terminal input2 [1], and the output signal state when the number of input states is “1” is the input terminal i.
The number of input states “k” corresponding to the state of nput2 [2]
, The output signal state when
It corresponds to the state of [k + 1].

In this way, by associating the number of input states, which is the number of arbitrary states of the input terminal, with the second input signal terminal, that is, by associating two different states of the configuration data input terminals. This makes it possible to have an arbitrary symmetric function function.

Further, the data constituting the symmetric function function is
After being input once, it becomes possible to hold the configuration data by using the memory circuit or the memory element provided inside the integrated circuit C1.

On the other hand, when the selector function is to be expressed,
The k first input signal terminals shown in FIG. 1A are regarded as k control input terminals, and the k + 1 second input signal terminals are regarded as k + 1 data input terminals.

As described above, since the predetermined number of input states has a one-to-one correspondence with the predetermined state of the second input signal terminal, the predetermined number of input states is selected from among k + 1 different input state numbers. When the number of input states is selected, the state of one signal terminal is selected from the k + 1 second input signal terminals. In this way, it becomes possible to have a selector function.

The function of selecting one of a plurality of data inputs is known as a multiplexer function. The multiplexer function is a selector function having ^k control inputs and 2 ^k data inputs. However, unlike the circuit that selects according to the number of input states in the above embodiment, the selector function of the above embodiment allows a plurality of control inputs to select the same data, and is more flexible in terms of control input. .

As described above, the function-function reconfigurable integrated circuit IC1 according to the above-described embodiment can have both the symmetric function function and the selector function.

(Second Embodiment) FIG. 2 is a circuit diagram showing an integrated circuit IC2 capable of function / function reconfiguration according to a second embodiment of the present invention.

The function / function reconfigurable integrated circuit IC2 according to the second embodiment is a circuit using a threshold element and having both the symmetric function function and the selector function shown in the first embodiment.

The function / function reconfigurable integrated circuit IC2 is
It is a feedforward circuit having a two-stage logic configuration. The first stage is k + 1 threshold elements (Threshold Logic Elemen
t: TLE) having TLE [1] to TLE [k + 1],
The second stage has one threshold element TLE [k + 2].

Each threshold element TLE in the first stage has k first input signal terminals input1 [1] to input1.
K input terminals connected to 1 [k] and k + 1 second input signal terminals input2 [1] to input2
It has a total of k + 1 input terminals including one input terminal connected to one different terminal in [k + 1], and each has one output terminal.

The threshold element TLE [k + 2], which is the second-stage threshold element TLE, has k input terminals connected to the first input signal terminal and k + 1 of the first-stage threshold element TLE.
It has an input terminal connected to each output terminal and one output terminal.

The signal input from the first input signal terminal is called the first input signal, and the signal input from the second input signal terminal is called the second input signal.

Here, the threshold element TLE is defined as follows. That is, the threshold element TLE compares the sum of products of the value (logically 1 or 0) of the input signal and the weight with respect to the threshold for all the input signals, and the value of the sum of products is the threshold. If it is more than the above, it is defined as an element that outputs logical "1", and conversely, if the value of the product sum is smaller than the above threshold value, outputs "0". Then, the weight of the input terminal of the threshold element TLE [i] (1 ≦ i ≦ k + 1) in the first stage is
It is assumed that all are integers w _i and are equal to each other, and the threshold value T _i of the threshold element TLE [i] is represented by the following equation (1).

W _i · (i−1) <T _i <w _i · i (1) By setting as described above, the number m of input states of the first input signal terminal m (0 ≦ m ≦ For k), the sum of products of the values of the input signal and the weights with respect to all the input signals input to the threshold element TLE [i] is w if the state j = 0 of the second input signal terminal. _{If i} · m and the state j = 1 of the second input signal terminal, then w _i · (m + 1).

When the input signal has a predetermined number of input states m, the threshold element TLE [i] (1≤i≤k +) in the first stage
1) can be classified into first, second and third groups.

The first group is a group in which the threshold element TLE [i] having the threshold value T _i satisfies i <m + 1, and the second group is a group in which i = m + 1. The third group is a group that satisfies i> m + 1.

In the first group, i <m +
Since it is 1, T _i <w _i · (m + 1). This first
Is a threshold element TLE [1] to TLE [m].
Up to m threshold elements, the sum of products of all input signals exceeds the threshold value regardless of the value of the second input signal. Because of this, the output signal is always a logical one.

In the third group, i> m +
Since it is 1, T _i <w _i · m. This third group includes threshold elements TLE [m + 2] to TLE [k + 1].
And the second input signal has any value, the sum of products of all the input signals does not exceed the threshold value. Because of this, the output signal is always logically zero.

On the other hand, in the second group, i
= M + 1, the output signal of the threshold element TLE [i] depends on the second input signal value. That is, when the value j of the second input signal is j = 0, the relation between the product sum of the values of all the input signals and the weight and the threshold value is expressed by the following equation (2).

T _i > w _i · m (j = 0) Equation (2) Therefore, the output signal is logically 0.

When the value j of the second input signal is j = 1, the relation between the sum of products of all the input signal values and the weight and the threshold value is expressed by the following equation (3). “+1” in (m + 1) of the second term on the right side of Expression (3) is the effect of the second input signal.

T _i <w _i · (m + 1) (j = 1) (3) For this reason, the output signal is logically one.

As described above, the second group i =
The threshold element TLE [m + 1] of m + 1 has two different states of the second input signal terminal (the value of the second input signal j =
It can be seen that the output state differs depending on 0, 1).

Regarding the operation of the threshold element in the first stage, the above is summarized. When the number of input states is m, the m threshold elements in the first stage output logical 1 and km threshold thresholds. The element outputs a logical 0 and the only threshold element is the second
Depending on the value of the input signal of, a logical 1 or 0 is output.

The input terminals of the second threshold element TLE [k + 2] are composed of k first input signal terminals and k + 1 terminals connected to the first-stage output signal terminals. .

A signal input from the first input signal terminal is multiplied by a positive weight w _{(k + 2),} and a signal from the output signal terminal of the first stage is negative weight -w _{(k + 2). )} , And the sum of products operation is performed in the threshold element TLE [k + 2].

Here, the second threshold element TLE [k +
2], and assume that the number of input states is m. First, the input in the threshold element TLE [k + 2]
Of the direct contribution of the input signal of the
The contribution by the output signals of LE [1] to TLE [k + 1] will be considered separately.

The product sum of the value of the first input signal and the weight is w
_{(k + 2)} · m. For the output signal of the first stage, m threshold elements output logical 1's, km threshold elements output logical 0's, and only one threshold element outputs logical 1's or logical 1's. Since it is known to output 0, the sum of products for these signals is represented by -w _{(k + 2)} · m + Δ.

Where Δ is the threshold element TLE of the first stage
It means the value of the product sum of the value of the output signal of [m + 1] and the weight. From these, the second threshold element TLE [k +
It can be seen that the sum of products of all the input signals to [2] and the weights is Δ.

The sum of products Δ is the value of the output signal of the first threshold element TLE [m + 1] corresponding to i = m + 1 and the weight −w _{(k + 2)} of the _second threshold element TLE [k + 2]. If the value of the second input signal input to the threshold element TLE [m + 1] in the first stage is logical 1, the threshold element T
LE [m + 1] outputs logical 1 and Δ = −w _{(k + 2 )}
If the above signal is logical 0, the threshold element TL
E [m + 1] outputs logical 0, and Δ = 0.

At this time, the second threshold element TLE
The threshold value T _{(k + 2) of} [k + 2] is −w _{(k + 2)} <T _{(k + 2)} <0.
Then, the threshold element TLE [k + 2] outputs differently according to the different state of the signal of the second input signal terminal input to the threshold element TLE [m + 1].

Next, with respect to the threshold element, the definition of the threshold element is changed as follows. The threshold element TLE is
For all the input signals, the product sum of the value of the input signal (logically 1 or 0) and the weight is compared with the threshold value, and if the value of the product sum is equal to or larger than the threshold value, logical "0" is given. And then,
An element that outputs "1" if it is smaller than the threshold value,
It is defined as

That is, the concrete expression for the threshold element TLE [k + 2] is that the weight of the output signal from the threshold element in the first stage in the threshold element TLE [k + 2] is not the negative weight as described above. , The weights have the same absolute value, but the logical inversion (negative) of the output signal is input. An example of this is shown below.

In this case, when the number of input states is m, m of the threshold elements in the first stage output logical 0,
Of the threshold elements in the first stage, km output a logical 1,
The threshold element TLE [m + 1] outputs logical 1 or 0 depending on the signal state of the second input signal terminal. For the second threshold element TLE [k + 2], the sum of products for the first input signal is w _{(k + 2)} · m, and the sum of products for the output signal of the first threshold element is w _{(k + 2)} · m. _{(k + 2)}・ (k−
m) + Δ ′, and the sum of these is w _{(k + 2)} · k + Δ ′
Becomes Δ'is the product sum of the output signals of the threshold element TLE [m + 1] at the first stage, and takes 0 or w _{(k + 2)} .

Therefore, in this case, the threshold element TL
The threshold value T _{(k + 2)} of E [k + 2] is set to w _{( k + 2)} · k <T _{(k + 2)}
By setting <w _{(k + 2)} · (k + 1), the output state of the second-stage threshold element TLE [k + 2] is set to the first-stage threshold element as in the case where the negative weight is provided. TLE
It can be controlled by the second input signal input to [m + 1].

As described above, the state of the second input signal terminal is set to the number of input states of the signal of the first input signal terminal by one to one.
By making them correspond to each other, it becomes possible to generate an arbitrary k input variable symmetric function.

On the other hand, when the number of input states of the signal at the first input signal terminal is regarded as the control input value, it is possible to selectively output the signal state of a certain second input signal terminal. This indicates that the circuit selects k + 1 data inputs by k control inputs.

FIG. 3 is a diagram showing a functional function reconfigurable integrated circuit IC2a having three first input signal terminals and four second input signal terminals and constituted by a threshold element. .

In the first stage, four threshold elements TLE [1],
TLE [2], TLE [3], and TLE [4], and each threshold element has three first input signal terminals inp.
ut1 [1], input1 [2], input1
It has an input from [3], and further has second input signal terminals input2 [1], input2 [2], input.
It has inputs from 2 [3] and input2 [4]. Second
The second input signal input from the input terminal of is a unique input signal for each threshold element. That is, the threshold elements TLE [1], TLE [2], TLE
[3] and TLE [4] are respectively connected to the terminal input2.
[1], input2 [2], input2 [3], i
The second input signal from nput2 [4] is input.
In addition, the weight of the input in each threshold element is equal to "2".
Is set to.

Further, the threshold elements TLE [1] to TLE
The threshold values (T ₁ , T ₂ , T ₃ , T ₄ ) of [4] are (T ₁ , T ₂ ,
T _3, T ₄₎ = is set to (1,3,5,7). Two
The threshold element TLE [5] of the stage has an input from the first input signal terminal and a negative input of the signal from the output signal terminal of the first stage. From another perspective, it can be considered that the threshold element in the first stage is a threshold element that outputs logical inversion as an output signal. However, here, an example is shown in which the output state of the threshold element in the first stage is negated or logically inverted before being transmitted to the threshold element in the second stage.
The input weights are all "2" and the threshold value is "7".

FIG. 4 shows an integrated circuit I whose function and function can be reconfigured.
It is a figure explaining operation | movement of C2a.

In FIG. 4, the horizontal axis shows the number of input states of the first input signal terminal, and the vertical axis shows the state of the output signal of each threshold element.

Each threshold element in the first stage has an input from the second input signal terminal as an input other than that represented by the number of input states in FIG. For example, TLE [1] has an input from the terminal input2 [1]. TLE [1]
, The number of input states is m = 0, the terminal inpu
If the state of t2 [1] is "1", the threshold is exceeded and the output signal state is "1". If the state of input2 [1] is "0", the output signal state is "0". Is.

When m> 0, the output signal state becomes "1" regardless of the state of input2 [1].
In the figure, even if the second input signal terminal is in any state,
When the output signal state is fixed, it is shown by a black circle, and when the output signal state depends on the state of the second input signal terminal, it is shown by a white circle.

First-stage threshold elements TLE [2], TLE
Threshold element TLE for [3] and TLE [4]
Similar to [1], the meaning of the circles in FIG. 4 can be explained from the relationship between the number of input states and the threshold value.

Next, TLE which is the second threshold element
The operation [5] will be specifically described by using the case where the number of input states is two.

Since the number of input states is 2, the threshold element T
It can be seen that in the first input signal to LE [5], two signals are logical ones and the other one is a logical zero.
Regarding the output states of the threshold elements TLE [1] to TLE [4] in the first stage, referring to FIG. 4, TLE [1], TLE [2]
The output state of TLE [4] is also a logical 0, independent of the second input signal, and the output state of TLE [4] is also a logical 0. The output state of the threshold element TLE [3] depends on the value of the second input signal, and when the value of the second input signal is logical 1, the output state becomes logical 1, and conversely, When the value of the input signal is logical 0, the output state is 0.

The output states of these first-stage threshold elements are
Before being input to the threshold element TLE [5] of the second stage, it is negated, that is, logically inverted and weighted, and input to the threshold element TLE [5]. Therefore, when the number of input states is 2, it is not dependent on the value of the second input signal, and logical 1 is 2 from the first input signal and 1 from the negation of the output state of the threshold element in the first stage. , A total of three are entered.

When the value of the second input signal of the threshold element TLE [3] at the first stage is logical 1 or 0, the number of logical 1s input to the threshold element TLE [5] is , 3 or 4, respectively. Threshold element TLE
The sum of products of the values and weights of all the input signals input to [5] is “6” or “according to the value of the second input signal input to the threshold element TLE [3] in the first stage. 8 ”. This value is compared with the threshold value “7” of the threshold element TLE [5] to determine the output value. The meaning of the white circle in the input state number 2 of TLE [5] in FIG. 4 can be explained as above.

For all numbers of input states other than 2,
The output state of the threshold element TLE [5] can be explained as above.

Therefore, in each input state number, as shown in FIG.
The output state of the first-stage threshold element indicated by the white circle inside is
It can be seen that the threshold element TLE [5] is in the output state.

This means that an arbitrary symmetric function can be realized according to the state of the second input signal terminal.

FIG. 5 is a diagram showing an example of an AND circuit which is one of symmetric functions.

FIG. 5 (1) shows the relationship between the number of input states and the output signal state of each threshold element, and FIG. 5 (2) shows a truth table.

In order to have the AND function, the second input
Force signal terminals input2 [1], input2 [2],
The state of input2 [3] and input2 [4]
These are “0”, “0”, “0”, and “1”. At this time,
Set the state of the first input signal terminal to X ₁, X₂, X₃And T
Assuming that the output signal state of LE [5] is Y,
It becomes a truth table.

As described above, the AND function can be realized by the integrated circuit IC2a whose function and function can be reconfigured. Similarly, other symmetrical function functions are possible.

On the other hand, as shown in FIG. 4, the output states of the threshold element TLE [5] at the number of input states m = 0, 1, 2, 3 respectively indicate the second input terminal input2.
[1], input2 [2], input2 [3], i
In the state of nput2 [4], when the number of input states is regarded as a control input and the state of the second input signal terminal is regarded as a data input, it is possible to realize a 4-data input selector circuit with 3 control inputs. I understand.

As has been specifically described above, the integrated circuit of the above embodiment can have both the symmetric function function and the selector function.

In the above embodiment, the two different states are associated as described above, but "1" and "0" are set.
It is possible to easily infer the circuit configuration in the case where is completely inverted. Also, regarding the weights for the input signals input to the threshold elements, there is an example in which the weights are assumed to be equal in the above, but when the threshold elements are implemented as an actual integrated circuit, the weights are implemented as some physical quantity. Therefore, it is difficult to make them equal in a strict sense, and at the same time, there is no need for them to be the same, and values that can be considered equal in terms of the operating principle are sufficient.

By the way, in the above-mentioned embodiment using the threshold element, k first input signals are input to each threshold element one by one. However, since the weights of the first input signals are equal in each threshold element, it is not always necessary to input k first input signals to each threshold element one by one. In other words, the sum of the values of the first input signal may be calculated in advance, the sum may be input to each threshold element, and a certain weight may be applied in each threshold element. It is possible to obtain the same effect as when the k first input signals are input to the threshold element one by one.

(Third Embodiment) FIG. 6 shows an integrated circuit IC3 having both a k-input variable symmetric function function and a selector function for selecting one from k + 1 data inputs by k control inputs. Neuron MO, which is one of the threshold elements
It is a figure which shows the circuit structural example in the case of implement | achieving using an S transistor ((nu) MOS).

In this case, k = 3.

Next, the circuit configuration and operation of the integrated circuit IC3 will be described with reference to FIG.

The main component is a neuron MOS inverter which is an inverter circuit composed of νMOS,
Four pre-inverters 60 forming the first stage of the two-stage logic
It has 1,602,603,604 and the main inverter 600 used as the second stage.

As a control circuit and peripheral circuits, a data holding control circuit 606, a mode switching circuit 605, a waveform shaping circuit 609, and a delay generation circuit 614 are provided.

First, the circuit configuration and operation of the four pre-inverters will be described.

FIG. 7 is a circuit diagram specifically showing the pre-inverter 601.

The print verters 602, 603, 60
The specific example and the operation of No. 4 are the same as the specific example of the print verter 601 shown in FIG.

Pre-inverter 601 has five input gates. Input terminals of the pre-inverter 601 are terminals terminal [11] and terminal [1].
2] and terminal [13] are terminals input1 [1] and input, which are the first input signal terminals in FIG.
1 [2] and input1 [3], and the capacitance value between the floating gate and each of them is C ₁₁ ,
It is a C _12, C _13.

The terminal input2 [xa] shown in FIG. 7 is
The terminal input2 which is the second input signal terminal in FIG.
[1], input2 [2], input2 [3], i
The terminals input2 [1a], inp connected to nput2 [4] via the transmission gate.
ut2 [2a], input2 [3a], input2
It is a terminal that is connected to any one of [4a] and receives the second input signal, and the capacitance value between the floating gate and the second input signal is C _2x .

Terminal terminal [0] shown in FIG.
Represents a terminal connected to the power supply potential or the ground potential shown in FIG. 6, and the capacitance value between the floating gate and the floating gate is C ₀ .

The terminal ctl3 shown in FIG. 7 is the terminal ctl3 in FIG. 6, and is a terminal for inputting a signal for controlling conduction and interruption of the floating gate initialization NMOSFET of the pre-inverter.

As an example, when the potential of the floating gate shown in FIG. 7 exceeds half of the power source potential V _dd (V _dd / 2), the potential of the output terminal of the inverter is inverted so that the neuron MOS inverter is inverted. Design, C ₁₁ , C
The ratios of ₁₂ , C ₁₃ , C _2x , and C ₀ are all set to 1/5, and the terminal te
Consider a circuit in which rminal [0] is connected to the power supply potential.

The potential of the terminal ctl3 shown in FIG. 7 is set to V _dd , the floating gate initialization NMOSFET of the pre-inverter 601 is made conductive, the floating gate is set to the ground potential, and the pre-inverter 60 is set between them.
All the input signals of 1 and the potential of a terminal (for example, terminal terminal [0]) fixed to a predetermined potential are set to the ground potential.

In this state, the potential of the terminal ctl3 is set to the ground potential, and the NMOSFET is cut off. Such an operation of bringing the floating gate to a certain potential and then bringing it into a floating state is called initialization of the floating gate. The terminal to be fixed to the predetermined potential is fixed to the predetermined potential after it is completely floating.

After the above operation, the state of the output terminal of the pre-inverter 601 can be divided into the following three cases depending on the state of the first input signal.

Here, when the potential of the output terminal is higher than V _dd / 2, it is logically "1", and when it is V _dd / 2 or less, it is logically "0".

In the first of the above three cases (the first of the states of the output terminals of the pre-inverter 601), all the first input signals are at ground potential ( , Hereafter referred to as “when the number of input states is 0”), and the potential of the terminal input2 [xa] is V _dd ,
Regardless of the ground potential, the pre-inverter 60
The state of the output terminal of 1 is logically "1".

In the second of the above three cases (the second of the states of the output terminals of the pre-inverter 601), one of the first input signals is the power supply potential V _dd.
(Hereinafter, referred to as “the case where the number of input states is 1”), the potential of the floating gate is
It depends on the potential of the terminal input2 [xa]. Since the terminal terminal [0] is already connected to the power supply, when the potential of the terminal input2 [xa] is the ground potential, the potential of the floating gate is (2 /
5). Since it can be approximated by V _dd and the potential of the floating gate is smaller than V _dd / 2, the state of the output terminal of the pre-inverter is logically an inversion of the logical state of the floating gate. It becomes "1". On the other hand, terminal i
When the potential of nput2 [xa] is the power source potential V _dd , the potential of the floating gate is (3/5) · V _dd.
Since the potential of the floating gate is larger than V _dd / 2, the state of the output terminal of the pre-inverter 601 is logically “0”. Thus, in the second case, the logical negation value of the terminal input2 [xa] is output from the pre-inverter 601.

In the third of the above three cases (the third of the states of the output terminals of the pre-inverter 601), any two or more of the first input signals are the power supply potential V _dd. (Hereinafter, referred to as “the case where the number of input states is 2 or more”), and the terminal input2 [x
The potential of the floating gate is
It is larger than V _dd / 2, and the state of the output terminal of the pre-inverter is logically “0”.

The three cases in which the state of the output terminal of the pre-inverter 601 can be taken have been described above.

The capacitance ratio of the capacitance between the input terminal of the neuron MOS inverter, that is, the first input signal terminal, the second input signal terminal, the terminal fixed to a predetermined potential, and the floating gate is adjusted. By doing so, it is possible to set the above-mentioned second case in any number of input states.

Next, by controlling the floating gate potential of the pre-inverter by the terminal ctl3, the terminal in
The point that the potential corresponding to the logical inversion of the potential of put2 [xa] can be held will be described.

The potential of the terminal ctl3 is set to the power source potential V _dd ,
The floating gate potential of the pre-inverter 601 is
While fixed to the ground potential, the terminal input2
The potential of [xa] is set to V _dd , and the terminal terminal
All other input terminals including [0] are set to ground potential,
With this input state maintained, the potential of the terminal ctl3 is set to the ground potential, the floating gate is set to the floating state, and then the potential of the terminal that is fixed to a predetermined potential is fixed, and the potential of the terminal input2 [xa] is set to V _dd. Fixed to.

In this state, the amount of charge accumulated in the floating gate is equal to
When only the potential of put2 [xa] is V _dd, it is the amount of charge accumulated in the floating gate. Therefore, even if the potential of the terminal input2 [xa] is V _dd , the floating gate potential is There is no effect to increase.

That is, when the floating gate is connected to the ground potential, the terminal input2 [x
The same state as when the potential of a] is set to the ground potential is maintained. Conversely, the terminal input2 [x
When the floating gate is initialized by setting the potential of [a] to the ground potential, the terminal inp is set in the floating state.
Fixing ut2 [xa] to V _dd increases the potential of the floating gate. That is, terminal in
The state of V _dd is held as the potential of put2 [xa].

As described above, if it is desired to hold V _dd as a value which is logically opposite to the value to be held as the potential of the terminal input2 [xa], for example, V _dd is held as the potential of the terminal input2 [xa]. Terminal input2 [x
The floating gate is initialized by setting the potential of a] to the ground potential. Conversely, if it is desired to maintain the ground potential, the potential of the terminal input2 [xa] is set to V _dd
To initialize and then the terminal input21 [xa]
A method of fixing the potential of 2 to V _dd may be adopted.

It has been described above that the potential of the terminal input2 [xa] can be held by operating the floating gate potential and the input signal.

As described above, in the pre-inverter, when the number of input states is predetermined, the logical inversion of the input signal at the terminal input2 [xa], which is the second input signal terminal, is used as the output signal of the pre-inverter. Further, after the floating gate is initialized, by fixing the potential of the terminal input2 [xa] to the power supply potential V _dd , the logical inversion of the signal at the terminal input2 [xa] is performed at the time of the floating gate initialization. It is possible to hold

Next, the basic symmetric function function operation and selector function operation of the function circuit reconfigurable integrated circuit IC3 shown in FIG. 6 will be described with reference to FIG.

FIG. 8 is a circuit diagram showing the main constituent circuit of the integrated circuit IC3 with reconfigurable function and function shown in FIG.

In FIG. 8, four pre-inverters 80
A two-stage logic in which 1, 802, 803, and 804 are the first stage and the main inverter 800 is the second stage is configured, and an output buffer 805 is connected to the output terminal of the main inverter 800.

In the circuit shown in FIG. 8, the pre-inverter 80
1 to 804 and the floating gate of the main inverter 800 are both initialized with the potentials of all input terminals set to the ground potential.

Further, as described for the pre-inverter 601, shown in FIG. 7, the four pre-inverters 801, 80 are provided.
2, 803 and 804 are input state numbers 0, 1 and
Corresponding to terminals 2 and 3, terminals input2 [1], input
t2 [2], input2 [3], input2 [4]
It is designed to output the logical inversion of.

The threshold potential of the main inverter 800 shown in FIG. 8 is designed to be V _dd / 2, and
Of the three first input signal terminals, the input terminals connected to the output terminals of the four pre-inverters 801 to 804, and the floating gate of the main inverter 800 are all equal in ratio 1 It is designed for / 7.

When the number of input states is 0, the state of the output terminal of the pre-inverter 801 is the terminal input2 [1].
Of the other pre-inverter 8
The states of the output terminals of 02 to 804 are logically “1” without depending on the potential of the second input terminal.

Therefore, 7 of the main inverter 800 is
Of the three input terminals, three first input terminals are logically “0”, three output terminals of the pre-inverter are logically “1”, and one terminal is the terminal input2.
Since it is a logical inversion of [1], the potential of the floating gate is (3/7) · V _dd + when the logical inversion potential of the terminal _{input2 [1]} is expressed as V ′ _{input2 [1].}
(1/7) · V ′ _{input2 [1]} . Therefore, if the potential of the terminal input2 [1] is V _dd , the potential of the floating gate becomes (3/7) · V _dd , which is smaller than the threshold potential, so that the output of the main inverter 800 is logically When it becomes “1” and the potential of the terminal input2 [1] is 0, the potential of the floating gate becomes
(4/7) · V _dd, which is higher than the threshold potential, so the output of the main inverter 800 is logically “0”.

That is, when the number of input states is 0,
The logical value of the terminal input2 [1] is output from the main inverter 800.

When the number of input states is 1, the logical value of the terminal input2 [2] becomes
It is output from the main inverter 800. When the number of input states is 2, the logical value of the terminal input2 [3] is output from the main inverter 800. When the number of input states is 3, the logical value of the terminal input2 [4] is output from the main inverter 800.

This means that the relationship between the number of input states and the output signal state of FIG. 4 shown in the second embodiment is the same.

The circuit shown in FIG. 8 has the terminal input1.
[1], input1 [2], and input1 [3]
Are used as three control input terminals, and the terminal input2 [1]
~ Input2 [4] has a selector function for inputting four data, and terminals input2 [1] to input2
By fixing ut2 [4] to some logical value,
It also has a 3-input symmetric function function.

The circuit shown in FIG. 6 is different from the circuit shown in FIG. 8 in that a circuit for initializing a floating gate, a data holding control circuit 606 for holding a function function, and a second input which is an input of a pre-inverter. A mode switching circuit 605 that switches between continuously passing a signal from a signal terminal through a pre-inverter and holding the value thereof, and a waveform shaping circuit 609 that matches an electrical signal with a logical state.
And a delay generation circuit 614 are added.

First, the terminals input2 [1] to input2 which are the second input signal terminals of the pre-inverter.
A case where the logical value of [4] is held in the pre-inverter will be described with reference to FIG.

This circuit has three first input signals and four
Two second input signals and three control signals are input,
Output two output signals. The first input signal is the terminal in
The first input signal terminals of put1 [1] to input1 [3] are input, and the second input signal is input terminal2.
It is input from the second input signal terminals of [1] to input2 [4].

The terminal ctl3 is connected to the main inverter 600.
Is a signal input terminal for controlling conduction and interruption of the floating gate initialization NMOSFET 611 connected to the floating gate of the NMOSFET 611. When the potential of the terminal ctl3 is the power supply potential V _dd , the NMOSFET 611 conducts,
The floating gate of the main inverter 600 is connected to the ground, and when the above potential is the ground potential, the NMOSFET 611 is cut off and the floating gate enters the floating state.

In the floating gates of the pre-inverters 601-604, the signal input from the terminal ctl3 is
By being processed by the delay generation circuit 615, the floating gate initialization N of the main inverter 600 is initialized.
The signal for controlling the MOSFET 611 is controlled by a signal added with a certain delay time.

The terminal ctl2 includes terminals input2 [1] to input2 [4] which are second input signal terminals and terminals input2 [1a] to input2 [4a] which are input signal terminals of the pre-inverters 601 to 604. It controls connection and disconnection, and at the same time controls the terminal input2 [1
a] to input2 [4a] are input terminals for signals for controlling disconnection and connection to the power supply.

When the potential of the terminal ctl2 is the power source potential V _dd , the terminals input2 [1] to input2 [4].
Are terminals input2 [1a] to input2, respectively.
Connected to [4a] and connected to terminals input2 [1a] to in2
put2 [4a] is disconnected from the power supply. Conversely, terminal c
When the potential of tl2 is the ground potential, the terminal inp
ut2 [1] to input2 [4] and the terminal input
2 [1a] to input2 [4a] are cut off, and the terminals input2 [1a] to input2 [4a] are connected to the power supply.

The terminal ctl1 is an input terminal for a signal that switches between two modes, a mode in which the second input signal is held in the pre-inverters 601 to 604 and a mode in which the second input signal passes as it is. When the potential of ctl1 is the power supply potential V _dd , the mode switching circuit 60
Data is held and output of the held data is performed by 5, and the second input signal continuously passes through the pre-inverters 601 to 604 at the ground potential.

In the above circuit, the potential of the terminal ctl1 is fixed to the power supply potential V _dd , and then the potential of the terminal ctl2 is set to the power supply potential V _dd to input the second input signal to the pre-inverters 601 to 604. can do. At this time, the mode switching circuit 605 causes the signal propagation control circuit 60 in the subsequent stage of the pre-inverters 601 to 604.
8 is cut off, and the output terminals of the pre-inverters 601 to 604 are disconnected from the input side of the main inverter 600. Here, the potential of the terminal ctl3 is set to the power source potential V _dd ,
The floating gate initialization NMOSFET 611 of the main inverter 600 is made conductive to set the floating gate potential to the ground potential. At this time, all the first input signals are at the ground potential. Further, the output signal of the delay generation circuit 615 causes the main inverter input gate initialization NMOSFET 610 to conduct, and the four input signals other than the first input signal in the main inverter 600 are also fixed to the ground potential.

The potential changeover switch 613 sets the potential of one of the input terminals of the pre-inverters 601 and 602 to the ground potential. By setting the second input signal to the ground potential, the pre-inverter 6
The inputs 01 to 604 are all at the ground potential.

In this input state, as the second input signal, as described with reference to FIG. 7, the logically inverted signal of the signal for generating the necessary function function is input.

After that, the potential of the terminal ctl3 is switched to the ground potential, and the floating gates of the main inverter 600 and the pre-inverters 601 to 604 are cut off from the ground to bring them into a floating state. After the floating gate becomes floating, the terminal ct
The potential of 12 is switched to the ground potential. As a result, the terminal input2 which is the input terminal of the pre-inverter
[1a] to input2 [4a] are terminals input2
[1] to input2 [4] are cut off and connected to the power supply.

Further, one of the input terminals of the pre-inverters 601 and 602 is connected to the power supply by the potential changeover switch 613, and the pre-inverters 601 to 604 are connected to the input terminal of the main inverter by the mode changeover circuit 605. It

By the series of these operations, it becomes possible to realize a predetermined symmetric function function.

FIG. 9 is a diagram showing the operation procedure.

The initialization time in FIG. 9 is the time for holding the data constituting the function function, and the time at which the potential is switched is indicated by the numbers 1, 2, 3, and 4 according to the procedure. Also, the terminal input1 is the terminal input1
[1] to input1 [4] is a general term for terminals, and the terminal i
nput2 is input2 [1] to input2
It is a general term for [4].

The output buffer 607 outputs a logical value held in the pre-inverters 601 to 604 corresponding to the number of input states of the first input signal, whereby a predetermined function function is realized. From a different point of view, this can be regarded as a memory function that outputs the logical value held in the pre-inverters 601 to 604 using the number of input states of the first input signal as an address. It can be regarded as a selector function for outputting the logical value held in the inverters 601 to 604.

Next, the terminals input2 [1] to inpu which are the second input terminals of the pre-inverters 601 to 604.
The logical value of t2 [4] is the preinherters 601 to 60.
The case of passing 4 continuously will be described with reference to FIG.

The potential of the terminal ctl3 is set to the power source potential V _dd ,
The floating gate of the main inverter 600 and the floating gates of the pre-inverters 601 to 604 are connected to the ground, and the main inverter input gate initialization NMOSFET 610 is made conductive. At the same time,
The potentials of the terminals ctl2 and ctl1 are set to the power supply potential V _dd , and the terminals input2 [1] to input2 [4] are
The pre-inverters 601 to 60 are connected to the terminals input2 [1a] to input2 [4a] by the signal propagation control circuit 608 at the subsequent stage of the pre-inverters 601 to 604.
The output terminal of No. 4 and the terminal which becomes the input of the main inverter 600 are disconnected.

At this time, by setting all the first input signals to the ground potential, all the input signals related to the main inverter 600 are set to the ground potential. Also,
By the potential changeover switch 613, one of the input terminals of each of the pre-inverters 601 and 602 is connected to the ground. Second input signal terminal i
By setting nput2 [1] to input2 [4] to the ground potential, all the input signals related to the pre-inverters 601 to 604 become the ground potential.

When this state is maintained, the terminal ct
The electric potential of 13 is set to the ground electric potential, and the main inverter 60
0 floating gate initialization NMOSFET 611
And the floating gate initialization NMOSFET 612 of the pre-inverters 601 to 604 are cut off, and the floating gate of the main inverter 600 and the floating gates of the pre-inverters 601 to 604 are switched to a floating state.

Then, the potential of the terminal ctl1 is set to the ground potential, and the signal propagation control circuit 608 passes the pre-inverters 601 to 604 via the mode switching circuit 605.
And the terminal connected to the input terminal of the main inverter 600 are connected.

By the series of these operations, the three first
It is possible to realize a selector function which outputs the one of the four second input signals corresponding to the number of input states by using the input signal of 4 as a control input and the four second input signals as data inputs.

FIG. 10 is a diagram showing the above-mentioned series of operation procedures.

The initialization time in FIG. 10 is the initialization time of the floating gates of the main inverter 600 and the pre-inverters 601-604, and the pre-inverter 601.
~ 604 is the time for connecting the output terminal of the main inverter 600 to the output terminal, and the time at which the potential is switched is indicated by the numbers 1, 2, and 3 according to the procedure.

Further, the terminal input1 is the terminal input
The terminals t1 [1] to input1 [4] are generic terms, and the terminal input2 is the terminals input2 [1] to input.
It is a generic term for t2 [4]. The "control input signal potential" in the item of the terminal potential during the implementation of the selector function means a combination of the potentials of the signals at the three first input signal terminals that are selection signals, and the "data input signal potential" is selected. Means a combination of the potentials of the signals of the second input signal terminal which are the data signals.

Next, the delay generation circuit 614 will be described.

Since the main inverter 600 is a multi-input circuit (7-input circuit in the above-mentioned embodiment), the delay of each input is not uniform when the signal of a certain input terminal is before the state transition. A time (delay time difference) that the signal at the input terminal is after the state transition may occur. The output signal during this time is a false signal and should be removed.

Terminal input which is the first input signal terminal
1 [1] to input1 [3] and the main inverter 6
The delay generation circuit 614 provided between the input terminal 00 and the input terminal 00 is inserted for the purpose of suppressing the delay time difference between the input signals described above.

Next, the waveform shaping circuit 609 will be described.

The potentials of the floating gates of the main inverter 600 and the pre-inverters 601 to 604 depend on the charge amount which is the product of the value of the capacitance between the input terminal and the floating gate and the input signal potential. There are multiple inputs, and the plurality of input signal potentials are not necessarily all power supply potentials or ground potentials. For this,
The potential of the floating gate often becomes an intermediate potential between the power supply potential and the ground potential, and the main inverter 6
00 and the potentials of the output terminals of the pre-inverters 601 to 604 have a high intermediate potential.

Since it is desirable that the input signal potential of the main inverter 600 is the power supply potential or the ground potential, the waveform shaping circuit 609 is inserted after the output terminals of the pre-inverters 601 to 604, and the intermediate potential is set to the power supply potential or the ground potential. A function to convert to ground potential is added.

The output buffer 607 is connected to the subsequent stage of the output terminal of the main inverter 600 to provide the same function as described above.

FIG. 11 is a diagram showing a result of a circuit simulation performed for confirming the operation of the circuit shown in FIG. 6, and is a diagram showing that a 3-input symmetric function function is realized.

In FIG. 11, the vertical axis represents the terminals ctl1 to ctl1.
potential of ctl3, terminal inp which is the second input signal terminal
potentials of ut2 [1] to input2 [4], terminals input1 [1] to input1 which are first input signal terminals
The potential of [3] and the potential of the terminal output are represented, and the horizontal axis represents time in μsec.

On the horizontal axis in the upper part of FIG. 11, the logical names realized during a certain time segment are described. Initialization of the floating gate and holding of the logical function to be realized are performed at the time of the first vertical dotted line for realizing each logical function.

During 0 to 1 μsec, an identity that logically outputs “1” is realized for any combination of the first input signals, and during 1 to 2 μsec, NA is realized.
ND is realized, XNOR is realized for 2 to 3 μsec, NOR is realized for 3 to 4 μsec, and 4 to 5 μm
OR is realized during sec and between 5 and 6 μsec.
XOR is realized, AND is realized for 6 to 7 μsec, and NULL that logically outputs “0” for any combination of the first input signals is realized for 7 to 8 μsec. I know that

FIG. 12 is a diagram showing a result of a circuit simulation performed for confirming the operation of the circuit shown in FIG. 6, which has three first input signals as control inputs and four input signals depending on the number of input states. It is a figure which shows having implement | achieved the selector function which selects one from two input signals.

In FIG. 12, the vertical axis represents the terminal ctl.
1 to ctl3 potential, the terminal i which is the second input signal terminal
potentials of nput2 [1] to input2 [4], terminals input1 [1] to inpu which are first input signal terminals
The potential of t1 [3] and the potential of the terminal output are shown, and the horizontal axis thereof shows time in μsec unit.

Further, the upper horizontal axis of FIG. 12 shows the terminal name of the signal selected during a certain time segment.

The floating gate is initialized at the time of the first vertical dotted line for realizing the selector function for selecting each signal. Inp between 0 to 1 μsec
Select the potential of ut2 [1], 1-2 μsec, 2-3
During μsec and 3 to 4 μsec, the potential of one different first input signal terminal is set to the power supply potential to set the number of input states to 1 and select input2 [2] to select 4 to 5 μsec, 5 to 5 μsec. 6 μsec, 6 to 7 μsec
In between, the number of input states is set to 2 by setting the potentials of the two first input signal terminals of different combinations to the power supply potential, and input2 [3] is selected to set 7 to 8 μse.
During the period c, the number of input states is set to 3 by setting the potentials of all the first input signal terminals to the power source potential.
2 [4] is selected. From this, it is understood that the integrated circuit IC3 shown in FIG. 6 realizes the selector function.

As described above in detail, in the integrated circuit IC3 shown in FIG. 6, it is possible to reconstruct a symmetric function which is a logical function that can be realized even after the integrated circuit is manufactured, and at the same time, It also has a selector function. Further, when realizing the symmetric function function, it can be regarded as a memory circuit that realizes writing and reading of the memory by changing the viewpoint.

(Fourth Embodiment) FIG. 13 has a three-input variable symmetric function function and a selector function for selecting one from four data inputs by three control inputs, and each function is configured. Function that realizes a circuit capable of holding data to be stored, that is, what kind of symmetric function is held if it is a symmetric function function, and holding a value that specifies the signal line to be selected if it is a selector function It is a figure which shows reconfigurable integrated circuit IC4.

Next, an integrated circuit IC whose function and function can be reconfigured
The circuit configuration of No. 4 and its operation will be described.

FIG. 14 shows a neuron MOS with a switch.
It is a figure which shows the inverter MI.

FIG. 15 is a diagram showing the pre-inverter 1301.

The configuration and operation of pre-inverters 1302-1304 are the same as those of pre-inverter 1301.

FIG. 16 is a diagram showing the main inverter 1300.

The functional circuit reconfigurable integrated circuit IC4 shown in FIG. 13 is a two-stage logic feedforward type, and has a neuron MOS inverter M with a switch shown in FIG.
I is used in each stage, the circuit shown in FIG. 15 is used as the pre-inverter 1301, and the main inverter 13
The circuit shown in FIG. 16 is used as 00.

The main constituent elements of the functional circuit reconfigurable integrated circuit IC4 are the four pre-inverters 1301, 1302, 1303, 1304 constituting the first stage of the two-stage logic.
The main inverter 1300 is the second stage, and as the main control circuit and peripheral circuits, the function / function configuration data holding control circuit 1305 and the selection data holding control circuit 1306 are included.
A mode switching circuit 1307 and a waveform shaping circuit 1309
And delay generation circuits 1314, 1315 and the like.

The operating principles and configurations of the pre-inverters 1301 to 1304 and the main inverter 1300 are the same as those of the integrated circuit IC3. In the integrated circuit IC3, the first input signal is
Pre-inverters 601-604 and main inverter 60
0 is directly input to the integrated circuit IC4, but is different from the integrated circuit IC3 in that the integrated circuit IC4 is connected via the selection data holding control circuit 1306.

For this reason, the circuit diagram of the pre-inverter 1301 shown in FIG. 15 is the same circuit as the circuit shown in FIG. 7, but the input signal terminal name is changed. I have changed.

Terminals input1 [1a] to input [3a] in the pre-inverter 1301 shown in FIG.
Are the first input signal terminals input1 [1] to input
t1 [3] are connected to the respective t1 [3] via the selection data holding control circuit, and the signal values are connected to the terminals input [1] 1 to
It becomes the signal value of input1 [3] or the value of the power supply potential.

The terminal input2 [xa] in the pre-inverter 1301 shown in FIG. 15 is the terminal input2.
It is a general term for [1a] to input2 [4a]. Figure 15
Of the pre-inverter 1301 shown in FIG.
nal is a terminal for inputting a signal that controls the threshold value as seen from the input signal of the pre-inverter, and is connected to the power supply potential or the ground potential.

Next, four modes of the integrated circuit IC4, which are different from the integrated circuit IC3 (third embodiment), and the control method thereof will be described.

The four modes possessed by the integrated circuit IC4 are the first of which the data constituting the symmetric function function out of the symmetric function functions must be continuously input without being held.
Mode, a second mode in which the data is held, a third mode in which the address of the signal to be selected in the selector function is continuously input, and a fourth mode in which the address of the signal to be selected is held. Is the mode.

FIG. 17 is a diagram showing a procedure for realizing the first mode in the integrated circuit IC4.

In FIG. 17, the initialization time indicates the time of the preprocessing when executing the function processing, and 1, 2, 3 indicate the time series of the procedure. Also, the terminal input1 is
The terminals input1 [1] to input1 [3] are generic terms, and the terminal input2 is the terminal input2 [1] to input2.
It is a generic term for input2 [4].

At the beginning of the preprocessing, the terminal ctl
1 to ctl4 are set to the power supply potential V _dd , and the terminals input
1 and input2 are set to the ground potential 0.

In the division 1 in this initialization time, the function function configuration data holding control circuit 1305 causes the terminal i
ninput2 [1] to input2 [4] are connected to terminals input2 [1a] to input2 [4a], respectively, and the selection data holding control circuit 1306 causes the terminals input1 [1] to input1 [3] to be input to input1 [3], respectively. 1a] to input1 [3a], and the signal propagation control circuit 1308 cuts off the output terminals of the pre-inverters 1301 to 1304 and the input terminal of the main inverter 1300. Also, the pre-inverters 1301 to 1304 and the main inverter 1
The floating gates of 300 are both connected to the ground, and the terminals input1 [1] to input1 [3] are connected.
And the signal potentials of the terminals input2 [1] to input2 [4] are all at the ground potential 0, and the input gate initialization NMOSFET 131 of the main inverter 1300.
Since 0 is conductive, the pre-inverters 1301-1
The input signals of both 304 and the main inverter 1300 are all at the ground potential.

In the division 2 in the initialization time, the terminal ctl4 is set to the ground potential, so that the floating gate initialization NM of the main inverter 1300 is obtained.
OSFET 1311, and pre-inverters 1301-13
04 floating gate initialization NMOSFET 1
The NMOSFET typified by 312 is turned off. By this operation, the pre-inverters 1301 to 13
04 and the main inverter 1300 are initialized in a state where all input signals are at the ground potential.

In the time segment 3, when the terminal ctl1 is set to the ground potential 0, the signal propagation control circuit 1308 connects the output terminals of the pre-inverters 1301 to 1304 and the input terminal of the main inverter 1300. In addition, the PMOSFET in the potential changeover switch 1313
Becomes conductive, and the pre-inverters 1301, 1302
The terminal terminal of is at the power supply potential.

In this state, the terminals input2 [1] to i
nput2 [4] is set to the potential combination V _conf of the configuration data representing a predetermined function and the terminal input1
The symmetric function function can be realized by inputting the signal V _sig to be processed by the symmetric function to [1] to input1 [3].

The solid right arrow in FIG. 17 indicates V _dd.
The potential continues, and the dotted right-pointing arrow indicates that the 0 potential continues.

The above description is the procedure for realizing the first mode.

Next, a procedure for realizing the second mode (a mode capable of holding data forming a symmetric function function) will be described.

FIG. 18 is a diagram showing a procedure for realizing the second mode. The view of FIG. 18 is the same as that of FIG.

In time division 1, terminals ctl1 to ct1
The potential of 14 is V _dd , the terminal input1 is the ground potential 0, and the input 2 is the potential of the logical inversion of the function function configuration data. Comparing the second mode with the first mode, the difference is that the terminal input2
It is only the potential of.

In time segment 2, the floating gate initialization NMOSFE of the main inverter 1300 is set by setting the potential of the terminal ctl4 to the ground potential.
The NMOSFET typified by T1311, and the floating gate initialization NMOSFET 1312 of the pre-inverters 1301 to 1304 are turned off.

By this operation, the main inverter 13
00 is initialized in the state where all the input signals are at the ground potential, and the pre-inverters 1301-1304 have terminals in
Input signals except put2 are at ground potential,
The terminal input2 is initialized in the state of the potential of the logical inversion of the function function configuration data.

In the time segment 3, when the terminal ctl2 is set to the ground potential, the function / function configuration data holding control circuit 1
Depending on 305, terminals input2 [1] to input
2 [4] and terminals input2 [1a] to input2
The connection with [4a] is cut off, and the terminal input
2 [1a] to input2 [4a] are connected to the power supply potential.

Further, the signal propagation control circuit 1308 controls the output terminal of the pre-inverter and the main inverter 1.
The input terminal of 300 is connected. By this operation,
The terminal input2 is connected to the pre-inverters 1301 to 130.
4 is not connected, the output of the integrated circuit IC4 is not affected by the state of the terminal input2. In FIG. 18, inp in the item of terminal potential during execution of function processing
The horizontal bar of the ut2 term indicates that any value may be used.

In this state, the symmetric function function can be realized by inputting the signal V _sig to be processed by the symmetric function to the terminals input1 [1] to input1 [3] which are the terminal input1. To the terminal input2,
It is possible to realize a desired symmetric function function by inputting the potential of the logical inversion of the function function configuration data, initializing the floating gate, and then reconnecting to the power supply potential. Example)).

FIG. 19 shows, in the selector function which is the third mode in the integrated circuit IC3, the signal selected by the address is not held while the address corresponding to the selected signal is held. It is a figure which shows the procedure which implement | achieves the mode to output.

The view of FIG. 19 is the same as the view of FIG.

In the third mode of the integrated circuit IC3, the operation performed during the initialization time is almost the same as the operation in the first mode. The operation of the third mode differs from the operation of the first mode in that when the selector function is executed, the terminals input1 [1] to input1 [3]
To the terminals input2 [1] to inpu, by inputting the potential combination V _sel of the address signals of the selected data.
The point is to give a combination of signal potentials of the selected data to t2 [4].

The first mode, the second mode, and the third mode described above can also be realized in the integrated circuit IC3.

FIG. 20 is a diagram showing a procedure for realizing the mode for holding the address for the selected data in the selector function which is the fourth mode which cannot be realized by the integrated circuit IC3.

In time segment 1, terminals ctl1 to ct1
l4 is set to the power supply potential, the logically inverted potential of the address signal of the selected data is input to the terminal input1, and the terminal input2 is set to the ground potential.

The "potential of logical inversion with respect to the address signal of the selected data" means, for example, in the integrated circuit IC4 initialized in the procedure of FIG.
The potentials of [1] to input1 [3] are (V _dd , V _dd ,
0), the terminal input2 [3] is selected and becomes (0,
0, V _dd ).

In the time section 2, the potential of the terminal ctl4 is set to the ground potential, so that the floating gate initialization NMOSFET 1311 of the main inverter 1300 and the pre-inverters 1301 to 1304 and the NMOSFET 1311.
The NMSOFET typified by the MOSFET 1312 is cut off.

In time segment 3, when the potential of the terminal ctl3 is set to the ground potential, the selected data holding control circuit 13
06, terminals input1 [1] to input1
[3] and terminals input1 [1a] to input1
[3a] is cut off, and terminals 1nput1 [a] to inp
ut1 [3a] is connected to the power supply.

In time segment 4, in time segment 3, terminals input1 [1] to input1 [3] are connected to pre-inverters 1301 to 1304 and main inverter 1300.
Since it was cut off from the input terminal of, it is connected to the ground. This operation is not always necessary and does not affect the circuit even if any potential is input.

When the potential of the terminal ctl1 is set to the ground potential in the time division 5, the signal propagation control circuit 1308 connects the output terminals of the pre-inverters 1301 to 1304 and the input terminal of the main inverter 1300, and the potential changeover switch 1313. The PMOSFET becomes conductive and one of the input terminals of each of the pre-inverters 1301 and 1302 is connected to the power supply. In this state, the selector function can be executed. The selected data is data in which the potential of the logical inversion of the address is held in advance.

In FIG. 20, the horizontal bar indicates the potential during the execution of the selector function for the terminal input1.
It means that the potential of nput1 [1] to input1 [3] may be any potential.

The procedure described above makes it possible to execute four modes.

21, FIG. 22, FIG. 23, and FIG. 24 are diagrams showing the results of circuit simulation for confirming the operation of the integrated circuit IC4.

FIG. 21 shows the first mode in which the 3-input symmetric function function is realized in the integrated circuit IC4.

The vertical axis represents the potentials of the terminals ct11 to ctl4,
Terminals input1 [1] to i which are first input signal terminals
The potential of nput1 [3], the potentials of the terminals input2 [1] to input2 [4] that are the second input signal terminals, and the potential of the terminal output are shown, and the horizontal axis represents time in μsec unit.

Further, on the upper horizontal axis of FIG. 21, the logical names realized during a predetermined time segment are described. Figure 2
In 1, the pre-processing for the processing to be executed, such as the initialization of the floating gate, is performed at the time of the first vertical dotted line for realizing each logic function.

The potentials of the terminals ctl1 to ctl4 are as shown in FIG.
You can confirm that it is as shown in.

During the period of 0 to 1 μsec, the potentials of the second input signal terminals input2 [1] to input2 [4] are data forming a symmetric function, and the same potential is maintained during the function processing. , First input signal terminals input1 [1] to inpu, which are input data to be function-processed
It can be seen that the identity that logically outputs "1" is realized for any combination of the potentials of t1 [3].

During 1 to 2 μsec, NAND is realized, during 2 to 3 μsec, XNOR is realized, and 3 to 4 are realized.
NOR is realized during μsec, OR is realized during 4-5 μsec, XOR is realized during 5-6 μsec, AND is realized during 6-7 μsec, and 7-8
It can be seen that NULL is logically output “0” for any combination of the first input signals during μsec.

FIG. 22 shows the second mode, which is a second input signal terminal which is a terminal for inputting data constituting the symmetric function function, that is, terminals input2 [1] to input2.
It is shown that the three-input symmetric function function is realized by temporarily inputting the logically inverted data of the data forming the symmetric function function to t2 [4].

The ordinate and abscissa of FIG. 22 have the same meaning as in FIG. In FIG. 22, at the time of the first vertical dotted line for realizing each logic function, pre-processing for processing to be executed such as initialization of the floating gate is performed.
It can be confirmed that the potentials of the terminals ctl1 to ctl4 are as shown in FIG.

In addition, the terminals input2 [1] to inpu
When the potential of t2 [4] is compared with the case shown in FIG. 21, the potential of the logical inversion of the applied potential is shown in FIG. 22 at the time when each symmetric function function of FIG. 21 is executed. In some cases, it can be confirmed that the voltage is applied during each initialization time.

That is, in the case of realizing the XNOR function in the range of 2 μsec to 3 μsec, if the data constituting the symmetric function function is not held as shown in FIG. 21, the terminal input2 [1] of the terminal input2 [1] is processed during the function processing. Potential is V
_dd , the potential of the terminal input2 [2] becomes 0,
The potential of the terminal input2 [4] becomes V _dd , and the terminal in
While the potential of the put2 [4] becomes 0, if the data forming the symmetric function function is held as shown in FIG. 22, the potential of the terminal input2 [1] is set to 0 during the initialization time. Then, the potential of the terminal input2 [2] is set to V _dd , the potential of the terminal input2 [3] is set to 0, and the potential of the terminal input2 [4] is set to V _dd .

During 0 to 1 μsec, identity is realized, and during 1 to 2 μsec, NAND is realized.
Realizes XNOR for ~ 3μsec, 3 ~ 4μse
NOR is realized during c, and O is maintained during 4 to 5 μsec.
Realize R, and realize XOR for 5 to 6 μsec.
AND is realized for 6 to 7 μsec, and 7 to 8 μse
It can be seen that during c, NULL that logically outputs "0" is realized for any combination of the first input signals, and thus the 3-input symmetric function function is realized.

FIG. 23 shows the third mode, in which the three first input signals are used as control inputs and the number of input states is four.
It is a figure which shows having implement | achieved the selector function which selects one from two 2nd input signals.

The vertical axis represents the potentials of the terminals ctl1 to ctl4,
Terminals input1 [1] to i which are first input signal terminals
The potential of nput1 [3], the potentials of the terminals input2 [1] to input2 [4], which are the second input signal terminals, and the potential of the terminal output, the horizontal axis represents time μsec.
It is expressed in units.

Further, in FIG. 23, the upper horizontal axis shows the terminal name of the signal selected during a certain time segment. Pre-processing including initialization of the floating gate is performed in the time between the first vertical dotted lines for realizing the selector function for selecting each signal. It can be confirmed that the potential shown in FIG. 19 is applied during the initialization time and the selector function execution time.

During 0 to 1 μsec, the potential of the terminal input2 [1] is set to 0 by setting the potentials of all terminals of the terminals input [1] 1 to input1 [3] to the ground potential 0 during execution of the selector function. Selected, 1
Between ~ 2 µsec, 2 ~ 3 µsec, and 3 ~ 4 µsec, in terminals input1 [1] to input1 [3],
The number of input states is set to 1 by setting the potential of one different terminal to the power supply potential, and the terminal input2
Select [2] and select 4-5μsec, 5-6μsec, 6
Terminal input1 [1] to inp for up to 7 μsec
In ut1 [3], the number of input states is set to 2 by setting the potentials of two terminals having different combinations to the power supply potential, and the terminal input2 [3] is selected, and 7 to 8 μsec.
Between them, the terminal input1 which is the first input signal terminal
By setting the potentials of all the terminals [1] to input1 [3] to the power supply potential, the number of input states is set to 3, and the terminal input2 [4] is selected.

In FIG. 23, since the output potential of the terminal output matches the potential of the selected terminal,
It can be seen that the selector function is realized.

FIG. 24 shows the fourth mode, which is a first input signal terminal which is a terminal for inputting an address of data to be selected, that is, terminals input1 [1] to input1.
At t1 [3], the data of logical inversion of the address data is temporarily input during the initialization time, so that four second input signal terminal terminals input2 [1] to input2.
This shows that the selector function for selecting the signal of one terminal from t2 [4] is realized.

The ordinate and abscissa in FIG. 24 are the same as those in FIG. In FIG. 24, preprocessing including initialization of the floating gate is performed in the time between the first vertical dotted lines for realizing the selector function for selecting each signal. It can be confirmed that the potential shown in FIG. 20 is applied during this initialization time and during the selector function execution time. In addition, terminals input1 [1] to in
The potential of put1 [3] is compared with FIG.
It can also be confirmed in FIG. 24 that the potential of the logical inversion of the potential applied during the execution of the selector function of FIG. 23 is applied during each initialization time.

For example, when the signal of the terminal input2 [2] is selected during 1 μsec to 2 μsec, if the address data is not held as shown in FIG. 23, the terminal input1 [1] is output during execution of the selector function. ] Becomes V _dd , and the potential of the terminal input1 [2] becomes 0
Therefore, the potential of the terminal input1 [3] is 0, whereas if the address data is held as shown in FIG. 24, the terminal input1 [3] is retained during the initialization time.
The potential of [1] is set to 0, the potential of the terminal input1 [2] is set to V _dd, and the potential of the terminal input1 [3] is set to V _dd .

Between 0 and 1 μsec, during the initialization time,
By setting the potentials of all the terminals of the terminals input1 [1] to input1 [3] to the power supply potential V _dd ,
Select the potential of ut2 [1], 1-2 μsec, 2-3
Between μsec and 3 to 4μsec, during each initialization time,
By setting the potential of one of the terminals input [1] 1 to input1 [3] different from each other to the ground potential 0, the terminal input2 [2] is selected and 4 to 5 μm is selected.
sec, 5 to 6 μsec, and 6 to 7 μsec, the terminals input1 [1] to input1 during each initialization time.
In [3], the potentials of the two terminals of different combinations are set to the ground potential 0, so that the terminal input2
[3] is selected, and the terminal input1 [1] which is the first input signal terminal is input during the initialization time for 7 to 8 μsec.
The terminals input2 [4] are selected by setting the potentials of all the terminals of input to input1 [3] to the ground potential 0.

In FIG. 24, since the output potential of the terminal output matches the potential of the selected terminal, it can be seen that the selector function is realized.

As described above, in the integrated circuit IC4 in which the function and function can be reconfigured, even after the integrated circuit is manufactured, it is possible to reconfigure the symmetric function, which is a feasible logical function, and at the same time, the selector function is obtained. In the case of realizing the symmetric function function, it is possible to freely select the first mode in which the data forming the function function is not held and the second mode in which the data forming the function function is held, and to realize the selector function. Can freely select the third mode in which the address data is not held and the fourth mode in which the address data is held, and thus the four modes can be freely selected.

That is, the integrated circuit capable of reconfiguring the function / function of the above-mentioned embodiment can take out only the symmetric function, which is often used in the logic circuit, from the Boolean function, and at the same time, in the same circuit, only the symmetric function / function can be obtained. Not
It also has a selector function, and it is possible to switch the above two functions as needed by a mode switching circuit.

Further, the data forming the function function can be held without using a dedicated memory element or memory circuit, and the integrated circuits IC1 to IC4 can be used as a memory circuit. That is, the above embodiment integrates the three functions of the symmetric function function, the selector function, and the memory function.

The above-described embodiment adopts the configuration in which only the symmetric functions that are frequently used in the logic LSI are taken out from the Boolean functions, so that all Boolean functions like the conventional reconfigurable device are adopted. In order to reduce the area and compensate for the deterioration of the function, the structure that also has the selector function is used.

Further, in the above embodiment, by applying the threshold element for realizing the threshold logic to the feedforward type two-stage logic, the above symmetric function function and selector function can be realized.

A circuit configuration having k + 1 threshold elements in the first stage and one threshold element in the second stage is adopted, and k first input signals are provided in each of the threshold elements in the first stage. And a second input signal, which is an input signal specific to each threshold element, and two threshold values of the threshold elements are all different values. When the number of input states is a predetermined number generated by one input signal, the sum of products of the signal value of the input signal and the weight of the threshold element, and the sum of products for the next number of input states Set to a value between the calculated value.

The threshold element of the second stage has two kinds of signals as a first input signal and a logical inversion of the output signal of the threshold element of the first stage, that is, a negative signal. At this time, the output value of the first threshold element or the logical value of the output value corresponding to the number of input states of the first input signal is adjusted by adjusting the weight and threshold value of the second threshold element. It becomes possible to output the inversion. The above function can be realized by controlling the threshold value of each threshold element in the first stage to a desired value by the second input signal.

A semiconductor region of the first conductivity type is provided on the substrate,
An insulating film is provided on a region which has a source and drain region which is a semiconductor of a second conductivity type different from the first conductivity type provided in the semiconductor region and which separates the source and drain regions. A semiconductor element having a floating gate electrode provided via the floating gate electrode capable of taking an electrically floating state, and having a plurality of gate electrodes capacitively coupled through the floating gate electrode and the insulating film. An element having a structure in which at least one of the semiconductor elements is connected to a terminal having a preset potential through a switch in at least one of the semiconductor elements is called a neuron MOS transistor with switch, As the above threshold element,
An inverter circuit composed of this neuron MOS transistor with a switch is used.

An inverter circuit composed of neuron MOS transistors with switches is called a neuron MOS inverter. K + 1 neuron MOS inverters are used in the first stage of the feedforward two-stage logic,
When viewed as a threshold element, all the weights for the first input signal are made equal, and the threshold value is set to each neuron MOS.
It is set between a certain number of input states and the number of input states obtained by adding "1" to the number of input states without overlapping in the inverter, and the logic of the second input signal which is an input unique to each neuron MOS inverter. The threshold value is set to be exceeded only when the target value is "1".

The second stage neuron MOS inverter receives k first input signals and k + 1 first stage neuron MOS inverter output signals. The weights for this input are all equal and the threshold is k. By setting in this way, the above function can be realized. Further, by operating the potential of the floating gate of the neuron MOS inverter with a switch, it becomes possible to have a property of a memory function of retaining a symmetric function function.

As described above, unlike the conventional reconfigurable device, the functional function reconfigurable integrated circuit of the above embodiment has both a symmetric function function and a selector function.
By using the neuron MOS inverter, it is possible to realize a high function having a memory function in a small area.

That is, in the above embodiment, in the integrated circuit which realizes the function function of k input variables (k is an arbitrary positive integer), k first input signal terminals and k + 1 second input signals are provided. In the terminal and the first input signal terminal, the number of terminals whose state of the first input signal terminal is logically either “1” or “0” is m (0 ≦ m ≦ k). When it is called that the number of input states is m, the number of input states of the first input signal terminal and the n (1 ≦ n ≦ k + 1) th input of the k + 1 second signal terminals are described. Corresponding means for making one-to-one correspondence between the states of the signal terminals, and the state of the n-th input signal terminal in the second input signal terminal or the second input when the number of input states is m. The logical inversion of the state of the n-th input signal terminal in the signal terminal is calculated by And means for the output state,
A function function reconfigurable integrated circuit having two functions of a k input variable symmetric function function and a selector function of selecting one from k + 1 second input signals by k first input signals Here is an example.

Further, in the above-mentioned embodiment, there are k + 1 threshold elements provided in the first stage of the two-stage logic and one threshold element provided in the second stage of the two-stage logic. , Above 1
Each of the k + 1 threshold elements provided in the stage has k first input signal terminals and one second input signal terminal that is different for each threshold element, The first threshold element of the first stage has k input terminals for inputting the first input signal and k + 1 inputs for inputting signals related to the output signals of the k + 1 threshold elements of the first stage. And each of the threshold elements in the first stage has different threshold values, and one threshold element in the second stage is one of the k + 1 threshold elements in the first stage. In the output signal,
A function function for inputting one of a signal having a weight having an opposite sign to the weight applied to the first input signal terminal and a signal having a positive weight added to the logically inverted signal of the output signal. It is an example of a reconfigurable integrated circuit.

Further, in the above-described embodiment, the semiconductor region of the first conductivity type is provided on the substrate, and the source is the semiconductor of the second conductivity type different from the first conductivity type provided in the semiconductor region. A floating gate electrode in an electrically floating state, which has an area and a drain area and which separates the source area and the drain area from each other, is provided through an insulating film, and is electrically connected, cut off, or electrically connected. Has a structure in which the floating gate electrode is connected to a terminal having a preset potential through an element that can take two states of high impedance, and the floating gate electrode and the insulating film are interposed. When a semiconductor element having a plurality of input gate electrodes capacitively coupled with each other is called a neuron MOS transistor with switch, Element having a structure including at least one MOS transistor, the element connected to the floating gate electrode of the neuron MOS transistor with switch, and the element capable of assuming two states of cutoff or electrically high impedance are made conductive. Potential of the floating gate electrode in the ON state, and the neuron MO with the switch in the ON state of the element
By controlling at least one of the potential of the input terminal of the S transistor and the potential of the input terminal of the neuron MOS transistor when the element is in the cutoff state, a circuit having both a symmetric function function and a selector function is provided. It is an example of a functional function reconfigurable integrated circuit to be configured.

Further, the above-mentioned embodiment has a two-stage logic,
The semiconductor device has k + 1 semiconductor elements in the stage and one semiconductor device in the second stage, and each of the k + 1 semiconductor devices in the first stage has k first input signal terminals. And a second input signal terminal that is different in each semiconductor element and a terminal connected to zero or more terminals with a preset potential, and the one semiconductor element in the second stage is , K + 1 input terminals for inputting a first input signal and k + 1 input terminals for inputting signals related to output signals of the k + 1 semiconductor elements in the first stage, and the first stage All of the semiconductor elements have different threshold values from each other, and one semiconductor element in the second stage is k
It is an example of a functional function reconfigurable integrated circuit in which a signal obtained by multiplying a logically inverted signal of output signals of +1 semiconductor elements by a positive weight is input.

Further, the above embodiment is an example of a functional function reconfigurable integrated circuit having a switching circuit for selecting one of the symmetric function function and the selector function.

In the above embodiment, when the symmetric function function is realized, the first mode for realizing the symmetric function function only during the time when the data forming the symmetric function function is input,
A second mode in which it is possible to retain the data that constitutes the symmetric function function, and a third mode in which the selector function is realized only when the address for the selected signal is input when realizing the selector function. And the mode for holding the address for the selected signal.
4 is an example of a functional function reconfigurable integrated circuit having a control circuit for switching between four modes.

The above embodiment has a source region and a drain region which are semiconductors of the second conductivity type different from the first conductivity type provided in the semiconductor region. A floating gate electrode that is in an electrically floating state and is provided via an insulating film on a region that separates the In addition, it is defined as a concept including a state in which the impedance is electrically high.

[0257]

According to the present invention, it is possible to reconfigure the logical function even after manufacturing, have both the symmetric function function and the selector function, and do not use a dedicated memory element or memory circuit. It is possible to hold the function / function configuration data, and therefore, it is possible to achieve a high function in a small area on the integrated circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing the configuration and principle of an integrated circuit IC1 capable of reconfiguring a function / function according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an integrated circuit IC2 with reconfigurable function and function according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a functional function reconfigurable integrated circuit IC2a having three first input signal terminals and four second input signal terminals and configured by a threshold element.

FIG. 4 is a diagram illustrating the operation of an integrated circuit IC2a with reconfigurable function and function.

FIG. 5 is a diagram showing an example of an AND circuit which is one of symmetric functions.

FIG. 6 shows an integrated circuit IC3 having a k-input variable symmetric function function and a selector function for selecting one from k + 1 data inputs by k control inputs, and
It is a figure which shows the circuit structural example in the case of implement | achieving using the neuron MOS transistor ((nu) MOS) which is one.

FIG. 7 is a circuit diagram specifically showing a pre-inverter 601.

8 is a functional circuit reconfigurable integrated circuit IC shown in FIG.
3 is a circuit diagram showing the main component circuit in FIG.

9 is a diagram showing a procedure regarding a terminal potential when realizing a symmetric function function in the circuit of FIG.

10 is a diagram showing a procedure regarding a terminal potential when a selector function is realized in the circuit of FIG.

11 is a diagram showing a result of a circuit simulation performed to confirm the operation of the circuit shown in FIG. 6, and is a diagram showing that a 3-input symmetric function function is realized.

FIG. 12 is a diagram showing a result of a circuit simulation performed to confirm the operation of the circuit shown in FIG.
It is a figure which shows having implement | achieved the selector function which selects one from two 2nd input signals.

FIG. 13 has a three-input variable symmetric function function and a selector function that selects one from four data inputs by three control inputs, and holds data that constitutes each function, that is, a symmetric function. A diagram showing a functional function reconfigurable integrated circuit IC4 that realizes a circuit that can hold what kind of symmetric function if it is a function, and can hold a value that specifies a signal line to be selected if it is a selector function Is.

FIG. 14: Neuron MOS inverter with switch M
It is a figure which shows I.

FIG. 15 is a diagram showing a pre-inverter 1301.

FIG. 16 is a diagram showing a main inverter 1300.

FIG. 17 is a diagram showing a procedure for realizing the first mode in the integrated circuit IC4.

FIG. 18 is a diagram showing a procedure for realizing a second mode for holding data in the integrated circuit IC4.

FIG. 19 is a procedure for realizing a mode in which a signal selected by an address is output only while inputting the address without holding an address for the selected signal in the selector function similar to the integrated circuit IC3. FIG.

FIG. 20 is a diagram showing a procedure for realizing a mode for holding an address for selected data in a selector function which is a fourth mode which cannot be realized by the integrated circuit IC3.

FIG. 21 is a diagram showing a result of circuit simulation for confirming the operation of the integrated circuit IC4.

FIG. 22 is a diagram showing a result of a circuit simulation for confirming the operation of the integrated circuit IC4.

FIG. 23 is a diagram showing a result of circuit simulation for confirming the operation of the integrated circuit IC4.

FIG. 24 is a diagram showing a result of circuit simulation for confirming the operation of the integrated circuit IC4.

FIG. 25 is a diagram showing a configuration of a conventional table lookup (LUT) type variable logic unit.

FIG. 26 is a diagram showing a configuration of a conventional multiplexer (MUX) type variable logic unit.

FIG. 27 is a configuration diagram of a conventionally known PLA type variable logic unit.

FIG. 28 is a circuit diagram of a conventional CMOS type SRAM cell.

[Explanation of symbols]

IC1, IC2, IC3, IC4 ... Integrated circuit capable of reconfiguring function / function, 600, 800, 1300 ... Main inverter, 601-604, 801-804, 1301-1304
... pre-inverter, 605, 1307 ... mode switching circuit, 606 ... data holding control circuit, 607, 805, 1316 ... output buffer, 608, 1308 ... signal propagation control circuit, 609, 1309 ... waveform shaping circuit, 610, 1310 ... main Inverter input gate initialization NMOSFET, 611, 1311 ... Main inverter floating gate initialization NMOSFET, 612, 1312 ... Pre-inverter floating gate initialization NMOSFET, 613, 1313 ... Potential changeover switch, 614, 615, 1314 , 1315 ... Delay generation circuit, 1305 ... Function function configuration data holding control circuit, 1306 ... Selection data holding control circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-77427 (JP, A) JP-A-48-25261 (JP, A) JP-B-41-1163 (JP, B1) (58) Field (Int.Cl. ⁷ , DB name) H03K 19/177 G06F 7/00 H01L 27/10 371

Claims (9)

(57) [Claims] 1. An integrated circuit for realizing a function function of k input variables (k is an arbitrary positive integer), k first input signal terminals; k + 1 second input signal terminals; 1 input signal terminal, the first
When the number of terminals whose input signal terminals are logically either "1" or "0" is m (0≤m≤k), when the number of input states is called m A corresponding means for making a one-to-one correspondence between the number of input states of the first input signal terminal and the state of the n (1 ≦ n ≦ k + 1) th input signal terminal in the k + 1 second signal terminals. When the number of input states is m, n at the second input signal terminal
Means for making the output state of the integrated circuit the logical inversion of the state of the second input signal terminal or the state of the nth input signal terminal in the second input signal terminal;
Reconstruction of function function characterized by having two functions of k input variable symmetric function function and selector function of selecting one from k + 1 second input signals by k first input signals Possible integrated circuit. 2. The k + 1 threshold element provided in the first stage of the two-stage logic, and the one threshold element provided in the second stage of the two-stage logic according to claim 1. And each of the k + 1 threshold elements provided in the first stage has terminals for k first input signals,
Each of the threshold elements has one different second input signal terminal, and one threshold element in the second stage has an input terminal for inputting k first input signals and the one stage. And k + 1 input terminals for inputting signals relating to the output signals of the k + 1 threshold elements of the eye, and each of the threshold elements of the first stage has threshold values different from each other, One threshold element of the eye is k + 1 in the first stage.
Of the output signals of the threshold elements of the signal obtained by multiplying the signal having the sign opposite to the weight applied to the first input signal terminal, and the signal obtained by multiplying the logically inverted signal of the output signal by the positive weight. A functional function reconfigurable integrated circuit characterized by inputting one of the signals. 3. A source region and a drain region, which have a semiconductor region of a first conductivity type on a substrate and are semiconductors of a second conductivity type different from the first conductivity type provided in the semiconductor region. And a floating gate electrode that is in an electrically floating state and is provided via an insulating film on a region that separates the source region and the drain region, and has electrical continuity and interruption or electrically high impedance. The floating gate electrode is connected to a terminal having a preset potential via an element that can take two states, and a plurality of capacitors are capacitively coupled to the floating gate electrode via an insulating film. When a semiconductor element having an input gate electrode of a switch is called a neuron MOS transistor with switch, the neuron MOS transistor with switch An element that has a structure including at least one of the following, and that is capable of assuming two states of conduction, which is connected to the floating gate electrode of the neuron MOS transistor with a switch, and interruption or electrical high impedance, is in a conduction state. Of the potential of the floating gate electrode, the potential of the input terminal of the neuron MOS transistor with switch when the element is conductive, and the potential of the input terminal of the neuron MOS transistor when the element is in the blocking state A functional-function reconfigurable integrated circuit, characterized in that a circuit having both a symmetric function function and a selector function is configured by controlling at least one potential of 4. The threshold device according to claim 3, which is a two-stage logic, in which a threshold element using k + 1 semiconductor elements is provided in the first stage and one semiconductor element is used in the second stage. And each of the k + 1 threshold elements in the first stage has k first input signal terminals, one second input signal terminal that is different in each threshold element, and 0 or more. And a terminal connected to a terminal of a preset electric potential of, the one threshold element of the second stage has an input terminal for inputting k first input signals and a first stage. and k + 1 input terminals for inputting signals related to the output signals of the k + 1 threshold elements, each of the threshold elements in the first stage has a different threshold value from each other, and the second stage One threshold element of the above is k + 1
A functional function reconfigurable integrated circuit, wherein a signal obtained by multiplying a logically inverted signal of output signals of a plurality of threshold elements by a positive weight is input. 5. The function function reconfigurable integrated circuit according to claim 3, further comprising a switching circuit that selects one of a symmetric function function and a selector function. 6. The first mode according to claim 3 or 4, wherein, when realizing the symmetric function function, the symmetric function function is realized only during a time when data constituting the symmetric function function is input. A second mode in which it is possible to retain the data that constitutes the symmetric function function, and a third mode in which the selector function is realized only when the address for the selected signal is input when realizing the selector function. And a function circuit reconfigurable integrated circuit having a control circuit for switching between four modes, a fourth mode capable of holding an address for a selected signal. 7. The function / function reconfigurable device according to claim 3, wherein the threshold element using the semiconductor element is an element forming an inverter circuit. Integrated circuit. 8. The output terminal of the threshold element using the semiconductor element of the first stage and the threshold element of the threshold element using the semiconductor element of the second stage according to any one of claims 3 to 7. A functional function reconfigurable integrated circuit, wherein a circuit connecting to an input terminal is a circuit including a waveform shaping circuit. 9. The delay generation circuit according to claim 3, wherein a circuit on a signal path for supplying a signal to be an input of a threshold element using the semiconductor element of the second stage is a delay generation circuit. A functional-function reconfigurable integrated circuit, which is a circuit having: