JP3485231B2 - Data transfer method between buses, bridge device for connecting buses, and data processing system including a plurality of buses - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for controlling data transfer between buses in a data processing system including a plurality of buses, and for interconnecting the buses to enable data transfer between the buses. The present invention relates to a data processing system including a bridge device and a plurality of buses. In particular, the invention is
Including at least first, second, and third buses, and
Data transfer method between buses and connection between buses in a data processing system in which addresses on a second bus are assigned addresses within a predetermined range and devices on other buses are assigned addresses outside the predetermined range And a data processing system including a plurality of buses. More specifically, the present invention relates to a data transfer method between buses for suitably processing a data transfer request from a device on a second bus to another, a bridge device for connecting the buses, and a plurality of bridge devices. A data processing system including a bus.

[0002]

2. Description of the Related Art Bus environment of personal computer: With the recent technological innovation, various personal computers (PC) such as desktop type, tower type and notebook type have been developed and put on the market.

Inside these PCs, various controller chips including a host CPU and other components such as memories and peripheral devices are interconnected by a common signal transmission path called a "bus". The bus is embodied in the form of an expansion slot on the system board, and various expansion cards can be attached to the expansion slot.

The standardization of buses has a great impact on the computer industry. This is because system board manufacturers, expansion card manufacturers, etc. can manufacture and sell products according to standard bus specifications. In addition, the expansion of the surrounding environment allows PCs to be accepted by more users. This is because it becomes easy.

As a standard for bus architecture, ISA (Industry Standard Architectu) has been conventionally used.
re) has been widely known and used. The ISA bus is
It is designed in accordance with a CPU chip 80286 manufactured by Intel Corp. based on a bus adopted in IBM PC / AT (“PC / AT” is a trademark of IBM Corp. in the US). The basic performance of the ISA bus is 16-bit bus width,
Operation clock 8MHz, maximum data transfer rate 4MBps
Is. The ISA bus is one of the most widely accepted bus architectures to date.
Compatible with A (ie connectable to ISA bus,
It has abundant expansion boards, peripheral devices, and software (OS, BIOS, applications) that operate normally. That is, ISA is
It can be said that it is a bus architecture that inherited more of the "gacy".

However, recently, "PowerPC 6xx"("PowerPC6xx"("Power") jointly developed by i486 and Pentium of Intel Corp. of America or IBM Corp.
Like "PC" is a trademark of IBM Corp. in the US, a powerful CPU with an operating clock of more than 100 MHz has been developed and widely spread. Along with this, in an ISA bus with a narrow bus width and a low data transfer rate, , It has become impossible to take full advantage of the high-speed CPU, and a graphics and full-motion video subsystem, S
CSI (Small Computer System Interface) storage subsystems, network subsystems, and other subsystems / expansion boards that require high-speed data transfer have appeared, but these subsystems also have ISA bus data input / output capability. Is running out of roles.

Under such a situation, the power-up C
To support PUs and subsystems,
An architecture has been proposed and developed. One of these is PCI (Peripheral Component Interco
nnect). The PCI bus was originally 19
A specification draft was formulated by Intel Corporation of the United States in 1991, and is currently being standardized and popularized by members of the SIG (Special Interest Group). The basic performance of the PCI bus is a bus width of 32 bits, an operation clock of 33 MHz, and a maximum data transfer rate of 132 MBps. In addition, PCI
In, the address and data are multiplexed, and there is no need to separate address lines and data lines. Therefore, the number of signals required for the PCI bus is reduced to about half that of other bus environments, and the number of connection pins for devices supporting the PCI bus connection is reduced. In PCI, in addition to PIO (programmable I / O transfer) in which the CPU transfers data, a device on the PCI bus (master device)
A bus master transfer that controls the bus to transfer data is also defined. For details on the structure and operation of the PCI bus architecture, see "PCI LocalBus Sp
ecification, Revision 2.0 "(Copyright 1992,1993)
And "PCI to PCI Bridge Architecture Specification,
Revision 1.0, 1994 "(original issue).

Features of PCI bus (1): The PCI bus is
It provides a wide bus width and high-speed clock, and is positioned as a local bus for the CPU. In the PCI bus, for example, in addition to a video controller that exhibits a drawing function,
PCMCIA (Personal Computer Memory Card Inte) that realizes interface protocol with PC card
rnational Association) controller, SCSI or L
An expansion board or the like of an AN (Local Area network) is connected. For example, connecting a video controller to the PCI bus can significantly enhance the display performance of the system.

Some devices connected to the PCI bus and the ISA bus can acquire the control right of the bus and send a command by themselves to execute the processing without using another device (for example, a CPU). There is a "master" device (or called an "initiator" device). There are also devices on the bus that receive commands sent in response to requests from the master, but these are called "slave" devices (or "target" devices). Many of the devices connected to the bus are designed to act as either masters or slaves, depending on the circumstances encountered.

For example, according to the PCI protocol, PCI
The master indicates the start of a transaction by asserting the "frame" signal (FRAME #). One PCI slave is P
It is specified that the CI master must respond within a predetermined time. That is, the PCI slave interprets the address transmitted on the PCI bus (the "address" here includes both the I / O address and the memory address, and so on), and the PCI slave itself targets the transaction. Then, the bus cycle is requested by asserting the "device select" signal (DEVSEL #) at a predetermined timing. That is, the PCI master requests a transaction by asserting the frame signal and the PCI slave acknowledges by asserting the device select signal.
That is, the PCI bus cycle is established. When the device selection signal is not received from the PCI slave within the predetermined time, the PCI master must execute a master abort (abort) to forcibly end the bus cycle.

In the PCI bus protocol, as a "predetermined timing" at which a PCI slave asserts a device selection signal, the PC signal is asserted after the frame signal is asserted.
3rd clock (Fast: high speed) with I-bus clock,
Three types of timings are defined: the fourth clock (Medium: medium speed) or the fifth clock (Slow: low speed) (see FIG. 11). In addition, the slave itself
The method of interpreting the address on the line and giving a positive response is called "Positive Decoding". An apparatus that adopts the positive decoding method may also be referred to as a "positive apparatus".

In addition, in the PCI bus protocol, as a special operation other than positive decoding, "subtractive decoding" is performed.
g) ”is defined. What is subtractive decoding? Fast, Med
Only when the device selection signal is not asserted at any of the ium and Slow timings, that is, when no positive device on the PCI bus responds to the request, the device recognizes itself as a slave device, and the Slow signal is detected.
Is an address interpretation method in which the device selection signal is asserted at the clock timing next to (see FIG. 11). A device that employs a subtractive decoding method is sometimes called a "subtractive device". In the PCI bus architecture, there is only one on one PCI bus
There can only be one subtractive device.

Characteristic (2) of PCI bus: Another characteristic of PCI is that connection with another bus is allowed by interposing a bridge chip as a bus cycle conversion circuit. For example, PCI bus and ISA bus are PCI
PCI to P between PCI buses with a toISA bridge
Each can be interconnected with a CI bridge. In addition, a bridge circuit (host t
By providing an oPCI bridge, a specific type of CPU chip (eg Intel x86 CP
U) as well as other types of CPUs (eg IBM
It is also possible to use "PowerPC" developed by the company.

In many current PCs, the PCI bus having a high input / output capability is used as a local bus, and the ISA operates in accordance with relatively low speed peripheral devices.
It uses a multiple bus architecture that uses the bus as an expansion bus. The PCI bus and the ISA bus are interconnected by a PCI to ISA bridge, and as a result, while enjoying the high-speed input / output function of PCI, a rich I
This means that you can take over SA assets as they are.

The bridge-connected buses are driven independently (that is, asynchronously). Therefore, even if a large number of devices are connected to one PCI bus, no load is given to other buses.
It can be said that CI has excellent electrical characteristics and stability. Also, the number of connectable devices can be increased by extending the bus with the bridge circuit.

Generally, the connection portion of the bridge circuit close to the CPU (that is, the host) is called the primary side,
Connect the connection part on the opposite side (that is, the peripheral side) to the secondary side (se
condary). The bridge circuit is also considered as one of the devices on the PCI bus and its main role is to perform bus cycle conversion between the primary and secondary buses. That is, the bridge circuit allows a bus transaction from a device on the primary side bus (hereinafter referred to as “primary side device”) to a device on the secondary side bus (hereinafter referred to as “secondary side device”). When issued, it will respond on behalf of the secondary device on the primary bus with an affirmative response,
On the secondary bus, the bus transaction is initiated on the secondary bus on behalf of the primary device. Conversely, when a bus transaction is issued from the secondary side device, the secondary side device acts on behalf of the primary side device and acknowledges, and on the primary side bus, the secondary side device takes the place of the bus transaction. Initiate the transaction on the primary bus.

The PCI to PCI bridge is a chip for connecting PCI buses to each other (described above), and its specification is "PCI to PCI BRIDGE ARCHI".
TECTURE SPECIFICATION Rev
Ision 1.0 ". According to the specification, the PCI to PCI bridge is defined as" Memory / I ".
O Base / Limit Register "function is supported. This is the primary PCI device and 2
By partitioning the memory address area and I / O address area that can be used with the secondary PCI device, each PC
This is because the device on the I bus can be uniquely accessed. For example, when an access request is issued on the primary PCI bus, only 2 when the specified address is the usable address area of the secondary PCI device.
The PCI-to-PCI bridge blocks access to other addresses without being initiated on the secondary PCI bus. When an access request is issued on the secondary PCI bus, the designated address is the secondary P
1 only when it is outside the usable address area of the CI device
It is not initiated on the next PCI bus, and other access is blocked by the PCI to PCI bridge.

FIG. 12 shows a "Memory / IO Base / Limit Re" of a PCI to PCI bridge.
gister "function (hereinafter referred to as" block function ")
Are schematically shown using an I / O address map. The shaded area in the figure, that is, the I / O address area (hereinafter referred to as "block area") partitioned by the I / O base address and the I / O limit address is the secondary PC.
This area is exclusively used by the I device. Primary PCI
The device can use only the other I / O address area. The PCI to PCI bridge has a register for storing the base address and the limit address in order to set the block area. On the other hand, the ISA device is not PnP compatible (described later), but the address to be used is traditionally determined depending on the type of device. For example, expansion adapter cards installed in ISA bus slots # 1 and # 2 are '800'h to'807'h and '300'h, respectively.
~ '305'h I / O address area is used, serial port and parallel port are'3E8'h ~ '3EF'h, '77 respectively.
The I / O address area of 8'h to '77A'h is used. The block area is usually set avoiding the addresses used by these ISA devices.

The PCI-to-PCI bridge generally supports the subtractive decoding method (described above) on the primary PCI bus. This is downstream, ie 2 from the master on the primary side.
This is because the data transfer to the slave device on the next side is taken into consideration. The subtractive PCI to PCI bridge is
It responds positively to the access request to the PCI device and operates subtractively when none of the PCI devices asserts the device selection signal within a predetermined time.

The PCI-to-PCI bridge that supports the block function and the subtractive decoding operation responds positively to the access request from the primary PCI device to the block area and responds positively to the secondary PCI.
Enables device bus cycle acquisition. In addition, this type of PCI to PCI bridge responds positively to the access request from the secondary PCI device to the primary PCI device outside the block area and acquires the bus cycle of the primary PCI device. It is possible. Furthermore, this type of PCI to PCI bridge responds subtractively to requests for access to ISA devices outside the block area, and the secondary side P
ISA bus connected to CI bus (secondary ISA bus)
A bridge has been realized.

Although not illustrated here, the PCI to PCI bridge also realizes the block function for memory addresses in the same manner.

PCI Bus Feature (3): Another PCI feature is PnP (Plug and
Play) is the point that corresponds. Here, PnP is a function in which the system side automatically recognizes its own surrounding environment. On a PnP-compatible system, even if the number and types of devices on the system change, such as inserting an expansion board into an expansion slot, you can use it as is without performing complicated operations such as DIP switch settings. It is a function that enables it. This is because, on a PnP-compatible system, "system resources" such as DMA level, IRQ level, I / O address, memory address, etc. are automatically set for a newly added device and are also extracted. The system resources used by the device are automatically released. In other words, P
The address used by the PCI device that supports nP is
The system itself can automatically recognize it.

On the other hand, most of the ISA devices (that is, devices connected to the ISA bus) are not PnP compatible,
Therefore, the system side cannot recognize the address used by the ISA device. For example, PnP is installed in the bus slot on the ISA bus bridge-connected to the PCI bus.
If an unsupported expansion adapter card is installed,
The PCI to ISA bridge cannot recognize the address used by this expansion adapter card. Therefore, the PC
Even if an access request to an ISA device that does not support PnP is issued on the I bus, it is difficult for the PCI to ISA bridge to respond positively to this because the used address of the ISA device is unknown. Therefore, PCIt
It is widely adopted to design oISA bridges as subtractive devices. The subtractive PCI to ISA bridge asserts the device selection signal by itself and transmits the access request to the ISA bus only when the device selection signal is not asserted on the PCI bus within a predetermined time (that is, positive). In short, an ISA device (for example, an add-in expansion adapter card) whose system side cannot recognize the used address does not operate on the bus only when none of the PnP compatible PCI devices requests the bus cycle.
It means that you can get a cycle.

Transactions on the PCI Bus: PCI
The bus architecture is that the PCI bus allows interconnection with other buses via a bridge chip, and that many PCs currently on the market allow a mixed PCI bus and an ISA bus. The points adopted are already mentioned. Therefore, the hardware configuration of the PC may be schematically shown as in FIG.

In the figure, as the hardware of the PC, a primary PCI bus, a secondary PCI bus, and an ISA
There are three independent bus environments called buses.
The "primary" and "secondary" prefixes on the two PCI buses are only meant to be close to the host CPU. The PCI buses are connected to each other by a PCI to PCI bridge chip. Further, various PCI devices having a PCI protocol are connected to each PCI bus.

An ISA bus is connected to each PCI bus via a PCI to ISA bridge chip. In this specification, an IS bridge-connected to the primary PCI bus is used.
The A bus will be referred to as a secondary ISA bus by referring to the ISA bus bridge-connected to the primary ISA bus and the secondary PCI bus. Various ISA devices having an ISA protocol are connected to each ISA bus.

The secondary PCI bus is a primary PCI.
In some cases, it may be built into the bus or system itself,
When deployed in a docking station of a notebook PC (for example, Japanese Patent Application No. 8-31699 assigned to the applicant (our reference number: JA99512)
8)).

In the multiple bus environment as shown in FIG. 13, eight kinds of transactions are considered. Among them, five kinds of transactions which are considered to require relatively explanation are shown in Table 1 below. In addition to the table below, as the combination of master and slave, primary PCI device and primary PCI device, primary PCI device and primary PCI device
There are ISA devices, secondary PCI devices, and primary ISA devices.

[0029]

[Table 1]

First, when an access request is made from a device on the primary side PCI bus (ie, “primary side PCI device”) to a device on the secondary side PCI bus (ie, “secondary side PCI device”), a PCI to PCI bridge is issued. The bus cycle is established by the circuit responding positively, initiating an access request on the secondary PCI bus, and then responding by the secondary PCI device.

From the primary PCI device to the secondary I
When an access request is made to a device on the SA bus (that is, a “secondary ISA device”), the PCI to PCI bridge responds on a subtractive basis, and then the secondary P
By the CItoISA bridge acting as a subtractive proxy response, the access request is transmitted on the ISA bus, and the secondary ISA device can be accessed.

From the secondary PCI device to the primary P
When requesting access to a CI device, PCI to PC
When the I bridge circuit responds positively on its behalf, 1
The bus cycle is established by initiating an access request on the secondary PCI bus and then responding by the primary PCI device.

From the secondary PCI device to the secondary P
When requesting access to a CI device, a bus cycle is directly established on the secondary PCI bus. At this time,
The PCI to PCI bridge is blocked by the primary PC
No access request is initiated on the I bus.

The above four bus transactions are relatively easily supported by the PnP function of PCI, that is, the PCI to PCI bridge recognizes the used addresses of all PCI devices.

On the other hand, the fifth bus transaction in [Table 1], that is, 2 from the secondary PCI device
Access to the secondary ISA device is not easy to achieve. This is because the address used by the ISA device is outside the usable address area of the secondary PCI device (see FIG. 12), and the PCI to PCI bridge uses the IS
This is because the access request to the A device is not blocked. As a result of not blocking, the PCI to PCI bridge itself requests the bus cycle positively (that is, first) and the subtractive secondary side PCI to I
The SA device loses the opportunity to respond.

This state will be described with reference to the timing chart ^{/ * /} in FIG. However, in the figure, the prefix "P_" is the primary side (that is, "Primary") PC
It is a signal line in the I bus, and the prefix "S"
_ "Indicates a signal line in the PCI bus on the secondary side (that is," Secondary ") (the same applies hereinafter), and a signal line with a suffix" * "as a suffix indicates PCItoPC.
Means asserted by the I-bridge.

The bus cycle begins with the secondary PCI device asserting a frame signal (S_FRAME #) to initiate a transaction. Further, the secondary PCI device is connected to the address / data signal line (S
_AD [31: 1]) and the command / byte enable signal lines (S_C / BE [3: 0]). In addition, the secondary PCI device indicates that it is ready to send and receive data.
In addition to asserting the initiator ready signal (S_IRDY #), the address / data signal line (S_AD
[31: 1]) with data and command / byte enable signal lines (S_C / BE [3: 0]) with byte.
The enable values are transmitted respectively.

Here, the address transmitted on S_AD [31: 1] at this time is the usable address area (that is, the block area) of the secondary side PCI device defined by "Base / Limit Register" in the PCI to PCI bridge. ) Outside. Therefore, PCIt
The oPCI bridge illusions access to the primary PCI device, and positively selects a device selection signal (S_DEVSEL) as a target on the secondary PCI bus.
#) Will be asserted. As a result, the subtractive secondary PCI to ISA bridge loses the opportunity to win a bus cycle.

Next, the PCI to PCI bridge 1
On the secondary PCI bus, as a master device, in order to develop a bus transaction similar to that of the secondary PCI bus, after a predetermined delay time, a frame select signal (P_F
RAME #) and assert the same address on the address / data signal lines (P_AD [31: 1]) on the command / byte enable signal lines (P_C / B).
The same command is transmitted to each of E [3: 0]). In addition, the PCI to PCI bridge asserts the initiator ready signal (P_IRDY #) and
The same data is transmitted to the address / data signal lines (P_AD [31: 1]), and the same byte enable value is transmitted to the command / byte enable signal lines (P_C / BE [3: 0]). .

However, on the primary PCI bus,
Since no device actually hits the designated address, the device selection signal (P_DEVSEL #) is not asserted at any timing of Fast, Mediun, Slow, and subtractive. As a result, the PCI to PCI bridge waits for a predetermined time and then the initiator ready signal (P_IRDY #).
Is negated, there is no choice but to "master abort" the bus cycle on the primary PCI bus. On the secondary PCI bus, a stop signal (S_STOP
#) To assert the bus cycle
I have no choice but to abort.

In short, the secondary ISA device will not get a bus cycle and the data will not be transferred forever. Thus, the presence of inaccessible device combinations in the system is very likely to cause an abend or system hang.
This is of course very problematic in setting the standard protocol of PCI to PCI bridge.

Such a problem is based on the fact that only the secondary PCI to ISA bridge of the secondary PCI devices has to respond to access to areas other than the block area. A relatively easy solution to such a problem is
The system will be aware of all addresses used by the ISA device. To do this, for example, 2
A register for storing all the addresses used by the secondary ISA device is newly added to the PCI to PCI bridge, or the P of the ISA device is configured by software.
It only has to support the nP function.

However, according to the former, PCIto
It is necessary to add a considerable number of registers in the PCI bridge, which inevitably increases the number of gates and the chip area, resulting in an increase in cost. In the latter case, most of the currently available software does not support the secondary ISA device, and the ISA device itself does not support P.
Addresses cannot be managed in the first place unless they are compatible with nP, which is technically impossible.

<< Note >> *: The protocol of the PCI bus and the definition of each signal line are well known to those skilled in the art. Here, in order to facilitate understanding of the contents shown in the timing charts of FIGS. 11 and 14, the meaning of each signal line will be briefly described. i) FRAME # (frame signal) indicates that the master device (ie, initiator) is about to initiate a transaction on the slave device (ie, target).
Is a signal for indicating intention to the master device and is asserted by the master device. ii) IRDY # (Initiator Ready: created by the initiator
The ready signal) is a signal for indicating that the master device is ready to transmit / receive data, and is asserted by the master device. iii) DEVSEL # (Device Select: Device selection
Selection signal) is a signal for notifying the master device that a certain slave device has learned that it is the device selected as the target, and is asserted by the slave device that has decoded the address. In other words, DE
VSEL # is a signal for the slave device to request a bus cycle. iv) TRDY # (Target Ready: target ready
Signal) is a signal for indicating that the slave device is ready to transmit / receive data, and is asserted by the slave device. v) STOP # (stop signal) is a signal to indicate to the master device that the slave device cannot process the transaction, and is asserted by the slave device. vi) A master abort is a mode of operation defined for a master device to abort (abend) an ongoing transaction, when no device on the bus responds to the transaction as a target (ie DEVSEL #). Remains in the negated state). For master abort, the master device is IRDY
This is done by negating #. vii) Target abort is an operation mode defined for aborting (abnormal termination) of a transaction in progress by a slave device, and is used when an access that cannot be processed by the slave device is performed. For target abort, slave device is DEVS
While negating EL # and TRDY #, STOP #
The master device is notified by asserting. viii) Retry is one of the operation modes defined for the slave device to cancel the transaction being executed, and is used when the slave device is temporarily in a state where access cannot be accepted. It Unlike Target Abort means a complete abort of access, Retry literally means a retry of the transaction to the master device. The slave device is allowed to S while asserting DEVSEL #.
The master device can be notified of the retry by asserting TOP #.

[0045]

SUMMARY OF THE INVENTION The present invention focuses on the problems as described above, and an object of the present invention is to provide an excellent control for data transfer between buses in a data processing system including a plurality of buses. Another object of the present invention is to provide an excellent bridge device for interconnecting buses to enable data transfer between buses, and an excellent data processing system including a plurality of buses.

A further object of the invention is at least the first:
A data processing system including second and third buses, wherein devices on the second bus are assigned addresses within a predetermined range, and devices on other buses are assigned addresses outside the predetermined range. In the above, there is provided an excellent data transfer method between buses, an excellent bridge device for connecting between buses, and an excellent data processing system including a plurality of buses.

A further object of the present invention is PCI to PCI.
An object of the present invention is to provide an excellent data transfer method between buses, a bridge device for connecting between buses, and a data processing system including a plurality of buses, which eliminates a combination of devices that cannot be accessed via a bridge.

A further object of the present invention is the PCI bus and IS.
In a data processing system having a bus environment in which an A bus is mixed, an excellent bus-to-bus data transfer method by which a bus master on a bus can suitably access a bus slave and a connection between buses To provide a data processing system including a bridge device and a plurality of buses.

A further object of the present invention is a PC interconnected with another PCI bus by a PCI to PCI bridge.
PCI to I that operates in a subtractive manner that interconnects the I bus, the ISA bus, and the PCI bus and the ISA bus
In a data processing system having an SA bridge,
A master device on the PCI bus can favorably access a slave device that operates subtractively, an excellent data transfer method between buses, an excellent bridge device for connecting buses, and a plurality of buses It is to provide an excellent data processing system including.

[0050]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and a first aspect thereof is that a first bus and a first bridge device are used to interact with the first bus. A second bus connected to the second bus, and a third bus interconnected with the second bus by a second bridge device, the devices on the second bus using addresses within a range; A device on the other bus is a method for controlling data transfer between the buses in a data processing system using an address outside the predetermined range, wherein: (a) the device on the second bus is Requesting access to a device on a third bus; (b) the first bridge device responding to the access request and transmitting on the first bus; and (c) the first bus. All devices on the bus 1 In response to not responding to the access request, the first bridge device holds the address of the device requested to access and terminates the access request; and (d) on the second bus. Device retrying the access request; (e) the first bridge device not responding to the access request if the address of the access requested device is the same as the address held; ) In response to all other devices on the second bus not responding to the access request, the second bridge device responds to the access request and transmits on the third bus. And a step of transferring data between buses.

A second aspect of the present invention is a PCI-side PCI bus, PCIto, which acts as a local bus of the host CPU.
A secondary PCI bus interconnected with the primary PCI bus by a PCI bridge, and a secondary PCI bus interconnected with the secondary PCI bus by a PCI to ISA bridge.
Including a secondary ISA bus, the secondary PCI device on the secondary PCI bus uses an address within a predetermined range, and the primary PCI device on the primary PCI bus and the secondary ISA A secondary ISA device on a bus is a method for controlling data transfer between buses in a data processing system that uses an address outside the predetermined range, including: (a) a secondary PCI device 2 by asserting the frame signal of the side PCI bus
Initiating an access request to the secondary ISA device, and (b) responding to the access request by the PCI to PCI bridge asserting a device selection signal of the secondary PCI bus and accessing the primary PCI bus. Initiating the request,
(C) In response to all the PCI devices on the primary side PCI bus not asserting a device selection signal of the primary side PCI bus within a predetermined time, the PCItoP
The CI bridge holds the address of the access request destination and terminates the access request; (d) the secondary PCI device terminates the access request by retry; and (e) the address of the access request destination. Is the same as the held address, the PCIt
the oPCI bridge does not assert the device selection signal of the secondary PCI bus, and (f) the PCIto
An ISA bridge asserting a device select signal on the secondary PCI bus to respond to the access request and initiate the access request on the secondary ISA bus. This is a data transfer method.

Here, in the step (b), the P
More preferably, the CItoPCI bridge positively asserts the device select signal on the secondary PCI bus.

In the step (c), the PC
It is more preferable that the ItoPCI bridge terminates the bus cycle on the primary side PCI bus by a master abort and terminates the bus cycle on the secondary side PCI bus by a retry.

In the step (f), the PC
The ItoISA bridge subtractively asserts the device selection signal of the secondary PCI bus.
More preferable.

The third aspect of the present invention is PCIto, a primary side PCI bus which acts as a local bus of the host CPU.
A secondary PCI bus interconnected with the primary PCI bus by a PCI bridge, wherein a positive secondary PCI device on the secondary PCI bus uses an address within a range, and A primary PCI device on a secondary PCI bus and a subtractive secondary PCI device are methods for controlling data transfer between buses in a data processing system using an address outside the predetermined range. (A) First secondary PC
An I-device initiates a subtractive access request to the second secondary PCI device by asserting a frame signal on the secondary PCI bus; and (b) the PCI to PCI bridge Positively asserting the device selection signal of the above, and initiating the access request on the primary side PCI bus; and (c) the primary side P bus.
In response to the fact that all the PCI devices on the CI bus do not assert the device selection signal of the primary PCI bus within a predetermined time, the PCI to PCI bridge holds the address of the access request destination and also makes a retry format. Terminating the transaction on the secondary side PCI bus, and (d) in response to the retry, the first 2
When the secondary PCI device retries the access request, and (e) the address of the access request destination is the same as the held address, the PCI to PCI bridge asserts the device selection signal of the secondary PCI bus to be positive. And (f) the second secondary PCI device does not assert the device selection signal on the secondary PCI bus after all other secondary PCI devices have not positively asserted the device selection signal. And a step of subtractively asserting, and a data transfer method between buses.

The fourth aspect of the present invention is to provide a primary PCI bus that serves as a local bus for the host CPU and a secondary P bus.
A bridge device for interconnecting with a CI bus, comprising a storage means for storing address information of a bus cycle ended by a retry by itself, a bridge for connecting between buses It is a device.

The fifth aspect of the present invention is to provide a primary PCI bus that serves as a local bus for the host CPU and a secondary P bus.
A bridge device for interconnecting with a CI bus, a storage means for storing address information of a bus cycle terminated by a retry by itself, and a bus cycle for designating an address stored in the storage means Is a bridge device for connecting between buses, characterized in that it includes a decoding means that does not respond to.

A sixth aspect of the present invention is that the primary side PCI bus that acts as a local bus of the host CPU and the secondary side P bus.
A bridge device for interconnecting with a CI bus, comprising: (a) a secondary side P connected to the secondary side PCI bus.
First storage means for storing an address area in which only the CI device is permitted to use, and (b) second storage means for storing address information of a bus cycle ended by a retry by itself. (C) primary side decoding means for determining an address hit when the address is within the usable address area of the secondary side PCI device defined in the first storage means, and (d) the primary side In response to an address hit by the side decoding means, a bus cycle on the primary side PCI bus is transferred to the secondary side P bus.
A first transmitting means for transmitting on the CI bus; and (e) an address outside the usable address area of the secondary PCI device defined by the first storing means and in the second storing means. A secondary-side decoding means for judging an address hit only when there is no address, and (f) in response to an address hit by the secondary-side decoding means,
A first transmission means for transmitting a bus cycle on the secondary side PCI bus to the primary side PCI bus; and a bridge device for connecting between buses.

Here, the primary side decoding means performs subtractive decoding and the above-mentioned 2
It is more preferable that the secondary decoding means performs positive decoding.

A seventh aspect of the present invention is a data processing system having a multiple bus structure, which comprises (a) a main processor for controlling the overall operation of the system, (b) a main memory, and (c). A first bus connected as a local bus of the main processor, and (d) at least one first device connected to the first bus,
(E) a second bus, and (f) a bridge interconnecting the first and second buses, which, when itself terminates the bus cycle, retries a bus cycle that is not requested again An unrequested bridge, (g)
At least one second device connected to the second bus, and a data processing system including a plurality of buses.

An eighth aspect of the present invention is a data processing system having a multiple bus structure, including (a) a main processor for controlling the overall operation of the system, (b) a main memory, and (c). A primary side PCI bus connected as a local bus of the main processor; and (d)
At least one 1 connected to the primary PCI bus
A secondary PCI device, (e) a secondary PCI bus,
(F) A PCI-to-PCI bridge interconnecting the primary-side PCI bus and the secondary-side PCI bus, the decoding means positively decoding on the secondary-side PCI bus, and the secondary-side PCI bus. And a PCI to PCI bridge including decoding suppressing means for suppressing the decoding of the bus cycle retried due to the fact that the terminal itself has ended with the retry,
(G) at least one secondary-side PCI device of the positive decoding type connected to the secondary-side PCI bus, and (h) subtractively decoding connected to the secondary-side PCI bus. A data processing system including a plurality of buses.

Here, the secondary side PCI device (h) of the type for the subtractive decoding is 2
PCIt for connecting the ISA bus to the secondary PCI bus
It may be an oISA bridge.

[0063]

According to the hardware of the computer system that preferably implements the present invention, the primary PCI bus that serves as the local bus of the host CPU and the primary PCI bus are P
Secondary PCI connected via CItoPCI bridge
The PCI device and the ISA device are connected to the PCI bus and the ISA bus, respectively, in a multiple bus environment in which the bus and the secondary PCI bus are connected via the PCI to ISA bridge. It is a thing. Further, it is more preferable that the PCI to PCI bridge is a type that supports the block function (described above) and the subtractive operation, and that the PCI to ISA bridge is the subtractive operation type.

In a computer system implementing the present invention, it is assumed that a PCI bus cycle in which a secondary PCI device is a master and a secondary ISA device is a slave is initiated. At this time, PCIto
The PCI bridge determines whether the address of the access request destination is outside the block area, and if it is outside the block area, then the “retry register” as the second storage means.
It is determined whether the address does not match the address stored in.

When the address in the retry register does not match, the PCI to PCI bridge recognizes that the access request is an access to the primary PCI device and responds positively to the access request on the secondary PCI bus. At the same time, the access request is transmitted on the primary PCI bus.

However, since the request is actually an access request to the ISA device on the secondary side, and none of the PCI devices on the primary side responds, the PCI to PCI bridge causes the master cycle to abort the bus cycle on the PCI bus on the primary side. I have no choice. At this time, the PCI-to-PCI bridge saves the address of the access request destination in its own retry register and terminates the bus cycle on the secondary side PCI bus not by target abort but by retry.

Then, the secondary PCI device retries access to the secondary ISA device in response to the retry. At this time, the address of the access request destination matches the address in the retry register.
The toPCI bridge does not respond to access requests on this secondary PCI bus. Therefore, the access request is 1
Not transmitted on the secondary PCI bus.

On the other hand, since none of the positive devices on the secondary PCI bus responded to the access request, the PCI to ISA bridge responds to this access request subtractively. And PCI to ISA
The bridge transmits an access request on the secondary ISA bus, and the secondary ISA device to which the access is requested responds to this, thereby establishing the original normal bus cycle.

In brief, according to the present invention, a PC
Whatever device is connected to the secondary side of the ItoPCI bridge, the PCI bus cycle can be surely completed normally. Such an operation is realized by the cooperative operation of the retry, which is one of the PCI protocols, and the retry register implemented in the PCI to PCI bridge.

Further, according to the present invention, normal data transfer from the secondary PCI device to the secondary ISA device can be realized without burdening the software design. It should be fully understood that the present invention is very effective in standardizing the PCI to PCI bridge of the subtractive decoding method.

Further objects, features and advantages of the present invention are as follows.
It will be clarified by a more detailed description based on embodiments of the present invention described below and the accompanying drawings.

[0072]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings.

A. External Configuration of Computer System FIG. 1 shows an external configuration of a typical personal computer (PC) 100 suitable for implementing the present invention.

The PC 100 is a type called a "notebook" which is small and lightweight and has excellent portability. This kind of P
C is a so-called "clam shell" structure that is composed of the system main body 110 and a lid 120 that is pivotally supported at a substantially rear edge of the main body 110. The system body 110 is an external storage device such as a system board (not shown) mounted with a CPU and a memory chip, an HDD (hard disk drive), an FDD (floppy disk drive), and a CD-ROM drive. Built-in type (not shown). A keyboard unit 35 is arranged on the upper surface of the main body 110. One lid 120 has a liquid crystal display (LCD).
The unit 23 is buried. Opening this clam shell allows keyboard input and a view of the LCD display screen. Further, by closing the clam shell, the top surface of the keyboard 35 and the 23 display screen of the LCD can be covered inside, which is convenient for storage and carrying.

In this type of notebook PC 100, a function expansion unit 200 generally called a "docking station" is prepared. The docking station 200 has a substantially flat shape, and at least a part of its upper surface forms a mounting surface for receiving the notebook PC 100. Notebook PC 1 installed
00 and the docking station 200 are electrically connected to each other by the connector portions 100A and 200A provided therein, respectively, so that electric signals can be exchanged between them. This type of docking station 200 generally provides a "port proxy function" and a "bus expansion function". With port proxy function, external mouse / keyboard,
This is a function of providing the PC 100 with ports for cable connection of externally oriented peripheral devices such as an external CRT display and an external FDD. Further, the bus expansion function is a function of further extending the bus in the PC 100 (for example, PCI bus or ISA bus) to increase the number of devices or expansion slots that can be connected to the bus.

The docking station 200 itself is not directly related to the gist of the present invention. It should be understood to the extent that the secondary PCI bus is provided by docking station 200. For details of the docking station, for example, Japanese Patent Application No. 8-31699 (our reference number: JA995) assigned to the present applicant.
128). Further, in order to realize the present invention, it is not necessary to be a notebook PC, but other forms (for example, desktop type, tower type,
Laptop type).

B. Computer system hardware
(A) Configuration The hardware of the computer system that preferably realizes the present invention is a PCI-side primary bus that acts as a local bus of the host CPU, and a PCI-side primary bus is PCIto.
A secondary PCI bus connected via a PCI bridge,
The secondary PCI bus is a type having a multiple bus environment provided with a secondary ISA bus connected via a PCI to ISA bridge. Usually, each PCI bus and ISA bus has one or more PCI devices and ISs, respectively.
Device A is connected. In addition, PCI to PC
I-bridge is "Memory / IO Base / Li"
mit Register "function (" block function ":
More preferably, it is a type that supports both the above) and subtractive decoding operations (described above).

FIG. 2 schematically shows the hardware configuration of a personal computer (PC) 100 suitable for implementing the present invention. Hereinafter, each part will be described. The PCI device connected to the PCI bus by a black-colored bidirectional arrow is designed to perform a subtractive decoding operation with respect to the PCI bus.

The CPU 10, which is the main controller of the system 100, uses the operating system (O
Various programs are executed under the control of S). The CPU 10 is, for example, "Pe" manufactured by Intel Corp.
ntium / 1xxMHz "or" PowerPC 6xx "co-developed by IBM Corp. in the US. OS
Is, for example, "OS / 2"("OS / 2" is the US I
BM's trademark) and Microsoft's "Wind"
ows95 "is sufficient.

The external pins of the CPU 10 are host to PC
The I-bridge 11 connects to the primary PCI bus 20. The primary PCI bus 20 is interconnected to the secondary PCI bus 20 by a PCI to PCI bridge 21, and is also interconnected to the primary ISA bus 30 by a primary PCI to ISA bridge 31. Furthermore, the secondary PCI bus 40 is a secondary PCI to ISA.
The bridge 51 interconnects the secondary ISA bus 50. In other words, system 100 is a multiple bus configuration that includes one or more PCI buses 20,40 and ISA 30,50 buses. In addition, PCI and IS
The basic performance and characteristics of A are as described in the section [Prior Art].

Host-to-PCI bridge 11 of this embodiment
Includes a memory controller for controlling an access operation to the main memory 13 and a data buffer for absorbing a speed difference between the CPU 10 and the PCI bus 20.

The main memory 13 is a writable storage device used for loading each program (OS, application, etc.) executed by the CPU 10 and temporarily storing work data. Generally, a plurality of DRAs are provided.
It is composed of M chips. In addition to this, the system 100
A semiconductor memory device such as the L2 (Level 2 cache) 12 and the ROM 37 is included. L2 cache 13
It is a high-speed memory provided to temporarily store a part of frequently-used codes and data to absorb the time required for the CPU 10 to access the main memory 13, and normally an SRAM chip is used. Also, the ROM 37
Is a read-only memory for permanently storing a test program (POST) at power-on, a code group (BIOS) for hardware operation of each device in the system 100, and data necessary for system maintenance. Is.

The primary PCI bus 20 has a primary PCI
PCI to PCI bridge 21, video controller 22, PCMCIA controller 2 as devices
5, the primary side PCI to ISA bridge 31 and the like are connected.

The PCI to PCI bridge 21 is a chip for interconnecting the primary PCI bus 20 and the secondary PCI bus 40. PCI to PCI bridge 21
Is "PCI to PCI BRIDGE ARCHIT
ECTURE SPECIFICATION Revi
version 1.0 "(described above) and includes the configuration and operation characteristics peculiar to this embodiment, the details of which are C
It will be described later in the paragraphs and D.

The video controller 22 includes the CPU 10
Is a peripheral controller chip for actually processing the drawing command from the VRAM 2 and the processed drawing information is once written in the screen buffer (VRAM) 24.
4 is read out and the screen is output to the display 23.

The PCIMCIA controller 25 is a PC
This is a dedicated controller chip for directly connecting the signal line on the I bus 20 to the PC card slot. card·
PCMCIA (Personal Computer Memo)
ry Card International Association) / JEIDA (J
apan Electronic Industry Development Association)
Standards established by (eg "PC Card Specification 95")
It is possible to actively insert and remove the PC card 26 conforming to the above.

The primary side PCI to ISA bridge 31 is
It is a chip for interconnecting the primary PCI bus 20 and the primary ISA bus 30, and the transaction on one bus is appropriately expanded on the other bus. The PCI to ISA bridge 31 of this embodiment is also used.
Has a configuration including each function of a DMA controller, a programmable interrupt controller (PIC), and a programmable interval timer (PIT). Furthermore, the PCI to ISA bridge 31 is an IDE (Integr
Equipped with an IDE interface conforming to ated Drive Electronics). The IDE interface includes, for example, an IDE hard disk drive (HDD) 27.
And external storage devices such as an IDE CD-ROM are connected.

The PCI-to-PCI bridge 21 of this embodiment is designed for subtractive decoding on the primary PCI bus 20 in order to realize the present invention more preferably (described later). For this reason,
The primary PCI to ISA bridge 31 is forced to adopt the positive decoding method. However,
The ISA devices on the primary ISA bus 30 are standard equipment, and therefore the bridge 30 has all primary I
Since the system resources of the SA device are known in advance, a positive response is possible.

The primary ISA bus 32 has a primary ISA.
An I / O controller 32 as a device, a keyboard (KBD) / mouse controller (KMC) 34, etc. are connected.

The I / O controller 32 is a peripheral controller chip for realizing serial or parallel data exchange with an external device via a serial port or a parallel port. Generally, a modem (not shown) is connected to the serial port, and a printer (not shown) is connected to the parallel port. The I / O controller 32 of this embodiment also controls the drive of the floppy disk drive (FDD) 33.

The KMC 34 is a peripheral controller chip for taking in the input code from the keyboard 35 and the designated coordinate values from the mouse 36 as computer data and transmitting it on the bus 30.

The CPU 10, the primary PCI device, and the primary ISA device described above are provided as a standard host system in the notebook computer main body, for example. On the other hand, the secondary PCI bus 40, the secondary ISA bus 50, and the secondary PCI devices 42, 43 ... And the secondary ISA devices 52, 53. It is provided in the form of a docking station (described above).

The secondary PCI bus 40 is a PCI to PC.
The I-bridge 21 interconnects the primary PCI bus 20 (described above). P on the secondary PCI bus 40
In addition to the CI to PCI bridge 21, a PCI device 4
2, 43 ... and secondary side PCI to ISA bridge 51
Is connected as a secondary PCI device. The PCI-to-PCI bridge 21 of this embodiment is designed to be positively decoded on the secondary PCI bus 40.

An example of the PCI devices 42, 43 ... Is P
These are devices that require high-speed input / output operations such as a network subsystem connected via a CMCIA controller or a LAN adapter card, and a storage subsystem connected via a SCSI adapter card. It should be noted that the PCI devices 42, 43 ... May request access to other devices (including the secondary ISA device) as a PCI master (that is, an initiator) as needed.

The secondary side PCI to ISA bridge 51 is
It is a chip for interconnecting the secondary PCI bus 40 and the secondary ISA bus 50, and the transaction on one bus is appropriately expanded on the other bus. The PCI to ISA bridge 51 of this embodiment is also used.
Has a configuration including each function of a DMA controller, a programmable interrupt controller (PIC), and a programmable interval timer (PIT) (same as above).

The secondary ISA bus 50 has a secondary ISA.
ISA devices 52, 53, ... As devices are connected. An example of the ISA devices 42, 43 ...
It is an ISA compatible expansion adapter card installed in the A bus slot. The ISA devices 52, 53, ... May be requested as slaves (that is, targets) to the PCI master as required. In this case, the bus transaction is realized by relaying the secondary PCI to ISA bridge 51 (described later).

The secondary side PCI to ISA of the present embodiment.
The bridge 51 employs a subtractive decoding method. This is because the PnP-capable ISA device responds to the subtractive operation only when none of the PnP-capable PCI devices positively requests the bus cycle, and the bus cycle is given to the PnP-unsupported ISA device (described above). In addition, the secondary side PCI to ISA bridge 51
Is the secondary side ISA device 52, 53 ... Is the secondary side PCI
Since the area other than the usable address area of the device is used (see FIG. 12), it becomes the only secondary side PCI device that is decoded for access to areas other than the usable address area of the secondary side PCI device.

A typical user of personal computer 100 operates the system via keyboard 35 or mouse 36 to execute various applications such as word processing, spreadsheets, communications, etc. and to display screen (ie desktop). ) 23 can be used to carry out one's business.

The so-called personal computer currently on the market
The computer will function well as the computer system shown in FIG. It should be noted that many electric circuits and the like other than those shown in FIG. 2 are required to configure the computer system. However, since these are well known to those skilled in the art and do not constitute the gist of the present invention, they are omitted in the present specification. In addition, it should be noted that only a part of the connections between the hardware blocks in the drawing are shown in order to avoid complication of the drawing.

C. Internal Configuration of PCI to PCI Bridge The present invention is preferably implemented by modifying and improving the configuration and operating characteristics of the PCI to PCI bridge 21. In this section, the bridge chip 21 will be described in more detail.

FIG. 3 shows a PCI-to-PCI bridge 21.
Schematically illustrates the internal configuration of the. Hereinafter, each part will be described.

The primary side PCI interface 201 and the secondary side PCI interface 202 are respectively connected to the primary side P
This is a circuit for realizing data exchange between the CI bus 20 and the secondary PCI bus 40. Each of the interfaces 201 and 202 includes an I / O buffer (not shown) for temporarily holding address information, data information, commands and the like transmitted on the buses 20 and 40.

Primary side address command decoder 20
3, the primary side target state machine 204 and the secondary side master state machine 205 are the primary side PC
The bus cycle on the I bus 20 is changed to the secondary PCI bus 40.
It is a block to expand above. That is, the decoder 203 interprets the address information and the command information received by the interface 201 and interprets them on the primary PCI bus 2
Determine if the current transaction on 0 is an access to a secondary PCI device. And the decoder 2
If 03 is affirmative, state machine 204
Operates as a target on the primary PCI bus 20,
Next, the state machine 205 uses the secondary PCI bus 4
0 acts as a master. Target state
The operation of the machine 204 is, for example, the primary PCI bus 20.
The assertion of the device selection signal (P_DEVSEL #) above, and the operation of the master state machine 205 is, for example, the assertion of the frame signal (S_FRAME #) on the secondary PCI bus 40. The primary address / command decoder 203 of the present embodiment performs subtractive decoding (described above).

The secondary side address command decoder 208 and the secondary side target state machine 20
7, and the primary master state machine 206 has 2
The bus cycle on the secondary PCI bus 40 is set to the primary PCI.
This is a block for developing on the bus 20. That is, the decoder 208 interprets the address information and command information received by the interface 202, and analyzes the secondary side P
It is determined whether the current transaction on the CI bus 40 is an access to the primary PCI device. And
If the decoder 208 makes a positive determination, the state machine 207 acts as a target on the secondary PCI bus 40, and then the state machine 206 causes the primary P to pass.
It operates as a master on the CI bus 20. target·
The operation of the state machine 207 is, for example, a secondary PC
Device selection signal (S_DEVSEL on I-bus 40)
#) Is asserted and the master state machine 20
The operation 6 is, for example, assertion of the frame signal (P_FRAME #) on the primary PCI bus 20. The secondary address / command / decoder 2 of the present embodiment
08 decodes positively (described above).

The PCI configuration register 211, the comparator 209, and the retry FIFO control circuit 210 are composed of the primary side decoder 203 and the secondary side decoder 2.
It is a block that cooperates with 08 decoding work.

The PCI configuration register 211 includes a memory / IO base / limit address register 211A and a retry FIFO 211B. Of these, the memory / IO base / limit address register 211A is the term “prior art” (eg, paragraphs [0017] and [0018]).
As described with reference to FIG. 12, the memory address area and the I / O address area (that is, “block area”) which are allowed to be used only by the secondary PCI device are defined. And a base address and a limit address for each I / O address space are stored. The primary side decoder 203 is a memory / IO /
Only the base / limit address register 211A is referenced to determine whether the current transaction on the primary PCI bus 20 is an access request to the secondary PCI device. It should be understood that the memory / IO base / limit address register 211A constitutes, for example, the "first storage means" of [claim 9].

The retry FIFO 211B is a buffer for temporarily storing address information and the like relating to a transaction to be retried, and in the present embodiment, it is a first-in first-out type having a plurality of stages of buffers. FIG. 4 illustrates the configuration of the retry FIFO 211B in detail. In the figure, the FIFO buffer 211B is composed of four stages of buffers, but increasing or decreasing stages is only a design matter. Each buffer has an address field for storing an address value, a valid flag indicating whether the currently stored content is valid or invalid, and whether the stored address is a memory address or an I / O address. It includes an M / IO flag for indicating. The address field may be 32 bits long considering the address width of the PCI bus. Each valid flag and M / IO flag is 1
Just a bit. For example, if the valid flag is 0, the data is invalid, and if the valid flag is 1, the data is valid. If the M / IO flag is 0, it is an I / O address, and if it is 1, it is a memory address. The retry FIFO 211B is
For example, it should be understood that it constitutes the "second storage means" of [claim 9].

The retry FIFO control circuit 210 is a block for managing the write contents of the retry FIFO 211B. The retry FIFO control circuit 210 uses P
The CItoPCI bridge 21 itself is the secondary PCI bus 4
When the transaction on 0 is completed by retry, the address information related to the transaction is stored in the FIFO.
It is adapted to write to an available buffer in 211B. When all the stages of the retry FIFO 211B are full (FULL), old data is discarded because of new input.

The comparator 209 is a block which plays a part of the decoding work of the secondary side address command decoder 208. More specifically, the comparator 209 is
Memory / specified address on the next PCI bus 40
IO Base / Limit Address Register 211A
In comparison with the contents of the above, when it is outside the usable address area (that is, the block area) of the secondary PCI device,
Further, it is determined whether or not the address exists in the retry FIFO 211B. If retry FIFO21
If it does not exist in 1B, the secondary side decoder 208 judges that it is an access to the primary side PCI device and responds to this transaction. On the other hand, retry FIFO 211B
If it exists in the secondary side PCI device, the secondary side decoder 208 determines that the secondary side P is in the usable address area of the secondary side PCI device.
Judge that it is an access to the CI device and do not respond to this transaction.

FIG. 5 shows the PCI to PCI bridge 21.
The operating characteristics (particularly the part related to the gist of the present invention) are shown in the form of a state transition diagram. Hereinafter, each state will be described.

State 0: This state is when the power is turned on and when 2
It is in a state of waiting for an access request from the secondary PCI device. The retry FIFOs 211B when the power is turned on are all blank.

State 1: When a transaction occurs from the secondary PCI device, this state is entered. State 1
First, it is determined whether the address specified by the secondary PCI device is the usable address area of the secondary PCI device defined by the memory / IO base / limit address register 211A. Then, it is determined whether or not the designated address exists in the retry FIFO 211B. If at least one of these two conditions is satisfied, it is considered as an address hit, and the PCI to PCI bridge 21 proceeds to state 6. If neither condition is satisfied, it is considered as an address miss, and the process proceeds to state 2.

State 2: This state is an address miss, that is, a state determined to be a bus cycle to the primary PCI device. PCI to PCI bridge 2
1 as the master device generates the same transaction on the primary PCI bus 20. Any primary PC
If the I-device responds to the transaction, the bus cycle is established. It then returns to state 0 after the bus cycle is complete. On the other hand, any one within a predetermined time
If the secondary PCI device also does not respond, go to state 3.

State 3: This state is in response to a transaction generated by the PCI to PCI bridge 21 1
There is no secondary PCI device. At this time, PC
The ItoPCI bridge 21 causes the bus cycle to be master aborted on the primary PCI bus 20 and proceeds to state 4.

State 4: In this state, PCItoPCI
The bridge 21 temporarily ends the bus cycle on the secondary PCI bus 40 by a retry rather than the target abort, and proceeds to state 5.

State 5: In this state, PCItoPCI
The bridge 21 has address information (that is, address value and M / IO flag) related to the bus cycle to be retried.
Is written to the available buffer in the retry FIFO 211B and the buffer is validated. It will then return to state 0 and wait for the retry of the bus cycle that was temporarily terminated.

State 6: This state is an address hit,
That is, the bus cycle between the secondary PCI devices (more specifically, the secondary PCI to ISA bridge 5
Access to the secondary side ISA device via 1). If a retry access is attempted to the secondary ISA device, the secondary PCI
PCI device uses unusable address space
Since the to PCI bridge does not respond positively, a subtractive response by the secondary PCI to ISA bridge 51 becomes possible and the bus cycle is established.

D. From the secondary PCI device to the secondary IS
In other words, the present invention preferably realizes the fifth bus transaction in [Table 1] (described above), that is, the access operation from the secondary PCI device to the secondary ISA device. It was made. Up to the previous section, the hardware environment of the computer system 100 embodying the present invention has been described in detail. Therefore, in this section, an access operation from the secondary PCI device to the secondary ISA device under the hardware environment will be described.

In FIGS. 6 to 8, access is made from the secondary PCI device (master: tentatively PCI device 42) to the secondary ISA device (slave: tentatively ISA device 52). When, PCIto
It is shown in the form of a flow chart showing the operation of the PCI bridge 21. The operation will be described below with reference to the drawings.

When the main power of the system 100 is turned on (step S10), the system 100 becomes available after a predetermined sequence of self-diagnosis test and OS boot. In this state, the retry FIFO
211B are all initialized, that is, in a blank state (step S12).

The PCI-to-PCI bridge 21 is in a standby state until the transaction by the secondary PCI device is started (step S14). However, the 1st and 2nd transactions in [Table 1] are preferably executed by a well-known logic, but they are not directly related to the gist of the present invention and will not be described in detail here.

When a transaction by the secondary PCI device is started, the PCI to PCI bridge 21
Temporarily stores the address information and command information transmitted on the secondary PCI bus 40 in the I / O buffer (step S16). Then, it is determined whether the current bus cycle is a memory cycle or an I / O cycle based on the acquired command information (step S18). If it is a memory cycle, it is further determined whether or not the acquired address is within the range of the address area defined by the memory base register value and the memory limit register value (step S20A). If it is an I / O cycle, it is further determined whether the acquired address is within the address area defined by the I / O base register value and the I / O limit register value (step S).
20B). Then, in any of steps S20A and S20B, the base / limit register 211A
If it is within the range of the address area defined by, branch S22.
To B, and if it is outside the range, branch S22 to C.

Since the acquired address is within the range of the address area defined by the base / limit register 211A, the slave to which the access is requested is also the secondary side PC.
It is an I-device. Therefore, in this case, the PCI to PCI bridge 21 is connected to the secondary PCI.
Transactions on the bus 40 are transferred to the primary PCI bus 20.
To the end of the transaction on the secondary side PCI bus 40 (step S24). Then, after the transaction is completed, the process returns to step S14 and the same processing is repeated.

On the other hand, if the acquired address is outside the range of the address area defined by the base / limit register, first, the address has already been retried FIFO 211B.
It is determined whether or not it exists (step S30).

If the acquired address is the retry FIF
If it exists in O211B, the secondary ISA that failed once
Since this means retry of access to the device, the process proceeds to step S24, where the PCI to PCI bridge 21 does not respond positively to the transaction and waits for the transaction to end on the secondary PCI bus 40. As a result, the secondary PCI to ISA bridge 51 can respond to the transaction subtractively and acquire the bus cycle. The number of transactions on the secondary PCI bus 40 is 2
The secondary ISA device, which is developed on the secondary ISA bus 50, is actually accessed. After the transaction is completed, the process returns to step S14 and the same processing is repeated.

On the other hand, the acquired address is the retry FIF
If it does not exist in O211B, the PCI to PCI bridge 21 recognizes the access to the primary PCI bus 20 side, responds positively to the transaction, and waits for a bus cycle on the secondary PCI bus 40. The data is transmitted on the primary PCI bus 20 (step S3).
2). As a result of the PCI to PCI bridge 21 responding positively, the secondary side PCI to ISA bridge 5
1 loses the opportunity to respond to subtractive.

If the bus cycle transmitted on the primary PCI bus 20 actually requests access to the primary PCI device, the corresponding device is the primary P
By responding positively on the CI bus 20, the transaction will be successfully completed. However, although the access is actually to the secondary side ISA device, the bridge 21 illusion is an access to the primary side PCI device because it is outside the address area defined by the base / limit register 211A. If there is, no device responds on the primary PCI bus 21. In this case, the PCI to PCI bridge 21
Has no choice but to terminate the transaction abnormally by the master abort on the primary PCI bus 20 operating as the master (step S34). This master abort is the secondary PCI to I of the secondary PCI devices.
Note that only the SA bridge relies on having to respond to accesses outside the block area.

However, the PCI-to-PCI bridge 21 according to this embodiment is a secondary PCI that operates as a target.
On the bus 40, the transaction is temporarily ended by the retry instead of the target abort (step S36). Furthermore, PCI to PCI bridge 2
1 writes the address information and command information of the current transaction (that is, whether it is a memory cycle or an I / O cycle) to each field of the usable buffer of the retry FIFO 211B and sets the valid flag of the buffer (step S38). . Then, the process returns to step S14.

In response to the bus cycle ending with a retry, the master secondary PCI device retries the same transaction. Then, in this case, since the designated address exists in the retry FIFO 211B, the determination block S30 is branched to “Y”,
The transaction will end successfully.

9 and 10, the secondary PCI device (provisionally, the PCI device 42) is changed to the secondary ISA.
A transaction on the PCI buses 20 and 40 when a device (probably an ISA device 52) is being accessed is illustrated in the form of a time chart. In each figure, the prefix "P_" indicates a signal line in the primary side (that is, "Primary") PCI bus, and the prefix "S_" indicates the secondary side (that is, "Secondary") P.
Indicates a signal line in the CI bus. Also, in FIG. 9, signal lines with a superscript "*" as a suffix are PCI.
10 means that the signal line with a superscript "*" as a suffix in FIG. 10 is asserted by the secondary PCI to ISA bridge 51. The operation of each chart will be described below.

First, please refer to FIG. The secondary PCI device 42 as the master device is S_FRAME #
Indication of the start of a transaction by asserting. At this time, the PCI device 42 uses the S
Address to _AD [31: 0] and S_C / BE [3:
0] to each command. However, the address at this time is the secondary PCI defined in the register 211A.
It is outside the usable address area of the device.

Next, when the PCI device 42 becomes ready to send and receive data, S_IRDY # is asserted, and data is sent to S_AD [31: 0] and S_C /
The byte enable value is transmitted to BE [3: 0], respectively.

On the other hand, the PCI to PCI bridge 21
Since the specified address is outside the usable address area of the secondary PCI device, the transaction is recognized as an access request to the primary PCI device, and as a target on the secondary PCI bus 40, S_
Assert DEVSEL # and request a bus cycle for now. In addition, the PCI to PCI bridge 21
Generates the same bus cycle on the primary PCI bus 20 as a master or initiator. That is, the PCI to PCI bridge 21 has the P_FRAM
A transaction is started by asserting E #, P_IRDY # is asserted when data can be transmitted / received, and P_AD [31: 0] and P_C / BE [3: 0].
The same address / data and command / byte enable value are transmitted to each.

However, the recognition that the transaction is an access request to the primary PCI device is an illusion, and the actual target is the secondary IS of the access destination.
It is a secondary side PCI to ISA bridge 51 that relays the A device 52. In other words, the primary PCI bus 20
There are no slave devices on top to respond to the transaction. Therefore, the PCI to PCI bridge 20
After a lapse of a predetermined time, the bus cycle on the primary PCI bus 20 must be terminated by the master abort.
However, the PCI-to-PCI bridge 21 temporarily ends the bus cycle on the secondary PCI bus 40 operating as a target by retry instead of target abort. Further, the PCI-to-PCI bridge 21 writes the address information relating to this retry bus cycle in each field of the usable buffer of the retry FIFO 211B.

Reference is now made to FIG. The master that has received the retry, that is, the secondary PCI device 42,
Assert S_FRAME # to retry the transaction. Also, the PCI device 42 sends the same address and command as the previous time to S_AD [31: 0] and S_AD [31: 0].
_C / BE [3: 0]. Further, when the data can be transmitted / received, the PCI device 42
While asserting S_IRDY #, S_AD [3
1: 0] and S_C / BE [3: 0], respectively, transmitting data and byte enable values.

On the other hand, the PCI to PCI bridge 21
Although the specified address is outside the usable address area of the secondary PCI device, it has already been retried FIFO2.
Since the same address exists in 11B, the primary PC
Recognizing that it is not an access request to the I-device, it does not respond to the transaction.

As a result of none of the other secondary PCI devices responding positively, the secondary PCI to ISA bridge 51 is given the opportunity to subtractively decode. In other words, the secondary PCI to ISA bridge 51 uses the S_D at the subtractive timing.
That is, EVSEL # is asserted to request a bus cycle.

Secondary-side PCIt that won the bus cycle
The oISA bridge 51 further asserts S_TRDY # and converts the bus cycle to convert the secondary IS.
It is transmitted on the A bus 50. As a result, the transaction is transmitted to the secondary ISA device 52 which is the target, and the data is safely transferred between the secondary PCI device 42 which is the master and the secondary ISA device 52 which is the slave. .

E. Addendum The present invention has been described in detail above with reference to specific embodiments. However, it is obvious that those skilled in the art can modify or substitute the embodiments without departing from the scope of the present invention. That is, the present invention has been disclosed in the form of exemplification, and should not be limitedly interpreted.
In order to determine the gist of the present invention, the section of the claims described at the beginning should be taken into consideration.

[0140]

As described above in detail, according to the present invention,
Excellent method for controlling data transfer between buses in a data processing system including multiple buses, excellent bridging device for interconnecting buses to enable data transfer between buses, and multiple buses It is possible to provide an excellent data processing system including.

Further, according to the present invention, at least the first,
A data processing system including second and third buses, wherein devices on the second bus are assigned addresses within a predetermined range, and devices on other buses are assigned addresses outside the predetermined range. The excellent data transfer method between buses, the excellent bridge device for connecting the buses, and the excellent data processing system including a plurality of buses can be provided.

Further, according to the present invention, PCI to PCI
It is possible to provide an excellent method of transferring data between buses, a bridge device for connecting between buses, and a data processing system including a plurality of buses, which eliminates a combination of devices that cannot be accessed via a bridge.

Further, according to the present invention, the PCI bus and IS
In a data processing system having a bus environment in which an A bus is mixed, an excellent bus-to-bus data transfer method that enables a bus master on a certain bus to suitably access a bus slave, and a connection between buses It is possible to provide an excellent data processing system including a plurality of buses and an excellent bridge device for doing so.

Further, according to the present invention, a PC interconnected with another PCI bus by a PCI to PCI bridge.
In a data processing system having an I bus, an ISA bus, and a PCI to ISA bridge of a subtractive decoding type that interconnects a PCI bus and an ISA bus, a slave device in which a master device on the PCI bus operates subtractively An excellent data transfer method between buses that can be suitably accessed to
It is possible to provide an excellent bridge device for connecting between buses and an excellent data processing system including a plurality of buses.

It should be fully understood that the present invention is very effective in standardizing the PCI to PCI bridge of the subtractive decoding system.

[Brief description of drawings]

FIG. 1 is a diagram showing an external configuration of a typical personal computer (PC) 100 suitable for implementing the present invention.

FIG. 2 is a diagram schematically showing an internal hardware configuration of a personal computer (PC) 100 suitable for implementing the present invention.

FIG. 3 is a diagram schematically showing an internal configuration of a PCI to PCI bridge 21.

FIG. 4 is a diagram illustrating in detail a configuration of a retry FIFO 211B in the PCI to PCI bridge 21.

5 is a state transition diagram describing operating characteristics of a PCI to PCI bridge 21. FIG.

FIG. 6 is a diagram illustrating a secondary side PCI device to a secondary side IS.
PCI when access is being made to the A device
6 is a flowchart (part 1) showing the operation of the toPCI bridge 21.

FIG. 7 is a diagram showing a configuration of the secondary PCI device to the secondary IS.
PCI when access is being made to the A device
6 is a flowchart (part 2) showing the operation of the toPCI bridge 21.

FIG. 8 is a diagram illustrating a secondary side PCI device to a secondary side IS.
PCI when access is being made to the A device
7 is a flowchart (part 3) showing the operation of the toPCI bridge 21.

FIG. 9 is a diagram illustrating a secondary side PCI device to a secondary side IS.
PCI when access is being made to the A device
FIG. 4 is a diagram showing transactions on buses 20 and 40 in the form of a time chart.

FIG. 10 is a diagram illustrating P when a secondary PCI device is accessing a secondary ISA device.
FIG. 6 is a diagram showing transactions on the CI buses 20 and 40 in the form of a time chart.

FIG. 11 is a diagram showing a transaction on the PCI bus according to the subtractive decoding method (however,
7 is a timing chart showing a single write operation).

FIG. 12 is a diagram showing a PCI-to-PCI bridge “M”;
memory / IO Base / Limit Regis
It is the figure which showed typically the "ter" function using the I / O address map.

FIG. 13 is a diagram schematically showing a hardware configuration (conventional example) of a PC in which a PCI bus and an ISA bus are mixed.

FIG. 14 is a transaction on the primary and secondary PCI buses when an access request occurs from the secondary PCI device to the secondary ISA device (conventional example).
3 is a timing chart showing the above.

[Explanation of symbols]

10 ... CPU, 11 ... Host to PCI bridge, 12
... L2 cache, 13 ... Main memory, 20 ... Primary side PCI bus, 21 ... PCI to PCI bridge, 22
… Video controller, 23… Display, 24…
VRAM, 25 ... PCMCIA controller, 26 ... P
C card, 27 ... IDE HDD / CD-ROM, 30
... Primary ISA bus, 31 ... Primary PCI to ISA bridge, 32 ... I / O controller, 33 ... FDD, 3
4 ... KMC, 35 ... KBD, 36 ... Mouse, 37 ... RO
M, 40 ... Secondary PCI bus, 42, 43 ... Secondary PC
I device, 50 ... Secondary ISA bus, 51 ... Secondary P
CItoISA bridge, 52, 53 ... Secondary ISA device, 100 ... Computer system (PC).

Front page continuation (72) Inventor Ikuo Sho, 1623 Shimotsuruma, Yamato-shi, Kanagawa 14 Yamato Plant, IBM Japan, Ltd. (72) Hidenobu Hanami 1623 Shimotsuruma, Yamato, Kanagawa Prefecture 14 Japan BM Co., Ltd. Yamato Plant (56) References JP-A-5-12190 (JP, A) JP-A 8-339344 (JP, A) (58) Fields investigated (Int.Cl . ⁷ , DB name) G06F 13/36 310 G06F 13/36 510 G06F 13/12 330 G06F 13/14 320

Claims (8)

(57) [Claims] 1. A primary-side PCI bus, which acts as a local bus of a host CPU, and a P for connecting PCI buses to each other.
A secondary PCI bus interconnected with the primary PCI bus by a CItoPCI bridge, wherein a positive secondary PCI device on the secondary PCI bus uses an address within a range, and Next P
A primary PCI device and a subtractive secondary PCI device on a CI bus are methods for controlling data transfer between buses in a data processing system that uses an address outside the predetermined range. ) The first secondary side PCI device is the secondary side PCI device.
Initiating an access request to the subtractive second PCI device by asserting a frame signal on the bus; (b) the PCItoPCI bridge
Positively asserting a device selection signal on the I bus and initiating the access request on the primary PCI bus; and (c) all PCI devices on the primary PCI bus are set to 1 within a predetermined time. In response to not asserting the device selection signal of the secondary PCI bus, the PCI to P
The CI bridge holds the address of the access request destination and terminates the transaction on the secondary PCI bus in a retry format, and (d) in response to the retry, the first secondary PCI device Retrying the access request, and (e) the PCI to PCI bridge does not positively assert the device selection signal of the secondary side PCI bus when the address of the access request destination is the same as the held address, f) After all other secondary PCI devices have not positively asserted the device select signal, the second
And subtractively asserting a device selection signal of the secondary PCI bus of the secondary PCI device, the data transfer method between the buses. 2. A bridge device for interconnecting a primary PCI bus, which acts as a local bus of a host CPU, and a secondary PCI bus, comprising: (a) being connected to the secondary PCI bus. Secondary PCI
A first storage means for storing an address area in which only the device is permitted to use; and (b) a second storage means for storing the address information of the bus cycle ended by the retry by itself. c) primary side decoding means for judging an address hit when the address is within the usable address area of the secondary side PCI device defined by the first storage means, and (d) the primary side. Address by decoding means
First transmission means for transmitting a bus cycle on the primary side PCI bus to the secondary side PCI bus in response to a hit; and (e) an address defined by the first storage means. Only when the address is outside the usable address area of the secondary PCI device and does not exist in the second storage means,
Secondary side decoding means for judging a hit; (f) address by the secondary side decoding means
A second transmission means for transmitting a bus cycle on the secondary PCI bus to the primary PCI bus in response to a hit; and for connecting between the buses. Bridge device. 3. The bus connection according to claim 2 , wherein the primary side decoding means performs subtractive decoding and the secondary side decoding means performs positive decoding. Bridge device for. 4. A data processing system including a primary side PCI bus and a secondary side PCI bus that act as a local bus of a host CPU, wherein the primary side PCI bus and the secondary side PCI bus are claimed. 2. A data processing system including a plurality of buses, which is connected by the bridge device according to 2 . 5. A data processing system having a multiple bus structure, comprising: (a) a main processor that controls the overall operation of the system; (b) a main memory; and (c) a local processor of the main processor. A primary-side PCI bus connected as a bus, and (d) at least one connected to the primary-side PCI bus
One primary PCI device, (e) a secondary PCI bus, and (f) the primary PCI bus and the secondary PCI bus.
Secondary side interconnected and connected to the secondary PCI bus
Address area where only PCI device is allowed to use
The first storage means for remembering and ending by retrying itself
To store the address information of the completed bus cycle
And a PCI to PCI bridge device including
And is positive on the secondary PCI bus.
Decoding means for decoding, and the secondary PCI
Retried due to the fact that he / she finished the retry on the bus.
Suppress decoding for tried bus cycles
-ToPC including decoding suppressing means
An I-bridge device, and (g) at least one connected to the secondary PCI bus.
A data processing system including a plurality of buses, comprising: one secondary PCI device; 6. A data processing system having a multiple bus structure, comprising: (a) a main processor that controls the operation of the entire system; (b) a main memory; and (c) a local processor of the main processor. A first bus connected as a bus; (d) at least one first device connected to the first bus; (e) a second bus; (f) the first and second A bridge that interconnects the buses of (1), which does not request the retryed bus cycle again when the bus cycle ends with a retry, and (g) at least the second bus connected to the second bus. comprising one of the second device, wherein the bridge is connected to said second bus the second
Only the device in the memory stores the address area that is allowed to use.
The first storage means for me
A second for storing bus cycle address information
A data processing system including a plurality of buses, comprising: a storage means . 7. A data processing system having a multiple bus structure, comprising: (a) a main processor that controls the operation of the entire system; (b) a main memory; and (c) a local processor of the main processor. A primary-side PCI bus connected as a bus, and (d) at least one connected to the primary-side PCI bus
One of the primary PCI devices, a (e) and the secondary side PCI bus, (f) the primary PCI bus and PCItoPCI bridge interconnecting the secondary PCI bus, the
Of the secondary PCI device connected to the secondary PCI bus
First for storing only the address area that is allowed to use
Storage means and bus service that was terminated by retry
Second storage means for storing address information of icle
And a decoding means for positively decoding on the secondary PCI bus, and a decoding suppression for suppressing decoding for a bus cycle retried due to the fact that the device itself has completed a retry on the secondary PCI bus. A PCI-to-PCI bridge including: (g) at least one positive-decoding type secondary-side PCI device connected to the secondary-side PCI bus; and (h) connected to the secondary-side PCI bus. And only one secondary side P of the type for subtractive decoding
A CI device, and a data processing system including a plurality of buses. 8. A secondary-side PCI device (h) of the type for subtractive decoding is a secondary-side PC.
PCI to ISA for connecting ISA bus to I bus
A data processing system including a plurality of buses according to claim 7 , wherein the data processing system is a bridge.