JP3481477B2 - Interconnection network equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed processing method of an interconnection network mainly for performing data transfer between a processor device and a memory device of a parallel computer system.

[0002]

2. Description of the Related Art As such a conventional example, there is, for example, a "data processing device" described in JP-A-08-018565.

FIG. 4 is a block diagram showing an example of the prior art,
FIG. 5 is a timing chart showing the schematic operation thereof.

FIG. 4 shows a parallel computer system in which a plurality of processor units and a plurality of memory units are combined (two processors and two memories in this example), two input ports connected to the processor, and a memory connected. In the interconnection network consisting of two output ports, the input data is the control signal indicating the destination port at the first machine cycle and the data first packet, and the data once received the data second packet at the next machine cycle. There are two packet transfers per transfer.

The registers 52 and 53 for inputting destination address (RA) signals indicating the data transfer destinations from the respective input ports 50 and 51 and the destinations (output ports) from both input ports temporarily conflict with each other. RA buffers 58 and 59 for holding RA, RA buffer 58,
59 or selectors 62 and 63 for selecting the output of the input registers 52 and 53, registers 54 and 55 for inputting data from each input port, and a register 56 for waiting for the data first packet and the data second packet.
57, like the RA buffer, data buffers 60 and 61 for temporarily holding data when destinations from both input ports conflict, data input register 54
/ 56, 55/57 or selectors 64 and 65 for selecting the outputs of the data buffers 60 and 61 form the input ports. In addition, arbiters 66 and 67 that perform priority passage data determination control when destinations conflict, selectors 68 and 69 that select passage data from each input port, and a data buffer that temporarily holds data that has passed through this selector. 70, 71, again the first data every machine cycle,
The selectors 72 and 73 for folding into the second packet form an output port.

The timing chart shown in FIG. 5 shows input # 0.
Port 50 (data D0-1, 2) and input # 1 port 5
1 shows the operation when both input ports of 1 (data D1-1, 2) receive the transfer data to the output # 0 port 74 at the same timing. The control signal input at the same timing as the first packet of data has a 2-bit structure of a flag V indicating that the data packet is valid and RA indicating the destination of the data. Means data transfer to the output # 1 port.

With respect to the data received at each input port, the first packet waits for the second packet by the registers 56 and 57, and the contention arbitration between both ports is performed at the timing when the first and second packets are completed. The arbitration of the input data is controlled by the arbiter 66 on the output # 0 port side, which is the destination of each data. In this example, the data passing priority of the output # 0 port is the input # 0.
Data from the port shall take precedence. As a result of contention arbitration, the data D0-1 / input to the input # 0 port
2 passes through the selector 68 at 1T in the timing chart and loses the contention arbitration.
/ 2 is temporarily held in the data buffer 61 and passes through the selector 68 in the next machine cycle. The data passed through the selector 68 is held in the data buffer 70, and the selector 72 folds the data again into the first and second two packets, and the D0 is output from the # 0 output port 74 every machine cycle.
-1, D0-2, D1-1, D2-2 are output in this order.

[0008]

The first problem in the above-mentioned interconnection network is that when a series of data composed of a plurality of packets is received at an input port, the first data packet is delayed until the final data packet arrives. Wait for the data packets that arrive at the port and perform the port-to-port contention process only when all the data packets are ready. That is, there is a waiting cycle time from the arrival of the first data packet to the completion of the final data packet, and the waiting time increases as the number of data packet constituents increases.

The second problem is that the data sent from the output port has a plurality of packets as in the input port section. Inside the network, all data packets are recombined into one packet and passed through the data transfer selector between the input / output ports. That is, at most one data is transferred from each input port to one output port per machine cycle, while at the output port interface, the data obtained by combining all the packets into one is re-composed into the multiple packet configuration. It has to be refolded, and it takes as many machine cycles as the number of packet constituents to occupy the output port interface until a set of plural packet data is output. Therefore, this time becomes longer as the number of output data packet components increases. The above two factors are factors that reduce the throughput of the network.

[Object of the Invention] An object of the present invention is to configure a time-division multiple packet received by an input port in an interconnection network for controlling data transfer between a plurality of processor units and memory units in a parallel computer system. Is to improve the system performance by shortening the machine cycle time required to transfer the data to the target output port and improving the data transfer efficiency.

[0011]

The present invention is provided between a plurality of processor units and a plurality of memory units in a parallel computer system, and at least input from an input port connected to each processor or each memory unit. A state in which each packet of each data is divided in an interconnection network device that outputs one data first and the other data later when the output destinations of the data composed of the first and second packets compete with each other. A plurality of buffers that can be held by, a first selector provided across the input / output terminals of each buffer, and a second selector that selects mutual outputs of the first packet side selectors of the first selectors. A third selector for selecting outputs of the selectors on the second packet side among the first selectors, and the second or the third selector And a arbiter and registers to sequentially operate the selector, the first intermediate package of one of the data
Output the second packet of one of the data
The second packet of one of the above-mentioned data
Output the first packet of the other data at the same time as the power,
After outputting the first packet of the other data,
It is characterized by outputting a second packet of data . Further, the present invention is provided between at least a first packet and a second packet which are provided between a plurality of processor devices and a plurality of memory devices in a parallel computer system, and which are input from an input port connected to each processor or each memory device. In an interconnection network device that outputs one data first and the other data later when the output destinations of the data conflict with each other, in the input port for the number of the processor devices and the output ports for the number of the memory devices. when, F for outputting data in order assurance in chronological order when the data is <br/> input holds the data transmitted from the processor device to the respective input ports units
Bypasses the input buffer by the number of IFO-controlled data packet divisions, and when the data does not exist in the input buffer and the data input from another input port can preferentially pass the data. For controlling the data passage timing from the input destination address (output port address) to the output port and the selector corresponding to each input buffer, the data from multiple input ports tries to pass to the same output port. A data contention arbitration control unit (arbiter) corresponding to each output port for determining passage priority, and a data packet input from each input port based on the data contention arbitration result of the arbiter is selected, and every one machine cycle Data from each input port to the destination output port in divided packets Passed against the time-division data packet number of independent selector provided in plurality for each output port for forwarding to the destination output port, said
After outputting the first packet of one of the data,
While outputting the second packet of data,
At the same time as the output of the second packet of the data
The first packet is output via the output port, and the other
After outputting the first packet of data,
2 packets are output through the output port
To do .

[Operation] A data buffer for individually inputting a series of data packets, which are composed of a plurality of time-division packets received by each input port, in units of one packet for each machine cycle, is input to each input port. Data selection control between ports by contention arbitration processing of multiple packets is provided by the number of divisions, and by performing parallel control in time division by an independent selector circuit corresponding to each packet, the final data packet Keep the data packet that arrived earlier until
Compared with the method in which the inter-port contention process is performed for the first time when all the data packets are prepared, the transfer TAT increase due to the waiting cycle time from the arrival of the first data packet to the preparation of the last data packet is reduced.

In addition, since the interface of each output port is independently provided for each packet, the time required for each packet to occupy the output port interface corresponding to each packet before outputting one set of plural packet data. One machine cycle is enough. The number of data packets that can be output per unit time is the number of packets that make up one set of data, compared to the case where data of multiple packet configurations is output by multiplying the machine cycle by the number of packets using the interface for one packet. Doubled, it is possible to improve the throughput of the network.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Description of Configuration] Next, embodiments of the present invention will be described in detail with reference to the drawings. Figure 1
FIG. 1 is a diagram showing an example of a computer system configuration which is a target of the present invention, and shows two processor devices 000 and 10
0 and 2 shared by these two processors 000 and 100
1 shows a parallel computer system in which two memory devices 200 and 300 are connected via an interconnection network.

FIG. 2 is a detailed diagram of the interconnection network shown in FIG. 1, and FIG. 3 is a timing chart showing the operation timing. The interconnection network of this embodiment has an input port 001 corresponding to the processor 000 and a processor 100. Input port 101 corresponding to the, and output port 20 corresponding to the shared memory 200
1. It has an output port 301 corresponding to the shared memory 300. Further, the series of data transferred from each processor to the interconnection network is composed of two time-divided packets, the first packet and the second packet, and each input port has two packets per machine cycle. Machine cycles are input continuously.
The valid signal of the transfer data packet and the destination output port designation are input in synchronization with the first packet.

In FIG. 2, the registers 0 and 1 receive a data packet valid signal (valid: V) from the input ports 001 and 101 and a signal (routing address: RA) indicating a data destination output port as a data first packet. Input synchronously. When V is “1”, the routing address synchronously input, the data first packet and the data second packet input in the next machine cycle are valid. If the routing address is “0”, the data packet is output port 201 ( Shared memory 200),
"1" means that the data is transferred to the output port 301 (shared memory 300). Register 2,
3 sequentially inputs the first data packet and the second data packet received by each input port.

That is, at the timing when "10" is set in the register 0, the shared memory 20 is stored in the register 2.
The first packet of request data for accessing 0 is input, and the second packet of request data is input to the register 2 in the next machine cycle.

Next, the RA buffers 4 and 5 are connected to the output port 2
Arbiter 12, which is the request contention arbitration circuit on the 01 side,
In the arbiter 13, which is a request conflict arbitration circuit on the output port 301 side, when requests from both input ports to the same output port compete at the same time, the request of the register 0 or 1 that was given the priority pass right due to the conflict is lost. This is a buffer for temporary storage. R
Similar to the A buffers 4 and 5, the first packet data buffers 6 and 7 out of the two packet configuration data when the requests directed to the same output port in the arbiter 12 or the arbiter 13 compete and the passage priority is not given. It is a buffer for temporarily storing the first data packet. The second packet data buffers 14 and 15 are buffers dedicated to the data second packet similar to the buffers 6 and 7, and the operation timing is delayed by one machine cycle of the buffers 6 and 7 (data input time of the first and second packets). Operation).

The selectors 8 and 9 select the output signals 0-0 and 1-0 of the registers 0 and 1 when there is no request stored in the RA buffers 4 and 5, and bypass the RA buffers 4 and 5. And sends the routing addresses of the registers 0 and 1 to the arbiter 12 or 13. In addition,
Registers 0, 1, RA buffers 4, 5 and selectors 8, 9
The order of sending requests to the arbiters 12 and 13 from the selectors 8 and 9 of the input buffer unit composed of
Guarantee the request input order of 1.

On the other hand, the selectors 10 and 11 select the output signals 2-0 and 3-0 of the registers 2 and 3 when the data stored in the first packet data buffers 6 and 7 does not exist, and the first packet The data selector 16 or 17 for bypassing the data buffers 6 and 7 and transferring the data of the first packet existing in the registers 2 and 3 between the input / output ports
Send to. The order of sending the requests to the selectors 16 and 17 is the FIFO of the first packet data buffers 6 and 7.
By controlling, the request input order of the registers 2 and 3 is guaranteed. Similarly, the selectors 18 and 19 output signals 2-0 and 3-0 of the registers 2 and 3 when the data stored in the second packet data buffers 14 and 15 does not exist.
To bypass the second packet data buffers 14 and 15 and send the data of the second packet existing in the registers 2 and 3 to the data selector 22 or 23 for transfer between input / output ports. The request transmission order to the selectors 22 and 23 is the second packet data buffers 14 and 15
The FIFO control ensures the request input order of the registers 2 and 3, and the selector control has an operation timing delayed by one machine cycle from the selectors 10 and 11 on the first packet side.

The arbiter 12 is a circuit for controlling the passage priority of the data packets transferred from the # 0 input port and the # 1 input port to the # 0 output port, and outputs the signal 8-0 and the signal 8-0 output from the selector 8. The signal 9-0 which is the output of the selector 9 is input and a signal 12-0 for controlling the selection of the data packet from the # 0 input port or the # 1 input port is generated from those values. In the contention arbitration control of this embodiment, when request data from both input ports are to be simultaneously transferred to the # 0 output port, # 0
Request data from the input port shall be passed preferentially.

However, in order to eliminate the bias between the ports, the request data from the # 1 input port which has lost the competition is preferentially passed in the next machine cycle. Of course, if there is only request data from one of the input ports, that data will pass.

The arbiter 13 is a circuit for controlling the passage priority of data packets transferred from the # 0 input port and the # 1 input port to the # 1 output port. The signal 9-0 which is the output of the selector 9 is input and the signal 13-0 for controlling the selection of the data packet from the # 0 input port or the # 1 input port is generated from those values.

In the contention arbitration control of this embodiment, when request data from both input ports are simultaneously transferred to the # 1 output port, the request data from the # 1 input port is preferentially passed. .

However, in order to eliminate the bias between the ports, the request data from the # 0 input port which has lost the competition is preferentially passed in the next machine cycle. Of course, if there is only request data from one of the input ports, that data will pass. As described above, the arbiter 12 and the arbiter 13 change the data priority passage order of the respective output ports to maintain the fairness of the priority order among the ports at the time of request conflict as a whole.

The selector 16 outputs the output signal 1 of the arbiter 12.
Either the first packet 10-0 of data transferred from the # 0 input port to the # 0 output port by 2-0 or the first packet 11-0 of data transferred from the # 1 input port to the # 0 output port. The first packet data from both input ports can be selectively switched for each machine cycle. The selector 17 outputs the first packet 10-0 of data transferred from the # 0 input port to the # 1 output port according to the output signal 13-0 of the arbiter 13 or the first packet 10-0 of data transferred from the # 1 input port to the # 1 output port. It is a selector for selecting either one of the packets 11-0, and it is possible to selectively switch the first packet data from both input ports for each machine cycle.

The selector 22 outputs the output signal 2 of the register 20.
Either the second packet 18-0 of data transferred from the # 0 input port to the # 0 output port by 0-0 or the second packet 19-0 of the data transferred from the # 1 input port to the # 0 output port. The second packet data from both input ports can be selectively switched for each machine cycle. The selector 23 outputs the second packet 18-0 of data transferred from the # 0 input port to the # 1 output port according to the output signal 21-0 of the register 21 or the second packet 18-0 of data transferred from the # 1 input port to the # 1 output port. It is a selector for selecting either of the two packets 19-0, and selectively switches the second packet data from both input ports every machine cycle at a timing delayed by one machine cycle from the selector 16.

The data first and second packets transferred to the # 0 output port selected by the selectors 16 and 22 are transmitted through the registers 24 and 26 to the # 0 output ports 201-0 and 201-1 corresponding to the memory 200. The first packet and the second packet are sent out every machine cycle, and the data transferred to the # 1 output port selected by the selectors 17 and 23 are stored in the memory via the registers 25 and 27. # 0 output port 301 corresponding to 300-
No. 1 from 0, 301-1 every machine cycle
The packet and the second packet are transmitted.

Further, instead of the registers 24, 25, 26, 27, a buffer capable of storing a plurality of data similar to that used in the data input section is provided, so that the memory device can be connected to the interconnection network. When there is busy control (request data unacceptable period), the data is temporarily held in the buffer so that the inter-port data selectors 16, 17, 22, 23 are busy (when an output port is It becomes possible to reduce the number of times that a request going to the busy port becomes busy and the data going to the other output port that follows cannot be swept).

[Explanation of Operation] Next, referring to the timing chart of FIG. 3, an example is given in which the # 0 input port and the # 1 input port simultaneously receive two consecutive request data to the # 0 output port. The specific operation will be described below.

The request data D0-1 received by the # 0 input port 001 is input to the registers 0 and 2, and the request data D received by the # 1 input port at the same timing.
1-1 is input to the registers 1 and 3. The routing addresses received by both input ports are both "0" and #
0 Indicates that the data is the transfer data to the output port. The RA buffers 4, 5, the first packet data buffers 6, 7, and the second packet data buffers 14, 15 are all empty.

The arbiter 12 performs request contention arbitration and preferentially passes the data D0-1 of the # 0 input port through the selector 16 by the arbiter output signal 12-0. The lost D1-1 is held in the first packet data buffer 7 and passes through the selector 16 in the next machine cycle. Data D2-1 received by the subsequent # 0 input port,
The same operation control is performed for the D3-1 received by the # 1 input port, and the data D0-1, D1-1, D2-1, and D3-1 are output in this order via the register 24 for each machine cycle. Data is transferred from -0 to the memory 200.

On the other hand, the second packet data is delayed by one machine cycle from the processing of the first packet data, and the register 2,
Pass 3. As for the second packet data received by each input port, the second packet D0-2 of the # 0 input port passes through the selector 22 in the same manner as the first packet by the output signal 20-0 of the register 20, and the data D1- of the # 1 output port. 2 is held in the second packet data buffer 15 and passes through the selector 22 in the next machine cycle. The same operation control is performed for the data D2-2 received by the subsequent # 0 input port and D3-2 received by the # 1 input port, and the data D0- is transmitted via the register 26 every machine cycle.
Output port 2 in the order of 2, D1-2, D2-2, D3-2
01-1 from the output port 201-0
Data is transferred to the memory 200 with a delay of one machine cycle from the packet.

In the embodiment described above, the processor 000,
Although the present invention relates to the network configuration for the data going from the shared memory 200, 300 to the shared memory 200, 300, the data transfer network configuration from the shared memory 200, 300 to the processor 000, 100 is also input port 0.
It is only necessary that 01 and 101 correspond to the shared memories 200 and 300 and the output ports 201 and 301 correspond to the processors 000 and 001, respectively, and the control method is the same as the above description.

[0035]

EFFECTS OF THE INVENTION Data buffers 6, 7, 14, 15 for independently inputting a series of data packets, which are composed of a plurality of time-division packets received by each input port, in units of one packet for each machine cycle. Are provided for each input port by the number of packet divisions, and data select control between ports by contention arbitration processing of a plurality of packets is performed in divided packet units by an independent selector circuit corresponding to each packet of the selectors 16, 22, 17, 23. By performing time-division parallel control, the first packet is made to wait until the second packet arrives, and the inter-port contention processing is performed for the first time at the timing when two packets are aligned.
The transfer TAT increase due to the waiting cycle time from the arrival of the first packet to the completion of the second packet can be reduced.

In addition, the interface of each output port is set to the packet unit 201-0, 201-1, 301-0, 3
By providing them independently like 01-1, it takes only one machine cycle for each packet to occupy the output port interface corresponding to each packet before outputting one set of plural packet data.

The number of data packets that can be output per unit time constitutes one set of data, as compared with the case where data of a plurality of packet configurations is output by multiplying the machine cycle by the number of packets using the interface for one packet. The number of packets that can be transmitted is doubled, and network throughput can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a computer system configuration which is a target of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is an operation timing chart in the embodiment of FIG.

FIG. 4 is a block diagram showing a conventional technique.

5 is an operation timing chart of the conventional technique of FIG.

[Explanation of symbols]

000,100 Processor 200,300 Shared memory 001,101 Input port 201,301 Output port 0,1,2,3,20,21,24,25,26,27
Registers 4, 5, 6, 7, 14, 15 Buffers 8, 9, 10, 11, 16, 17, 18, 19, 22,
23 selector 12, 13 arbiter 50, 51 input port 74, 75 output port 52-0, 52-1, 53-0, 53-1, 54, 5
5, 56, 57 registers 58, 59, 60, 61, 70, 71 buffers 62, 63, 64, 65, 68, 69, 72, 73
selector

Claims (7)

(57) [Claims] 1. A parallel computer system comprising at least first and second packets which are provided between a plurality of processor devices and a plurality of memory devices and which are input from an input port connected to each processor or each memory device. In an interconnection network device that outputs one data first and the other data later when the data output destinations conflict, a plurality of buffers that can hold each packet of each data in a divided state A first selector provided across the input / output terminals of the buffers; a second selector that selects mutual outputs of the first packet side selectors of the first selectors; and a first selector of the first selectors. A third selector that selects the outputs of the selectors on the two-packet side and the second or third selector are sequentially operated. And a arbiter and a register that, the one from the output of the first packet of the one data
Output the second packet of the other data, and
At the same time that the second packet of data of
The first packet of the other data is output and the first packet of the other data is output.
Output the second packet of the other data.
An interconnection network device characterized by the ability to operate . 2. The interconnection network device according to claim 1, wherein the input port is provided for a memory device and the output port is provided for a processor device. 3. The input port is compatible with a processor device,
The interconnection network device according to claim 1, wherein the output port is provided for a memory device. 4. A parallel computer system, which is provided between a plurality of processor devices and a plurality of memory devices, and comprises at least first and second packets input from an input port connected to each processor or each memory device. When the data output destinations conflict, in an interconnection network device that outputs one data first and the other data later, with an input port for the number of processor devices and an output port for the number of memory devices , an input buffer of the data packet number of divisions of by order guarantee FIFO control for outputting data in chronological order when the data holds the data is input to be transmitted from the processor device to the respective input port, the input There is no data in the buffer and the data is input from another input port. Controls the data transfer timing from the input destination address (output port address) to the output port, and the selector corresponding to each input buffer to bypass the input buffer when the data can be passed preferentially At the same time, when data from multiple input ports try to pass to the same output port, a data contention arbitration control unit (arbiter) corresponding to each output port for determining the priority of passage.
Then, the data packet input from each input port is selected based on the arbiter data contention arbitration result, and the data from each input port is passed to the destination output port in packet units for each machine cycle. , For each output port for transfer to the destination output port, an independent selector is provided for the number of time-divided data packets , and the first packet of the one data is output and then
Output the second packet of the other data, and
At the same time that the second packet of data of
Output the first packet of the
Output the first packet of one data and then the other data
An interconnection network device, characterized in that the second packet is output via an output port . 5. The interconnection network device according to claim 4, wherein each data packet output interface section of the output port has a memory device connected to the output port in a busy period (data unacceptable) like the input port section. An interconnection network device, wherein a FIFO-controlled data buffer for temporarily holding a plurality of data packets during a period) is provided. 6. The interconnection network device according to claim 4, wherein the input port is provided for a memory device and the output port is provided for a processor device. 7. The input port is compatible with a processor device,
6. The interconnection network device according to claim 4, wherein the output port is provided for a memory device.